Updates for clock changes.
--HG-- extra : convert_revision : 88699ba98a738a62204ae4182f7ee5dcab9285eb
This commit is contained in:
Kevin Lim
parent
7f39291c81
commit
71b6499c12
40 changed files with 286 additions and 294 deletions
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@ -12,7 +12,7 @@ physmem=system.physmem
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[system.cpu]
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type=AtomicSimpleCPU
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children=workload
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clock=1
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clock=500
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cpu_id=0
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defer_registration=false
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function_trace=false
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@ -47,7 +47,7 @@ progress_interval=0
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system=system
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cpu_id=0
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workload=system.cpu.workload
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clock=1
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clock=500
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phase=0
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defer_registration=false
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width=1
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@ -1,13 +1,13 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 713136 # Simulator instruction rate (inst/s)
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host_mem_usage 148308 # Number of bytes of host memory used
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host_seconds 2088.68 # Real time elapsed on the host
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host_tick_rate 713136 # Simulator tick rate (ticks/s)
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host_inst_rate 687229 # Simulator instruction rate (inst/s)
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host_mem_usage 149588 # Number of bytes of host memory used
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host_seconds 2167.42 # Real time elapsed on the host
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host_tick_rate 343614381 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1489514860 # Number of instructions simulated
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sim_seconds 0.001490 # Number of seconds simulated
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sim_ticks 1489514859 # Number of ticks simulated
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sim_seconds 0.744757 # Number of seconds simulated
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sim_ticks 744757429500 # Number of ticks simulated
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 1489514860 # number of cpu cycles simulated
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@ -2,6 +2,5 @@ warn: More than two loadable segments in ELF object.
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warn: Ignoring segment @ 0xb4000 length 0x10.
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warn: More than two loadable segments in ELF object.
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warn: Ignoring segment @ 0x0 length 0x0.
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0: system.remote_gdb.listener: listening for remote gdb on port 7000
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warn: Entering event queue @ 0. Starting simulation...
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warn: Ignoring request to flush register windows.
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@ -36,9 +36,9 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Mar 21 2007 00:46:54
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M5 started Wed Mar 21 00:47:20 2007
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M5 compiled Apr 27 2007 14:35:32
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M5 started Fri Apr 27 14:35:40 2007
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M5 executing on zizzer.eecs.umich.edu
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command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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Exiting @ tick 1489514859 because target called exit()
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Exiting @ tick 744757429500 because target called exit()
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@ -12,7 +12,7 @@ physmem=system.physmem
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[system.cpu]
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type=TimingSimpleCPU
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children=dcache icache l2cache toL2Bus workload
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clock=1
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clock=500
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cpu_id=0
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defer_registration=false
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function_trace=false
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@ -47,7 +47,7 @@ progress_interval=0
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system=system
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cpu_id=0
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workload=system.cpu.workload
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clock=1
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clock=500
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phase=0
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defer_registration=false
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// width not specified
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@ -1,41 +1,41 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 531377 # Simulator instruction rate (inst/s)
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host_mem_usage 154376 # Number of bytes of host memory used
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host_seconds 2803.12 # Real time elapsed on the host
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host_tick_rate 1212716 # Simulator tick rate (ticks/s)
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host_inst_rate 510352 # Simulator instruction rate (inst/s)
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host_mem_usage 155048 # Number of bytes of host memory used
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host_seconds 2918.60 # Real time elapsed on the host
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host_tick_rate 353062922 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1489514860 # Number of instructions simulated
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sim_seconds 0.003399 # Number of seconds simulated
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sim_ticks 3399390003 # Number of ticks simulated
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sim_seconds 1.030450 # Number of seconds simulated
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sim_ticks 1030449926500 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 2848.782706 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1848.782706 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency 2729.300186 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1729.300186 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 551182478 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency 528065000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 357702478 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency 334585000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_avg_miss_latency 3103.285714 # average SwapReq miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2103.285714 # average SwapReq mshr miss latency
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system.cpu.dcache.SwapReq_avg_miss_latency 3071.428571 # average SwapReq miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2071.428571 # average SwapReq mshr miss latency
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system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
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system.cpu.dcache.SwapReq_miss_latency 21723 # number of SwapReq miss cycles
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system.cpu.dcache.SwapReq_miss_latency 21500 # number of SwapReq miss cycles
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system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
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system.cpu.dcache.SwapReq_mshr_miss_latency 14723 # number of SwapReq MSHR miss cycles
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system.cpu.dcache.SwapReq_mshr_miss_latency 14500 # number of SwapReq MSHR miss cycles
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system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 3023.717816 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2023.717816 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency 2724.587576 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1724.587576 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 166586897 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 785395584 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency 707698000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 259745 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 525650584 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency 447953000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 259745 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 2949.038694 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency
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system.cpu.dcache.demand_avg_miss_latency 2726.599371 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 1726.599371 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 568905105 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 1336578062 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency 1235763000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 453225 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 883353062 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency 782538000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 453225 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 2949.038694 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_miss_latency 2726.599371 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 1726.599371 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 568905105 # number of overall hits
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system.cpu.dcache.overall_miss_latency 1336578062 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency 1235763000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 453225 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 883353062 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency 782538000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 453225 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
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system.cpu.dcache.replacements 449136 # number of replacements
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system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4068.114109 # Cycle average of tags in use
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system.cpu.dcache.tagsinuse 4095.694265 # Cycle average of tags in use
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system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 33495000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.warmup_cycle 112631000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 316447 # number of writebacks
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system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 3979.992714 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 2979.992714 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_miss_latency 3687.613843 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 2687.613843 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 4370032 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency 4049000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 3272032 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency 2951000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 3979.992714 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency
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system.cpu.icache.demand_avg_miss_latency 3687.613843 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 2687.613843 # average overall mshr miss latency
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system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 4370032 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency 4049000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
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system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 3272032 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency 2951000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 3979.992714 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency
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system.cpu.icache.overall_avg_miss_latency 3687.613843 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 2687.613843 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 1489513763 # number of overall hits
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system.cpu.icache.overall_miss_latency 4370032 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency 4049000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
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system.cpu.icache.overall_misses 1098 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 3272032 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency 2951000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
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system.cpu.icache.replacements 115 # number of replacements
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system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 865.251814 # Cycle average of tags in use
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system.cpu.icache.tagsinuse 891.763656 # Cycle average of tags in use
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system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadReq_accesses 454330 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 3215.864263 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1941.261615 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency 2631.120103 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1629.899651 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 427145 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 87423270 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency 71527000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.059835 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 27185 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 52773197 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_latency 44308822 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.059835 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 27185 # number of ReadReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses)
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@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3215.864263 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2631.120103 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1629.899651 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 427145 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 87423270 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 71527000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.059835 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 27185 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 52773197 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 44308822 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.059835 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 27185 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 770777 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3214.799956 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2630.249320 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1629.899651 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 743583 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 87423270 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 71527000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.035281 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 27194 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 52773197 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 44308822 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.035270 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 27185 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 2632 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 27185 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 23773.580402 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 24268.399126 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 743583 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 2531 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 3399390003 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1030449926500 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1489514860 # Number of instructions executed
|
||||
system.cpu.num_refs 569359656 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -2,6 +2,5 @@ warn: More than two loadable segments in ELF object.
|
|||
warn: Ignoring segment @ 0xb4000 length 0x10.
|
||||
warn: More than two loadable segments in ELF object.
|
||||
warn: Ignoring segment @ 0x0 length 0x0.
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Ignoring request to flush register windows.
|
||||
|
|
|
|||
|
|
@ -36,9 +36,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 29 2007 03:54:03
|
||||
M5 started Thu Mar 29 03:54:23 2007
|
||||
M5 compiled Apr 27 2007 14:35:32
|
||||
M5 started Fri Apr 27 14:35:40 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 3399390003 because target called exit()
|
||||
Exiting @ tick 1030449926500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 624449 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 148644 # Number of bytes of host memory used
|
||||
host_seconds 2753.78 # Real time elapsed on the host
|
||||
host_tick_rate 624449 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 658093 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 149896 # Number of bytes of host memory used
|
||||
host_seconds 2613.00 # Real time elapsed on the host
|
||||
host_tick_rate 329046277 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1719594534 # Number of instructions simulated
|
||||
sim_seconds 0.001720 # Number of seconds simulated
|
||||
sim_ticks 1719594533 # Number of ticks simulated
|
||||
sim_seconds 0.859797 # Number of seconds simulated
|
||||
sim_ticks 859797266500 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1719594534 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -2,6 +2,5 @@ warn: More than two loadable segments in ELF object.
|
|||
warn: Ignoring segment @ 0xa2000 length 0x10.
|
||||
warn: More than two loadable segments in ELF object.
|
||||
warn: Ignoring segment @ 0x0 length 0x0.
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Ignoring request to flush register windows.
|
||||
|
|
|
|||
|
|
@ -25,9 +25,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 23 2007 22:37:06
|
||||
M5 started Fri Mar 23 22:37:22 2007
|
||||
M5 compiled Apr 27 2007 14:35:32
|
||||
M5 started Fri Apr 27 15:11:49 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 1719594533 because target called exit()
|
||||
Exiting @ tick 859797266500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 446147 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 154148 # Number of bytes of host memory used
|
||||
host_seconds 3854.32 # Real time elapsed on the host
|
||||
host_tick_rate 13681801 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 462859 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 155288 # Number of bytes of host memory used
|
||||
host_seconds 3715.16 # Real time elapsed on the host
|
||||
host_tick_rate 345995852 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1719594534 # Number of instructions simulated
|
||||
sim_seconds 0.052734 # Number of seconds simulated
|
||||
sim_ticks 52734070003 # Number of ticks simulated
|
||||
sim_seconds 1.285430 # Number of seconds simulated
|
||||
sim_ticks 1285429818500 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 607807189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3420.154300 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2420.154300 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3129.930590 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2129.930590 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 594739458 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 44693656366 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 40901091000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.021500 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 13067731 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 31625925366 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 27833360000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.021500 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 13067731 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 15448 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 3631.818182 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2631.818182 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 3090.909091 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2090.909091 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 15437 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 39950 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 34000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.000712 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 11 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 28950 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 23000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000712 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 11 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 166970997 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3255.499606 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2255.499606 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 2764.531806 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1764.531806 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 165264000 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 5557128061 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 4719047500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010223 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1706997 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3850131061 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3012050500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010223 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1706997 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 774778186 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3401.130933 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3087.714271 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2087.714271 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 760003458 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 50250784427 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 45620138500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.019070 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 14774728 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 35476056427 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 30845410500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.019070 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 14774728 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 774778186 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3401.130933 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3087.714271 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2087.714271 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 760003458 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 50250784427 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 45620138500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.019070 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 14774728 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 35476056427 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 30845410500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.019070 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 14774728 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 14770643 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 14774739 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4094.978951 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4094.607725 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 760018895 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 35437000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 1932183000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 4191356 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 1719594535 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 4032.295228 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3032.295228 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3753.607103 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2753.607103 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1719593634 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 3633098 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 3382000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2732098 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2481000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1719594535 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 4032.295228 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3753.607103 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2753.607103 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1719593634 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 3633098 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 3382000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 901 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 2732098 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 2481000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 1719594535 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 4032.295228 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3753.607103 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2753.607103 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1719593634 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 3633098 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 3382000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 901 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 2732098 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 2481000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 31 # number of replacements
|
||||
system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 750.163929 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 737.434314 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1719593634 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 14775639 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 3097.556051 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1926.730191 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2607.028468 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1605.780536 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 8592784 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 19151739918 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 16118879000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.418449 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 6182855 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 11912693395 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 9928308213 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.418449 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 6182855 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 4191356 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 14775639 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3097.556051 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2607.028468 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1605.780536 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 8592784 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 19151739918 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 16118879000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.418449 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 6182855 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 11912693395 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9928308213 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.418449 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 6182855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 18966995 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3083.976361 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2595.599252 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1605.780536 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 12756915 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 19151739918 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 16118879000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.327415 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 6210080 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 11912693395 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9928308213 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.325980 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 6182855 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 6150087 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 6182855 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 27594.660688 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 26097.875810 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 12756915 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 12316534000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.warmup_cycle 390549075000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1069081 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 52734070003 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1285429818500 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1719594534 # Number of instructions executed
|
||||
system.cpu.num_refs 774793634 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 632 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -2,6 +2,5 @@ warn: More than two loadable segments in ELF object.
|
|||
warn: Ignoring segment @ 0xa2000 length 0x10.
|
||||
warn: More than two loadable segments in ELF object.
|
||||
warn: Ignoring segment @ 0x0 length 0x0.
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Ignoring request to flush register windows.
|
||||
|
|
|
|||
|
|
@ -25,9 +25,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 29 2007 15:41:48
|
||||
M5 started Thu Mar 29 15:42:11 2007
|
||||
M5 compiled Apr 27 2007 14:35:32
|
||||
M5 started Fri Apr 27 15:24:20 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 52734070003 because target called exit()
|
||||
Exiting @ tick 1285429818500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 638506 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 150340 # Number of bytes of host memory used
|
||||
host_seconds 213.38 # Real time elapsed on the host
|
||||
host_tick_rate 638505 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 644632 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 151548 # Number of bytes of host memory used
|
||||
host_seconds 211.36 # Real time elapsed on the host
|
||||
host_tick_rate 322315545 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 136246936 # Number of instructions simulated
|
||||
sim_seconds 0.000136 # Number of seconds simulated
|
||||
sim_ticks 136246935 # Number of ticks simulated
|
||||
sim_seconds 0.068123 # Number of seconds simulated
|
||||
sim_ticks 68123467500 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 136246936 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object.
|
|||
warn: Ignoring segment @ 0x1838c0 length 0x10.
|
||||
warn: More than two loadable segments in ELF object.
|
||||
warn: Ignoring segment @ 0x0 length 0x0.
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Ignoring request to flush register windows.
|
||||
warn: ignoring syscall time(4026527856, 4026528256, ...)
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 21 2007 00:48:18
|
||||
M5 started Wed Mar 21 00:48:40 2007
|
||||
M5 compiled Apr 27 2007 14:35:32
|
||||
M5 started Fri Apr 27 15:55:23 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 136246935 because target called exit()
|
||||
Exiting @ tick 68123467500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 473146 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 156372 # Number of bytes of host memory used
|
||||
host_seconds 287.96 # Real time elapsed on the host
|
||||
host_tick_rate 4801122 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 466766 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 157052 # Number of bytes of host memory used
|
||||
host_seconds 291.90 # Real time elapsed on the host
|
||||
host_tick_rate 335938336 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 136246936 # Number of instructions simulated
|
||||
sim_seconds 0.001383 # Number of seconds simulated
|
||||
sim_ticks 1382530003 # Number of ticks simulated
|
||||
sim_seconds 0.098059 # Number of seconds simulated
|
||||
sim_ticks 98059078500 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3575.086285 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2575.086285 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3241.706786 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2241.706786 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 162627100 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 147462000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 117138100 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 101973000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 3413.933333 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2413.933333 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 3166.666667 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2166.666667 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 51209 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 47500 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 36209 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 32500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 4579.703729 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3579.703729 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3588.938331 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2588.938331 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 481665760 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 377463000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 376491760 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 272289000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 4276.384116 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3484.100277 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2484.100277 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 644292860 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 524925000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 493629860 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 374262000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 4276.384116 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3484.100277 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2484.100277 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 57944942 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 644292860 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 524925000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 150663 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 493629860 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 374262000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 146582 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4060.510189 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4090.058697 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 33018000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 224414000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 107279 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2909.600795 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1909.600795 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2800.327765 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1800.327765 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 544165179 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 523728500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 357141179 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 336704500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 2909.600795 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 2800.327765 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 1800.327765 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 544165179 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 523728500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 357141179 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 336704500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 2909.600795 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 2800.327765 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 1800.327765 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 136059913 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 544165179 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 523728500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 187024 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 357141179 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 336704500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 184976 # number of replacements
|
||||
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1952.728312 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 2008.440865 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 1000315000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.warmup_cycle 69827484000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 3564.034868 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1961.482636 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2644.770157 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1643.366085 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 480000652 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 356195000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 264170520 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 221326901 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3564.034868 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2644.770157 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1643.366085 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 480000652 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 356195000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 264170520 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 221326901 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3550.642088 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2634.831752 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1643.366085 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 309728 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 480000652 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 356195000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 135187 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 264170520 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 221326901 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 101911 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 30685.350019 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 32141.182824 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 319451000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.warmup_cycle 20627583000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 82918 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1382530003 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 98059078500 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 136246936 # Number of instructions executed
|
||||
system.cpu.num_refs 58111522 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object.
|
|||
warn: Ignoring segment @ 0x1838c0 length 0x10.
|
||||
warn: More than two loadable segments in ELF object.
|
||||
warn: Ignoring segment @ 0x0 length 0x0.
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Ignoring request to flush register windows.
|
||||
warn: ignoring syscall time(4026527856, 4026528256, ...)
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 29 2007 03:55:17
|
||||
M5 started Thu Mar 29 03:55:38 2007
|
||||
M5 compiled Apr 27 2007 14:35:32
|
||||
M5 started Fri Apr 27 15:58:57 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 1382530003 because target called exit()
|
||||
Exiting @ tick 98059078500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 676464 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 149916 # Number of bytes of host memory used
|
||||
host_seconds 285.95 # Real time elapsed on the host
|
||||
host_tick_rate 676463 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 668374 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 150556 # Number of bytes of host memory used
|
||||
host_seconds 289.41 # Real time elapsed on the host
|
||||
host_tick_rate 334186387 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 193435973 # Number of instructions simulated
|
||||
sim_seconds 0.000193 # Number of seconds simulated
|
||||
sim_ticks 193435972 # Number of ticks simulated
|
||||
sim_seconds 0.096718 # Number of seconds simulated
|
||||
sim_ticks 96717986000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 193435973 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object.
|
|||
warn: Ignoring segment @ 0x11e394 length 0x10.
|
||||
warn: More than two loadable segments in ELF object.
|
||||
warn: Ignoring segment @ 0x0 length 0x0.
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Ignoring request to flush register windows.
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -18,11 +18,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 12 2007 16:53:49
|
||||
M5 started Mon Mar 12 17:37:07 2007
|
||||
M5 compiled Apr 27 2007 14:35:32
|
||||
M5 started Fri Apr 27 16:03:50 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic
|
||||
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
|
||||
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 193435972 because target called exit()
|
||||
Exiting @ tick 96717986000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 471554 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 155352 # Number of bytes of host memory used
|
||||
host_seconds 410.21 # Real time elapsed on the host
|
||||
host_tick_rate 766692 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 490451 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 156012 # Number of bytes of host memory used
|
||||
host_seconds 394.40 # Real time elapsed on the host
|
||||
host_tick_rate 342594746 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 193435973 # Number of instructions simulated
|
||||
sim_seconds 0.000315 # Number of seconds simulated
|
||||
sim_ticks 314505003 # Number of ticks simulated
|
||||
sim_seconds 0.135121 # Number of seconds simulated
|
||||
sim_ticks 135120940500 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3705.925703 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2705.925703 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3786.144578 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2786.144578 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1845551 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 1885500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1347551 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1387500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 3995 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2995 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 3500 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 3995 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 3500 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 2995 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 2500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3678.678637 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2678.678637 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3587.016575 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2587.016575 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 3995045 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 3895500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2909045 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2809500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3687.244949 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3649.621212 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 5840596 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 5781000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4256596 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4197000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3687.244949 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3649.621212 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 76708968 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 5840596 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 5781000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1584 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4256596 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4197000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 26 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1216.403972 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 1237.515646 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 23 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3138.680633 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2138.680633 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3066.269971 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2066.269971 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 38505334 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 37617000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 26237334 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 25349000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3138.680633 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3066.269971 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 38505334 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 37617000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 26237334 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 25349000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3138.680633 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3066.269971 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 193423706 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 38505334 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 37617000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 12268 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 26237334 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 25349000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 10342 # number of replacements
|
||||
system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1567.271345 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1591.858190 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2847.598413 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1846.400619 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2720.824463 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1719.824463 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14713541 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14058500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 9540352 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 8886333 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -174,29 +174,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2847.598413 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2720.824463 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 14713541 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 14058500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9540352 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 8886333 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2847.598413 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2720.824463 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 8708 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 14713541 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 14058500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 5167 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9540352 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 8886333 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -213,12 +213,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 3448.701925 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 3507.285738 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 314505003 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 135120940500 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 193435973 # Number of instructions executed
|
||||
system.cpu.num_refs 76732959 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 396 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object.
|
|||
warn: Ignoring segment @ 0x11e394 length 0x10.
|
||||
warn: More than two loadable segments in ELF object.
|
||||
warn: Ignoring segment @ 0x0 length 0x0.
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Ignoring request to flush register windows.
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -18,11 +18,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 29 2007 16:12:35
|
||||
M5 started Thu Mar 29 16:13:01 2007
|
||||
M5 compiled Apr 27 2007 14:35:32
|
||||
M5 started Fri Apr 27 16:08:41 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
|
||||
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
|
||||
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 314505003 because target called exit()
|
||||
Exiting @ tick 135120940500 because target called exit()
|
||||
|
|
|
|||
Loading…
Reference in a new issue