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Cache: add a response latency to the caches

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In the current caches the hit latency is paid twice on a miss. This patch lets
a configurable response latency be set of the cache for the backward path.
This commit is contained in:
Mrinmoy Ghosh 2012-09-25 11:49:41 -05:00
parent 74ab69c7ea
commit 6fc0094337
32 changed files with 180 additions and 86 deletions
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12
configs/common/Caches.py
View file

@ -31,7 +31,8 @@ from m5.objects import *
class L1Cache(BaseCache): class L1Cache(BaseCache):
assoc = 2 assoc = 2
block_size = 64 block_size = 64
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
mshrs = 10 mshrs = 10
tgts_per_mshr = 20 tgts_per_mshr = 20
is_top_level = True is_top_level = True
@ -39,14 +40,16 @@ class L1Cache(BaseCache):
class L2Cache(BaseCache): class L2Cache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 20 mshrs = 20
tgts_per_mshr = 12 tgts_per_mshr = 12
class PageTableWalkerCache(BaseCache): class PageTableWalkerCache(BaseCache):
assoc = 2 assoc = 2
block_size = 64 block_size = 64
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
mshrs = 10 mshrs = 10
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12
@ -55,7 +58,8 @@ class PageTableWalkerCache(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

12
configs/common/O3_ARM_v7a.py
View file

@ -147,7 +147,8 @@ class O3_ARM_v7a_3(DerivO3CPU):
# Instruction Cache # Instruction Cache
# All latencys assume a 1GHz clock rate, with a faster clock they would be faster # All latencys assume a 1GHz clock rate, with a faster clock they would be faster
class O3_ARM_v7a_ICache(BaseCache): class O3_ARM_v7a_ICache(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 2 mshrs = 2
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -158,7 +159,8 @@ class O3_ARM_v7a_ICache(BaseCache):
# Data Cache # Data Cache
# All latencys assume a 1GHz clock rate, with a faster clock they would be faster # All latencys assume a 1GHz clock rate, with a faster clock they would be faster
class O3_ARM_v7a_DCache(BaseCache): class O3_ARM_v7a_DCache(BaseCache):
latency = '2ns' hit_latency = '2ns'
response_latency = '2ns'
block_size = 64 block_size = 64
mshrs = 6 mshrs = 6
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -170,7 +172,8 @@ class O3_ARM_v7a_DCache(BaseCache):
# TLB Cache # TLB Cache
# Use a cache as a L2 TLB # Use a cache as a L2 TLB
class O3_ARM_v7aWalkCache(BaseCache): class O3_ARM_v7aWalkCache(BaseCache):
latency = '4ns' hit_latency = '4ns'
response_latency = '4ns'
block_size = 64 block_size = 64
mshrs = 6 mshrs = 6
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -183,7 +186,8 @@ class O3_ARM_v7aWalkCache(BaseCache):
# L2 Cache # L2 Cache
# All latencys assume a 1GHz clock rate, with a faster clock they would be faster # All latencys assume a 1GHz clock rate, with a faster clock they would be faster
class O3_ARM_v7aL2(BaseCache): class O3_ARM_v7aL2(BaseCache):
latency = '12ns' hit_latency = '12ns'
response_latency = '12ns'
block_size = 64 block_size = 64
mshrs = 16 mshrs = 16
tgts_per_mshr = 8 tgts_per_mshr = 8

4
src/mem/cache/BaseCache.py vendored
View file

@ -36,7 +36,9 @@ class BaseCache(MemObject):
type = 'BaseCache' type = 'BaseCache'
assoc = Param.Int("associativity") assoc = Param.Int("associativity")
block_size = Param.Int("block size in bytes") block_size = Param.Int("block size in bytes")
latency = Param.Latency("Latency") hit_latency = Param.Latency("The hit latency for this cache")
response_latency = Param.Latency(
"Additional cache latency for the return path to core on a miss");
hash_delay = Param.Cycles(1, "time in cycles of hash access") hash_delay = Param.Cycles(1, "time in cycles of hash access")
max_miss_count = Param.Counter(0, max_miss_count = Param.Counter(0,
"number of misses to handle before calling exit") "number of misses to handle before calling exit")

3
src/mem/cache/base.cc vendored
View file

@ -69,7 +69,8 @@ BaseCache::BaseCache(const Params *p)
writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,
MSHRQueue_WriteBuffer), MSHRQueue_WriteBuffer),
blkSize(p->block_size), blkSize(p->block_size),
hitLatency(p->latency), hitLatency(p->hit_latency),
responseLatency(p->response_latency),
numTarget(p->tgts_per_mshr), numTarget(p->tgts_per_mshr),
forwardSnoops(p->forward_snoops), forwardSnoops(p->forward_snoops),
isTopLevel(p->is_top_level), isTopLevel(p->is_top_level),

10
src/mem/cache/base.hh vendored
View file

@ -229,7 +229,15 @@ class BaseCache : public MemObject
/** /**
* The latency of a hit in this device. * The latency of a hit in this device.
*/ */
int hitLatency; const Tick hitLatency;
/**
* The latency of sending reponse to its upper level cache/core on a
* linefill. In most contemporary processors, the return path on a cache
* miss is much quicker that the hit latency. The responseLatency parameter
* tries to capture this latency.
*/
const Tick responseLatency;
/** The number of targets for each MSHR. */ /** The number of targets for each MSHR. */
const int numTarget; const int numTarget;

6
src/mem/cache/builder.cc vendored
View file

@ -71,7 +71,7 @@ using namespace std;
#if defined(USE_CACHE_FALRU) #if defined(USE_CACHE_FALRU)
#define BUILD_FALRU_CACHE do { \ #define BUILD_FALRU_CACHE do { \
FALRU *tags = new FALRU(block_size, size, latency); \ FALRU *tags = new FALRU(block_size, size, hit_latency); \
BUILD_CACHE(FALRU, tags); \ BUILD_CACHE(FALRU, tags); \
} while (0) } while (0)
#else #else
@ -80,7 +80,7 @@ using namespace std;
#if defined(USE_CACHE_LRU) #if defined(USE_CACHE_LRU)
#define BUILD_LRU_CACHE do { \ #define BUILD_LRU_CACHE do { \
LRU *tags = new LRU(numSets, block_size, assoc, latency); \ LRU *tags = new LRU(numSets, block_size, assoc, hit_latency); \
BUILD_CACHE(LRU, tags); \ BUILD_CACHE(LRU, tags); \
} while (0) } while (0)
#else #else
@ -124,7 +124,7 @@ BaseCacheParams::create()
iic_params.blkSize = block_size; iic_params.blkSize = block_size;
iic_params.assoc = assoc; iic_params.assoc = assoc;
iic_params.hashDelay = hash_delay; iic_params.hashDelay = hash_delay;
iic_params.hitLatency = latency; iic_params.hitLatency = hit_latency;
iic_params.rp = repl; iic_params.rp = repl;
iic_params.subblockSize = subblock_size; iic_params.subblockSize = subblock_size;
#else #else

16
src/mem/cache/cache_impl.hh vendored
View file

@ -897,8 +897,11 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
transfer_offset += blkSize; transfer_offset += blkSize;
} }
// If critical word (no offset) return first word time // If critical word (no offset) return first word time.
completion_time = tags->getHitLatency() + // responseLatency is the latency of the return path
// from lower level caches/memory to an upper level cache or
// the core.
completion_time = responseLatency +
(transfer_offset ? pkt->finishTime : pkt->firstWordTime); (transfer_offset ? pkt->finishTime : pkt->firstWordTime);
assert(!target->pkt->req->isUncacheable()); assert(!target->pkt->req->isUncacheable());
@ -911,11 +914,16 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
assert(target->pkt->cmd == MemCmd::StoreCondReq || assert(target->pkt->cmd == MemCmd::StoreCondReq ||
target->pkt->cmd == MemCmd::StoreCondFailReq || target->pkt->cmd == MemCmd::StoreCondFailReq ||
target->pkt->cmd == MemCmd::SCUpgradeFailReq); target->pkt->cmd == MemCmd::SCUpgradeFailReq);
completion_time = tags->getHitLatency() + pkt->finishTime; // responseLatency is the latency of the return path
// from lower level caches/memory to an upper level cache or
// the core.
completion_time = responseLatency + pkt->finishTime;
target->pkt->req->setExtraData(0); target->pkt->req->setExtraData(0);
} else { } else {
// not a cache fill, just forwarding response // not a cache fill, just forwarding response
completion_time = tags->getHitLatency() + pkt->finishTime; // responseLatency is the latency of the return path
// from lower level cahces/memory to the core.
completion_time = responseLatency + pkt->finishTime;
if (pkt->isRead() && !is_error) { if (pkt->isRead() && !is_error) {
target->pkt->setData(pkt->getPtr<uint8_t>()); target->pkt->setData(pkt->getPtr<uint8_t>());
} }

6
tests/configs/inorder-timing.py
View file

@ -33,7 +33,8 @@ m5.util.addToPath('../configs/common')
class MyCache(BaseCache): class MyCache(BaseCache):
assoc = 2 assoc = 2
block_size = 64 block_size = 64
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
mshrs = 10 mshrs = 10
tgts_per_mshr = 5 tgts_per_mshr = 5
@ -43,7 +44,8 @@ class MyL1Cache(MyCache):
cpu = InOrderCPU(cpu_id=0) cpu = InOrderCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
MyL1Cache(size = '256kB'), MyL1Cache(size = '256kB'),
MyCache(size = '2MB', latency='10ns')) MyCache(size = '2MB', hit_latency='10ns',
response_latency='10ns'))
cpu.clock = '2GHz' cpu.clock = '2GHz'

6
tests/configs/memtest.py
View file

@ -34,7 +34,8 @@ from m5.objects import *
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 12 mshrs = 12
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -46,7 +47,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8

3
tests/configs/o3-timing-checker.py
View file

@ -42,7 +42,8 @@ m5.util.addToPath('../configs/common')
class MyCache(BaseCache): class MyCache(BaseCache):
assoc = 2 assoc = 2
block_size = 64 block_size = 64
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
mshrs = 10 mshrs = 10
tgts_per_mshr = 5 tgts_per_mshr = 5

6
tests/configs/o3-timing-mp.py
View file

@ -35,7 +35,8 @@ m5.util.addToPath('../configs/common')
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 20 tgts_per_mshr = 20
@ -47,7 +48,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8

3
tests/configs/o3-timing.py
View file

@ -33,7 +33,8 @@ m5.util.addToPath('../configs/common')
class MyCache(BaseCache): class MyCache(BaseCache):
assoc = 2 assoc = 2
block_size = 64 block_size = 64
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
mshrs = 10 mshrs = 10
tgts_per_mshr = 5 tgts_per_mshr = 5

12
tests/configs/pc-o3-timing.py
View file

@ -39,7 +39,8 @@ mem_size = '128MB'
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 20 tgts_per_mshr = 20
@ -51,7 +52,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -62,7 +64,8 @@ class L2(BaseCache):
class PageTableWalkerCache(BaseCache): class PageTableWalkerCache(BaseCache):
assoc = 2 assoc = 2
block_size = 64 block_size = 64
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
mshrs = 10 mshrs = 10
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12
@ -73,7 +76,8 @@ class PageTableWalkerCache(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

12
tests/configs/pc-simple-atomic.py
View file

@ -39,7 +39,8 @@ mem_size = '128MB'
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -51,7 +52,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -62,7 +64,8 @@ class L2(BaseCache):
class PageTableWalkerCache(BaseCache): class PageTableWalkerCache(BaseCache):
assoc = 2 assoc = 2
block_size = 64 block_size = 64
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
mshrs = 10 mshrs = 10
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12
@ -74,7 +77,8 @@ class PageTableWalkerCache(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

12
tests/configs/pc-simple-timing.py
View file

@ -40,7 +40,8 @@ mem_size = '128MB'
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -52,7 +53,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -63,7 +65,8 @@ class L2(BaseCache):
class PageTableWalkerCache(BaseCache): class PageTableWalkerCache(BaseCache):
assoc = 2 assoc = 2
block_size = 64 block_size = 64
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
mshrs = 10 mshrs = 10
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12
@ -74,7 +77,8 @@ class PageTableWalkerCache(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

9
tests/configs/realview-o3-checker.py
View file

@ -46,7 +46,8 @@ import FSConfig
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 20 tgts_per_mshr = 20
@ -58,7 +59,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -69,7 +71,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

9
tests/configs/realview-o3-dual.py
View file

@ -37,7 +37,8 @@ from Benchmarks import *
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 20 tgts_per_mshr = 20
@ -49,7 +50,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -60,7 +62,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

9
tests/configs/realview-o3.py
View file

@ -37,7 +37,8 @@ import FSConfig
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 20 tgts_per_mshr = 20
@ -49,7 +50,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -60,7 +62,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

9
tests/configs/realview-simple-atomic-dual.py
View file

@ -37,7 +37,8 @@ from Benchmarks import *
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -49,7 +50,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -60,7 +62,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

9
tests/configs/realview-simple-atomic.py
View file

@ -36,7 +36,8 @@ import FSConfig
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -48,7 +49,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -59,7 +61,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

9
tests/configs/realview-simple-timing-dual.py
View file

@ -37,7 +37,8 @@ from Benchmarks import *
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -49,7 +50,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -60,7 +62,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

9
tests/configs/realview-simple-timing.py
View file

@ -37,7 +37,8 @@ import FSConfig
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -49,7 +50,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -60,7 +62,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

6
tests/configs/simple-atomic-mp.py
View file

@ -34,7 +34,8 @@ from m5.objects import *
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -46,7 +47,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8

6
tests/configs/simple-timing-mp.py
View file

@ -34,7 +34,8 @@ from m5.objects import *
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -46,7 +47,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8

5
tests/configs/simple-timing.py
View file

@ -32,7 +32,8 @@ from m5.objects import *
class MyCache(BaseCache): class MyCache(BaseCache):
assoc = 2 assoc = 2
block_size = 64 block_size = 64
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
mshrs = 10 mshrs = 10
tgts_per_mshr = 5 tgts_per_mshr = 5
@ -42,7 +43,7 @@ class MyL1Cache(MyCache):
cpu = TimingSimpleCPU(cpu_id=0) cpu = TimingSimpleCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
MyL1Cache(size = '256kB'), MyL1Cache(size = '256kB'),
MyCache(size = '2MB', latency='10ns')) MyCache(size = '2MB', hit_latency='10ns', response_latency ='10ns'))
system = System(cpu = cpu, system = System(cpu = cpu,
physmem = SimpleMemory(), physmem = SimpleMemory(),
membus = CoherentBus()) membus = CoherentBus())

9
tests/configs/tsunami-inorder.py
View file

@ -37,7 +37,8 @@ import FSConfig
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -49,7 +50,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -60,7 +62,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

9
tests/configs/tsunami-o3-dual.py
View file

@ -37,7 +37,8 @@ import FSConfig
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 20 tgts_per_mshr = 20
@ -49,7 +50,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -60,7 +62,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

9
tests/configs/tsunami-o3.py
View file

@ -37,7 +37,8 @@ import FSConfig
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 20 tgts_per_mshr = 20
@ -49,7 +50,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -60,7 +62,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

9
tests/configs/tsunami-simple-atomic-dual.py
View file

@ -36,7 +36,8 @@ import FSConfig
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -48,7 +49,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -59,7 +61,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

9
tests/configs/tsunami-simple-atomic.py
View file

@ -36,7 +36,8 @@ import FSConfig
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -48,7 +49,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -59,7 +61,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

9
tests/configs/tsunami-simple-timing-dual.py
View file

@ -36,7 +36,8 @@ import FSConfig
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -48,7 +49,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -59,7 +61,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12

9
tests/configs/tsunami-simple-timing.py
View file

@ -37,7 +37,8 @@ import FSConfig
# ==================== # ====================
class L1(BaseCache): class L1(BaseCache):
latency = '1ns' hit_latency = '1ns'
response_latency = '1ns'
block_size = 64 block_size = 64
mshrs = 4 mshrs = 4
tgts_per_mshr = 8 tgts_per_mshr = 8
@ -49,7 +50,8 @@ class L1(BaseCache):
class L2(BaseCache): class L2(BaseCache):
block_size = 64 block_size = 64
latency = '10ns' hit_latency = '10ns'
response_latency = '10ns'
mshrs = 92 mshrs = 92
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
@ -60,7 +62,8 @@ class L2(BaseCache):
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64
latency = '50ns' hit_latency = '50ns'
response_latency = '50ns'
mshrs = 20 mshrs = 20
size = '1kB' size = '1kB'
tgts_per_mshr = 12 tgts_per_mshr = 12