6fc0094337
In the current caches the hit latency is paid twice on a miss. This patch lets a configurable response latency be set of the cache for the backward path.
67 lines
3.4 KiB
Python
67 lines
3.4 KiB
Python
# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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from m5.params import *
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from m5.proxy import *
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from MemObject import MemObject
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from Prefetcher import BasePrefetcher
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class BaseCache(MemObject):
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type = 'BaseCache'
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assoc = Param.Int("associativity")
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block_size = Param.Int("block size in bytes")
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hit_latency = Param.Latency("The hit latency for this cache")
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response_latency = Param.Latency(
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"Additional cache latency for the return path to core on a miss");
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hash_delay = Param.Cycles(1, "time in cycles of hash access")
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max_miss_count = Param.Counter(0,
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"number of misses to handle before calling exit")
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mshrs = Param.Int("number of MSHRs (max outstanding requests)")
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prioritizeRequests = Param.Bool(False,
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"always service demand misses first")
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repl = Param.Repl(NULL, "replacement policy")
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size = Param.MemorySize("capacity in bytes")
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forward_snoops = Param.Bool(True,
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"forward snoops from mem side to cpu side")
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is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)")
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subblock_size = Param.Int(0,
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"Size of subblock in IIC used for compression")
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tgts_per_mshr = Param.Int("max number of accesses per MSHR")
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trace_addr = Param.Addr(0, "address to trace")
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two_queue = Param.Bool(False,
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"whether the lifo should have two queue replacement")
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write_buffers = Param.Int(8, "number of write buffers")
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prefetch_on_access = Param.Bool(False,
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"notify the hardware prefetcher on every access (not just misses)")
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prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
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cpu_side = SlavePort("Port on side closer to CPU")
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mem_side = MasterPort("Port on side closer to MEM")
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addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port")
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system = Param.System(Parent.any, "System we belong to")
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