Fix the caches not working in the regression
src/python/m5/objects/BaseCPU.py: Make mem parameter a MemObject, not just a PhysicalMemory Fix a reference not using self tests/configs/simple-atomic.py: Set the mem paramter tests/configs/simple-timing.py: Set the mem parameter --HG-- extra : convert_revision : 6bd9df36831a1c5bafc9e88ab945c2ebe91db785
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3329f6f639
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@ -6,7 +6,7 @@ from Bus import Bus
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class BaseCPU(SimObject):
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class BaseCPU(SimObject):
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type = 'BaseCPU'
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type = 'BaseCPU'
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abstract = True
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abstract = True
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mem = Param.PhysicalMemory(Parent.any, "memory")
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mem = Param.MemObject(Parent.any, "memory")
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system = Param.System(Parent.any, "system object")
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system = Param.System(Parent.any, "system object")
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if build_env['FULL_SYSTEM']:
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if build_env['FULL_SYSTEM']:
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@ -43,11 +43,12 @@ class BaseCPU(SimObject):
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self.icache_port = ic.cpu_side
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self.icache_port = ic.cpu_side
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self.dcache_port = dc.cpu_side
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self.dcache_port = dc.cpu_side
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self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
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self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
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# self.mem = dc
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
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self.addPrivateSplitL1Caches(ic, dc)
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self.addPrivateSplitL1Caches(ic, dc)
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self.toL2Bus = Bus()
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self.toL2Bus = Bus()
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self.connectMemPorts(self.toL2Bus)
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self.connectMemPorts(self.toL2Bus)
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self.l2cache = l2c
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self.l2cache = l2c
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self.l2cache.cpu_side = toL2Bus.port
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self.l2cache.cpu_side = self.toL2Bus.port
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self._mem_ports = ['l2cache.mem_side']
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self._mem_ports = ['l2cache.mem_side']
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@ -34,5 +34,6 @@ system = System(cpu = AtomicSimpleCPU(),
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membus = Bus())
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membus = Bus())
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system.physmem.port = system.membus.port
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system.physmem.port = system.membus.port
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system.cpu.connectMemPorts(system.membus)
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system.cpu.connectMemPorts(system.membus)
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system.cpu.mem = system.physmem
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root = Root(system = system)
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root = Root(system = system)
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@ -39,7 +39,7 @@ class MyCache(BaseCache):
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cpu = TimingSimpleCPU()
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cpu = TimingSimpleCPU()
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cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
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cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
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MyCache(size = '2MB'))
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MyCache(size = '2MB'))
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cpu.mem = cpu.dcache
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system = System(cpu = cpu,
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system = System(cpu = cpu,
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physmem = PhysicalMemory(),
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physmem = PhysicalMemory(),
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membus = Bus())
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membus = Bus())
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