diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 7906156a2..88a8bf5e3 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -6,7 +6,7 @@ from Bus import Bus
 class BaseCPU(SimObject):
     type = 'BaseCPU'
     abstract = True
-    mem = Param.PhysicalMemory(Parent.any, "memory")
+    mem = Param.MemObject(Parent.any, "memory")
 
     system = Param.System(Parent.any, "system object")
     if build_env['FULL_SYSTEM']:
@@ -43,11 +43,12 @@ class BaseCPU(SimObject):
         self.icache_port = ic.cpu_side
         self.dcache_port = dc.cpu_side
         self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+#        self.mem = dc
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
         self.addPrivateSplitL1Caches(ic, dc)
         self.toL2Bus = Bus()
         self.connectMemPorts(self.toL2Bus)
         self.l2cache = l2c
-        self.l2cache.cpu_side = toL2Bus.port
+        self.l2cache.cpu_side = self.toL2Bus.port
         self._mem_ports = ['l2cache.mem_side']
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index 9b7ce1429..2bf67f3b1 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -34,5 +34,6 @@ system = System(cpu = AtomicSimpleCPU(),
                 membus = Bus())
 system.physmem.port = system.membus.port
 system.cpu.connectMemPorts(system.membus)
+system.cpu.mem = system.physmem
 
 root = Root(system = system)
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 823a8aec1..78dfabe3b 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -39,7 +39,7 @@ class MyCache(BaseCache):
 cpu = TimingSimpleCPU()
 cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
                               MyCache(size = '2MB'))
-
+cpu.mem = cpu.dcache
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
                 membus = Bus())