sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

hsail: Fix disassembly of load instruction with 3 destination operands

Browse source
This commit is contained in:
Alexandru Dutu 2016-09-16 12:36:20 -04:00
parent bd65ec0744
commit 68127ca3da
1 changed files with 9 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
src/arch/hsail/insts/mem_impl.hh
View file

@ -93,6 +93,15 @@ namespace HsailISA
this->dest_vect[1].disassemble(), this->dest_vect[1].disassemble(),
this->addr.disassemble()); this->addr.disassemble());
break; break;
case 3:
this->disassembly = csprintf("%s_%s_%s (%s,%s,%s), %s", this->opcode,
segmentNames[this->segment],
MemDataType::label,
this->dest_vect[0].disassemble(),
this->dest_vect[1].disassemble(),
this->dest_vect[2].disassemble(),
this->addr.disassemble());
break;
case 4: case 4:
this->disassembly = csprintf("%s_%s_%s (%s,%s,%s,%s), %s", this->disassembly = csprintf("%s_%s_%s (%s,%s,%s,%s), %s",
this->opcode, this->opcode,