stats: Bump stats for fixes, mostly TLB and WriteInvalidate
This commit is contained in:
Andreas Hansson
parent
966c3f4bc5
commit
6489598fb4
54 changed files with 59871 additions and 58871 deletions
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@ -1,45 +1,45 @@
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---------- Begin Simulation Statistics ----------
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---------- Begin Simulation Statistics ----------
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||||||
sim_seconds 0.061144 # Number of seconds simulated
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sim_seconds 0.061494 # Number of seconds simulated
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sim_ticks 61144411500 # Number of ticks simulated
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sim_ticks 61493732000 # Number of ticks simulated
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final_tick 61144411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 271316 # Simulator instruction rate (inst/s)
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host_inst_rate 280016 # Simulator instruction rate (inst/s)
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host_op_rate 272668 # Simulator op (including micro ops) rate (op/s)
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host_op_rate 281410 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 183101149 # Simulator tick rate (ticks/s)
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host_tick_rate 190051649 # Simulator tick rate (ticks/s)
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host_mem_usage 442968 # Number of bytes of host memory used
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host_mem_usage 385752 # Number of bytes of host memory used
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host_seconds 333.94 # Real time elapsed on the host
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host_seconds 323.56 # Real time elapsed on the host
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sim_insts 90602849 # Number of instructions simulated
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sim_insts 90602849 # Number of instructions simulated
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sim_ops 91054080 # Number of ops (including micro ops) simulated
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sim_ops 91054080 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 996736 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 996800 # Number of bytes read from this memory
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system.physmem.bytes_read::total 996736 # Number of bytes read from this memory
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system.physmem.bytes_read::total 996800 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 15574 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 15575 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 16301343 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 16209782 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 16301343 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 16209782 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 811194 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 806586 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 811194 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 806586 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 16301343 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 16209782 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 16301343 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 16209782 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15574 # Number of read requests accepted
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system.physmem.readReqs 15575 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM
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system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side
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system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 993 # Per bank write bursts
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system.physmem.perBankRdBursts::0 993 # Per bank write bursts
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system.physmem.perBankRdBursts::1 890 # Per bank write bursts
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system.physmem.perBankRdBursts::1 890 # Per bank write bursts
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system.physmem.perBankRdBursts::2 950 # Per bank write bursts
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system.physmem.perBankRdBursts::2 949 # Per bank write bursts
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system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
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system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
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system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
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system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
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system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
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system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
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@ -49,10 +49,10 @@ system.physmem.perBankRdBursts::8 1024 # Pe
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system.physmem.perBankRdBursts::9 962 # Per bank write bursts
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system.physmem.perBankRdBursts::9 962 # Per bank write bursts
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system.physmem.perBankRdBursts::10 938 # Per bank write bursts
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system.physmem.perBankRdBursts::10 938 # Per bank write bursts
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system.physmem.perBankRdBursts::11 899 # Per bank write bursts
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system.physmem.perBankRdBursts::11 899 # Per bank write bursts
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system.physmem.perBankRdBursts::12 903 # Per bank write bursts
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system.physmem.perBankRdBursts::12 904 # Per bank write bursts
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system.physmem.perBankRdBursts::13 867 # Per bank write bursts
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system.physmem.perBankRdBursts::13 867 # Per bank write bursts
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system.physmem.perBankRdBursts::14 877 # Per bank write bursts
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system.physmem.perBankRdBursts::14 877 # Per bank write bursts
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system.physmem.perBankRdBursts::15 904 # Per bank write bursts
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system.physmem.perBankRdBursts::15 905 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 61144323500 # Total gap between requests
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system.physmem.totGap 61493643500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 15574 # Read request sizes (log2)
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system.physmem.readPktSize::6 15575 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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@ -86,9 +86,9 @@ system.physmem.writePktSize::3 0 # Wr
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 15451 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 112 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1531 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::samples 1534 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 649.865447 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 648.594524 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 447.084914 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 444.741065 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 397.724653 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 399.329877 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 242 15.81% 15.81% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 241 15.71% 15.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 164 10.71% 26.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 178 11.60% 27.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 94 6.14% 32.66% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 90 5.87% 33.18% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 77 5.03% 37.69% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 63 4.11% 37.29% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 65 4.25% 41.93% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 79 5.15% 42.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 106 6.92% 48.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 102 6.65% 49.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 51 3.33% 52.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 28 1.83% 54.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 704 45.98% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation
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system.physmem.totQLat 71490500 # Total ticks spent queuing
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system.physmem.totQLat 73246500 # Total ticks spent queuing
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system.physmem.totMemAccLat 363503000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totMemAccLat 365277750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
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system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 4590.37 # Average queueing delay per DRAM burst
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system.physmem.avgQLat 4702.83 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 23340.37 # Average memory access latency per DRAM burst
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system.physmem.avgMemAccLat 23452.83 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 16.30 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 16.30 # Average system read bandwidth in MiByte/s
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system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.13 # Data bus utilization in percentage
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system.physmem.busUtil 0.13 # Data bus utilization in percentage
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@ -212,68 +212,45 @@ system.physmem.busUtilRead 0.13 # Da
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 14033 # Number of row buffer hits during reads
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system.physmem.readRowHits 14031 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 90.11 # Row buffer hit rate for reads
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system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 3926051.34 # Average gap between requests
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system.physmem.avgGap 3948227.51 # Average gap between requests
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system.physmem.pageHitRate 90.11 # Row buffer hit rate, read and write combined
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system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::IDLE 55905599000 # Time in different power states
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system.physmem.memoryStateTime::IDLE 56242943250 # Time in different power states
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system.physmem.memoryStateTime::REF 2041520000 # Time in different power states
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system.physmem.memoryStateTime::REF 2053220000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 3193563500 # Time in different power states
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system.physmem.memoryStateTime::ACT 3193793750 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem.actEnergy::0 6305040 # Energy for activate commands per rank (pJ)
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system.physmem.actEnergy::0 6320160 # Energy for activate commands per rank (pJ)
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system.physmem.actEnergy::1 5254200 # Energy for activate commands per rank (pJ)
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system.physmem.actEnergy::1 5261760 # Energy for activate commands per rank (pJ)
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system.physmem.preEnergy::0 3440250 # Energy for precharge commands per rank (pJ)
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system.physmem.preEnergy::0 3448500 # Energy for precharge commands per rank (pJ)
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system.physmem.preEnergy::1 2866875 # Energy for precharge commands per rank (pJ)
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system.physmem.preEnergy::1 2871000 # Energy for precharge commands per rank (pJ)
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system.physmem.readEnergy::0 63671400 # Energy for read commands per rank (pJ)
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system.physmem.readEnergy::0 63663600 # Energy for read commands per rank (pJ)
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system.physmem.readEnergy::1 57454800 # Energy for read commands per rank (pJ)
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system.physmem.readEnergy::1 57462600 # Energy for read commands per rank (pJ)
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system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
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system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
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system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
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system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
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system.physmem.refreshEnergy::0 3993213120 # Energy for refresh commands per rank (pJ)
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system.physmem.refreshEnergy::0 4016098320 # Energy for refresh commands per rank (pJ)
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system.physmem.refreshEnergy::1 3993213120 # Energy for refresh commands per rank (pJ)
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system.physmem.refreshEnergy::1 4016098320 # Energy for refresh commands per rank (pJ)
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system.physmem.actBackEnergy::0 2474179335 # Energy for active background per rank (pJ)
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system.physmem.actBackEnergy::0 2490497865 # Energy for active background per rank (pJ)
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system.physmem.actBackEnergy::1 2524417425 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::1 2514078765 # Energy for active background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::0 34512404250 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::0 34708310250 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::1 34468335750 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::1 34687625250 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.totalEnergy::0 41053213395 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::0 41288338695 # Total energy per rank (pJ)
|
||||||
system.physmem.totalEnergy::1 41051542170 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::1 41283397695 # Total energy per rank (pJ)
|
||||||
system.physmem.averagePower::0 671.485556 # Core power per rank (mW)
|
system.physmem.averagePower::0 671.483256 # Core power per rank (mW)
|
||||||
system.physmem.averagePower::1 671.458220 # Core power per rank (mW)
|
system.physmem.averagePower::1 671.402899 # Core power per rank (mW)
|
||||||
system.membus.trans_dist::ReadReq 1030 # Transaction distribution
|
system.cpu.branchPred.lookups 20789429 # Number of BP lookups
|
||||||
system.membus.trans_dist::ReadResp 1030 # Transaction distribution
|
system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted
|
||||||
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
|
system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect
|
||||||
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
|
system.cpu.branchPred.BTBLookups 8973618 # Number of BTB lookups
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes)
|
system.cpu.branchPred.BTBHits 8867020 # Number of BTB hits
|
||||||
system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 15574 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 15574 # Request fanout histogram
|
|
||||||
system.membus.reqLayer0.occupancy 21822000 # Layer occupancy (ticks)
|
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.membus.respLayer1.occupancy 149565000 # Layer occupancy (ticks)
|
|
||||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
||||||
system.cpu.branchPred.lookups 20748984 # Number of BP lookups
|
|
||||||
system.cpu.branchPred.condPredicted 17053332 # Number of conditional branches predicted
|
|
||||||
system.cpu.branchPred.condIncorrect 764055 # Number of conditional branches incorrect
|
|
||||||
system.cpu.branchPred.BTBLookups 8969348 # Number of BTB lookups
|
|
||||||
system.cpu.branchPred.BTBHits 8846034 # Number of BTB hits
|
|
||||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.branchPred.BTBHitPct 98.625162 # BTB Hit Percentage
|
system.cpu.branchPred.BTBHitPct 98.812096 # BTB Hit Percentage
|
||||||
system.cpu.branchPred.usedRAS 62305 # Number of times the RAS was used to get a target.
|
system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
|
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
|
||||||
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||||
|
|
@ -359,69 +336,192 @@ system.cpu.itb.hits 0 # DT
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||||
system.cpu.numCycles 122288823 # number of cpu cycles simulated
|
system.cpu.numCycles 122987464 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.committedInsts 90602849 # Number of instructions committed
|
system.cpu.committedInsts 90602849 # Number of instructions committed
|
||||||
system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed
|
system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed
|
||||||
system.cpu.discardedOps 2027782 # Number of ops (including micro ops) which were discarded before commit
|
system.cpu.discardedOps 2068195 # Number of ops (including micro ops) which were discarded before commit
|
||||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||||
system.cpu.cpi 1.349724 # CPI: cycles per instruction
|
system.cpu.cpi 1.357435 # CPI: cycles per instruction
|
||||||
system.cpu.ipc 0.740892 # IPC: instructions per cycle
|
system.cpu.ipc 0.736684 # IPC: instructions per cycle
|
||||||
system.cpu.tickCycles 109176308 # Number of cycles that the object actually ticked
|
system.cpu.tickCycles 109826570 # Number of cycles that the object actually ticked
|
||||||
system.cpu.idleCycles 13112515 # Total number of cycles that the object has spent stopped
|
system.cpu.idleCycles 13160894 # Total number of cycles that the object has spent stopped
|
||||||
|
system.cpu.dcache.tags.replacements 946107 # number of replacements
|
||||||
|
system.cpu.dcache.tags.tagsinuse 3616.604238 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.tags.total_refs 26267660 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.tags.avg_refs 27.644261 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.tags.warmup_cycle 20617906250 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.tags.occ_blocks::cpu.inst 3616.604238 # Average occupied blocks per requestor
|
||||||
|
system.cpu.dcache.tags.occ_percent::cpu.inst 0.882960 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.tags.occ_percent::total 0.882960 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||||
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id
|
||||||
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2249 # Occupied blocks per task id
|
||||||
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id
|
||||||
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.dcache.tags.tag_accesses 55463255 # Number of tag accesses
|
||||||
|
system.cpu.dcache.tags.data_accesses 55463255 # Number of data accesses
|
||||||
|
system.cpu.dcache.ReadReq_hits::cpu.inst 21598813 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.ReadReq_hits::total 21598813 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits::cpu.inst 4661073 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits::total 4661073 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits
|
||||||
|
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
|
||||||
|
system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits
|
||||||
|
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
||||||
|
system.cpu.dcache.demand_hits::cpu.inst 26259886 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.demand_hits::total 26259886 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits::cpu.inst 26259886 # number of overall hits
|
||||||
|
system.cpu.dcache.overall_hits::total 26259886 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses::cpu.inst 914958 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses::cpu.inst 73908 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses::cpu.inst 988866 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses::cpu.inst 988866 # number of overall misses
|
||||||
|
system.cpu.dcache.overall_misses::total 988866 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910311744 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency::total 11910311744 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345697500 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency::total 2345697500 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency::cpu.inst 14256009244 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency::total 14256009244 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency::cpu.inst 14256009244 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency::total 14256009244 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses::cpu.inst 22513771 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses::cpu.inst 27248752 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.demand_accesses::total 27248752 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses::cpu.inst 27248752 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses::total 27248752 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040640 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015609 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.331663 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.331663 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.073010 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.073010 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency::total 14416.522809 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency::total 14416.522809 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks
|
||||||
|
system.cpu.dcache.writebacks::total 943286 # number of writebacks
|
||||||
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11523 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_hits::total 11523 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27140 # number of WriteReq MSHR hits
|
||||||
|
system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_hits::cpu.inst 38663 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_hits::total 38663 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits::cpu.inst 38663 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits::total 38663 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903435 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46768 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses::cpu.inst 950203 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses::cpu.inst 950203 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958869756 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958869756 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333434750 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333434750 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292304506 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency::total 11292304506 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292304506 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency::total 11292304506 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040128 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009877 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.338432 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.338432 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28511.690686 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28511.690686 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.tags.replacements 5 # number of replacements
|
system.cpu.icache.tags.replacements 5 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 690.927522 # Cycle average of tags in use
|
system.cpu.icache.tags.tagsinuse 690.411179 # Cycle average of tags in use
|
||||||
system.cpu.icache.tags.total_refs 27773574 # Total number of references to valid blocks.
|
system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks.
|
system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.tags.avg_refs 34587.265255 # Average number of references to valid blocks.
|
system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.tags.occ_blocks::cpu.inst 690.927522 # Average occupied blocks per requestor
|
system.cpu.icache.tags.occ_blocks::cpu.inst 690.411179 # Average occupied blocks per requestor
|
||||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.337367 # Average percentage of cache occupancy
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.tags.occ_percent::total 0.337367 # Average percentage of cache occupancy
|
system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
|
system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
|
||||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
|
||||||
system.cpu.icache.tags.tag_accesses 55549557 # Number of tag accesses
|
system.cpu.icache.tags.tag_accesses 55716427 # Number of tag accesses
|
||||||
system.cpu.icache.tags.data_accesses 55549557 # Number of data accesses
|
system.cpu.icache.tags.data_accesses 55716427 # Number of data accesses
|
||||||
system.cpu.icache.ReadReq_hits::cpu.inst 27773574 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits::cpu.inst 27857009 # number of ReadReq hits
|
||||||
system.cpu.icache.ReadReq_hits::total 27773574 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits::total 27857009 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits::cpu.inst 27773574 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits::cpu.inst 27857009 # number of demand (read+write) hits
|
||||||
system.cpu.icache.demand_hits::total 27773574 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits::total 27857009 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits::cpu.inst 27773574 # number of overall hits
|
system.cpu.icache.overall_hits::cpu.inst 27857009 # number of overall hits
|
||||||
system.cpu.icache.overall_hits::total 27773574 # number of overall hits
|
system.cpu.icache.overall_hits::total 27857009 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
|
||||||
system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
|
||||||
system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses
|
system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses
|
||||||
system.cpu.icache.overall_misses::total 803 # number of overall misses
|
system.cpu.icache.overall_misses::total 803 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 55313498 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 55346748 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.ReadReq_miss_latency::total 55313498 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency::total 55346748 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency::cpu.inst 55313498 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency::cpu.inst 55346748 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.demand_miss_latency::total 55313498 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency::total 55346748 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency::cpu.inst 55313498 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency::cpu.inst 55346748 # number of overall miss cycles
|
||||||
system.cpu.icache.overall_miss_latency::total 55313498 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency::total 55346748 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses::cpu.inst 27774377 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses::cpu.inst 27857812 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.ReadReq_accesses::total 27774377 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses::total 27857812 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses::cpu.inst 27774377 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses::cpu.inst 27857812 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.demand_accesses::total 27774377 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses::total 27857812 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses::cpu.inst 27774377 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses::cpu.inst 27857812 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses::total 27774377 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses::total 27857812 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
|
||||||
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
|
||||||
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68883.559153 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68924.966376 # average ReadReq miss latency
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::total 68883.559153 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency::total 68924.966376 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency::total 68883.559153 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency::total 68924.966376 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency::total 68883.559153 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency::total 68924.966376 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -436,130 +536,97 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 803
|
||||||
system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53373502 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53408252 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 53373502 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 53408252 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53373502 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53408252 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency::total 53373502 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency::total 53408252 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53373502 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53408252 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency::total 53373502 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency::total 53408252 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66467.623910 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66510.899128 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66467.623910 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66510.899128 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 904183 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 904183 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::Writeback 943269 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46761 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46761 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843551 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count::total 2845157 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 1894213 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::5 1894213 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 1894213 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 1890375500 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer0.occupancy 1371498 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer1.occupancy 1428579494 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
|
|
||||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||||
system.cpu.l2cache.tags.tagsinuse 10264.635477 # Cycle average of tags in use
|
system.cpu.l2cache.tags.tagsinuse 10247.121792 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.tags.total_refs 1831263 # Total number of references to valid blocks.
|
system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks.
|
system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.tags.avg_refs 117.713119 # Average number of references to valid blocks.
|
system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9373.658869 # Average occupied blocks per requestor
|
system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236502 # Average occupied blocks per requestor
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976609 # Average occupied blocks per requestor
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885290 # Average occupied blocks per requestor
|
||||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.286061 # Average percentage of cache occupancy
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027190 # Average percentage of cache occupancy
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027188 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.tags.occ_percent::total 0.313252 # Average percentage of cache occupancy
|
system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id
|
||||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id
|
||||||
system.cpu.l2cache.tags.tag_accesses 15216022 # Number of tag accesses
|
system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses
|
||||||
system.cpu.l2cache.tags.data_accesses 15216022 # Number of data accesses
|
system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 903145 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 903199 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_hits::total 903145 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits::writebacks 943269 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits
|
||||||
system.cpu.l2cache.Writeback_hits::total 943269 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits
|
||||||
system.cpu.l2cache.ReadExReq_hits::cpu.inst 32217 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits::cpu.inst 32224 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits::total 32217 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits::cpu.inst 935362 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::cpu.inst 935423 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_hits::total 935362 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::total 935423 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits::cpu.inst 935362 # number of overall hits
|
system.cpu.l2cache.overall_hits::cpu.inst 935423 # number of overall hits
|
||||||
system.cpu.l2cache.overall_hits::total 935362 # number of overall hits
|
system.cpu.l2cache.overall_hits::total 935423 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 1038 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_misses::total 1038 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses::cpu.inst 15582 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses::cpu.inst 15583 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses::cpu.inst 15582 # number of overall misses
|
system.cpu.l2cache.overall_misses::cpu.inst 15583 # number of overall misses
|
||||||
system.cpu.l2cache.overall_misses::total 15582 # number of overall misses
|
system.cpu.l2cache.overall_misses::total 15583 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71732750 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71718500 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::total 71732750 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency::total 71718500 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959611500 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958069250 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::total 959611500 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency::total 958069250 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 1031344250 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1029787750 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::total 1031344250 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::total 1029787750 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 1031344250 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1029787750 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::total 1031344250 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::total 1029787750 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 904183 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 904238 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::total 904183 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses::writebacks 943269 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses::total 943269 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46761 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46768 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses::total 46761 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses::cpu.inst 950944 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses::cpu.inst 951006 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_accesses::total 950944 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses::cpu.inst 950944 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses::cpu.inst 951006 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses::total 950944 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001148 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001149 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.001148 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.311028 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.310982 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311028 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69106.695568 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69026.467757 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.695568 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69026.467757 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65979.888614 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65873.848322 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65979.888614 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65873.848322 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::total 66188.181877 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::total 66084.049926 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::total 66188.181877 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::total 66084.049926 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -574,161 +641,94 @@ system.cpu.l2cache.demand_mshr_hits::cpu.inst 8
|
||||||
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1031 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15574 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15575 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15574 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15575 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58370500 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58344750 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58370500 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58344750 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772672000 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774500250 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772672000 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774500250 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831042500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832845000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::total 831042500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::total 832845000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831042500 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832845000 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::total 831042500 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::total 832845000 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001139 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001140 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.311028 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310982 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311028 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56670.388350 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56590.446169 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56670.388350 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56590.446169 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53126.512651 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53252.217409 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53126.512651 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53252.217409 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.tags.replacements 946045 # number of replacements
|
system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution
|
||||||
system.cpu.dcache.tags.tagsinuse 3618.157159 # Cycle average of tags in use
|
system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution
|
||||||
system.cpu.dcache.tags.total_refs 26265609 # Total number of references to valid blocks.
|
system.cpu.toL2Bus.trans_dist::Writeback 943286 # Transaction distribution
|
||||||
system.cpu.dcache.tags.sampled_refs 950141 # Sample count of references to valid blocks.
|
system.cpu.toL2Bus.trans_dist::ReadExReq 46768 # Transaction distribution
|
||||||
system.cpu.dcache.tags.avg_refs 27.643907 # Average number of references to valid blocks.
|
system.cpu.toL2Bus.trans_dist::ReadExResp 46768 # Transaction distribution
|
||||||
system.cpu.dcache.tags.warmup_cycle 20427116250 # Cycle when the warmup percentage was hit.
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 3618.157159 # Average occupied blocks per requestor
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843692 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.883339 # Average percentage of cache occupancy
|
system.cpu.toL2Bus.pkt_count::total 2845298 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.dcache.tags.occ_percent::total 0.883339 # Average percentage of cache occupancy
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183296 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id
|
system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2250 # Occupied blocks per task id
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id
|
system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram
|
||||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||||
system.cpu.dcache.tags.tag_accesses 55458945 # Number of tag accesses
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.dcache.tags.data_accesses 55458945 # Number of data accesses
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.dcache.ReadReq_hits::cpu.inst 21596750 # number of ReadReq hits
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.dcache.ReadReq_hits::total 21596750 # number of ReadReq hits
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.dcache.WriteReq_hits::cpu.inst 4661085 # number of WriteReq hits
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.dcache.WriteReq_hits::total 4661085 # number of WriteReq hits
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
|
system.cpu.toL2Bus.snoop_fanout::5 1894292 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits
|
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.dcache.demand_hits::cpu.inst 26257835 # number of demand (read+write) hits
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||||
system.cpu.dcache.demand_hits::total 26257835 # number of demand (read+write) hits
|
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||||
system.cpu.dcache.overall_hits::cpu.inst 26257835 # number of overall hits
|
system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram
|
||||||
system.cpu.dcache.overall_hits::total 26257835 # number of overall hits
|
system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks)
|
||||||
system.cpu.dcache.ReadReq_misses::cpu.inst 914897 # number of ReadReq misses
|
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
|
||||||
system.cpu.dcache.ReadReq_misses::total 914897 # number of ReadReq misses
|
system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks)
|
||||||
system.cpu.dcache.WriteReq_misses::cpu.inst 73896 # number of WriteReq misses
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.cpu.dcache.WriteReq_misses::total 73896 # number of WriteReq misses
|
system.cpu.toL2Bus.respLayer1.occupancy 1428672494 # Layer occupancy (ticks)
|
||||||
system.cpu.dcache.demand_misses::cpu.inst 988793 # number of demand (read+write) misses
|
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
|
||||||
system.cpu.dcache.demand_misses::total 988793 # number of demand (read+write) misses
|
system.membus.trans_dist::ReadReq 1031 # Transaction distribution
|
||||||
system.cpu.dcache.overall_misses::cpu.inst 988793 # number of overall misses
|
system.membus.trans_dist::ReadResp 1031 # Transaction distribution
|
||||||
system.cpu.dcache.overall_misses::total 988793 # number of overall misses
|
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
|
||||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11909486494 # number of ReadReq miss cycles
|
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
|
||||||
system.cpu.dcache.ReadReq_miss_latency::total 11909486494 # number of ReadReq miss cycles
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342568500 # number of WriteReq miss cycles
|
system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.dcache.WriteReq_miss_latency::total 2342568500 # number of WriteReq miss cycles
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.dcache.demand_miss_latency::cpu.inst 14252054994 # number of demand (read+write) miss cycles
|
system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.dcache.demand_miss_latency::total 14252054994 # number of demand (read+write) miss cycles
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.dcache.overall_miss_latency::cpu.inst 14252054994 # number of overall miss cycles
|
system.membus.snoop_fanout::samples 15575 # Request fanout histogram
|
||||||
system.cpu.dcache.overall_miss_latency::total 14252054994 # number of overall miss cycles
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 22511647 # number of ReadReq accesses(hits+misses)
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.dcache.ReadReq_accesses::total 22511647 # number of ReadReq accesses(hits+misses)
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses)
|
system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses)
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses)
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||||
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
system.membus.snoop_fanout::total 15575 # Request fanout histogram
|
||||||
system.cpu.dcache.demand_accesses::cpu.inst 27246628 # number of demand (read+write) accesses
|
system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks)
|
||||||
system.cpu.dcache.demand_accesses::total 27246628 # number of demand (read+write) accesses
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.cpu.dcache.overall_accesses::cpu.inst 27246628 # number of overall (read+write) accesses
|
system.membus.respLayer1.occupancy 146202000 # Layer occupancy (ticks)
|
||||||
system.cpu.dcache.overall_accesses::total 27246628 # number of overall (read+write) accesses
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040641 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_miss_rate::total 0.040641 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015606 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate::total 0.015606 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569 # average ReadReq miss latency
|
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569 # average ReadReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31700.883674 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 31700.883674 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency::total 14413.588076 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency::total 14413.588076 # average overall miss latency
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.writebacks::writebacks 943269 # number of writebacks
|
|
||||||
system.cpu.dcache.writebacks::total 943269 # number of writebacks
|
|
||||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11517 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.dcache.ReadReq_mshr_hits::total 11517 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27135 # number of WriteReq MSHR hits
|
|
||||||
system.cpu.dcache.WriteReq_mshr_hits::total 27135 # number of WriteReq MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_hits::cpu.inst 38652 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_hits::total 38652 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_hits::cpu.inst 38652 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_hits::total 38652 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903380 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses::total 903380 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46761 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses::total 46761 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.demand_mshr_misses::cpu.inst 950141 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.demand_mshr_misses::total 950141 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 950141 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_misses::total 950141 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958325256 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958325256 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334896250 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334896250 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293221506 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::total 11293221506 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293221506 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::total 11293221506 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040129 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009876 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.213490 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.213490 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,58 +1,58 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.220941 # Number of seconds simulated
|
sim_seconds 0.226819 # Number of seconds simulated
|
||||||
sim_ticks 220941341500 # Number of ticks simulated
|
sim_ticks 226818771000 # Number of ticks simulated
|
||||||
final_tick 220941341500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 226818771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 295257 # Simulator instruction rate (inst/s)
|
host_inst_rate 285609 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 295257 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 285609 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 163632311 # Simulator tick rate (ticks/s)
|
host_tick_rate 162496290 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 243348 # Number of bytes of host memory used
|
host_mem_usage 242892 # Number of bytes of host memory used
|
||||||
host_seconds 1350.23 # Real time elapsed on the host
|
host_seconds 1395.84 # Real time elapsed on the host
|
||||||
sim_insts 398664665 # Number of instructions simulated
|
sim_insts 398664665 # Number of instructions simulated
|
||||||
sim_ops 398664665 # Number of ops (including micro ops) simulated
|
sim_ops 398664665 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
system.clk_domain.clock 1000 # Clock period in ticks
|
system.clk_domain.clock 1000 # Clock period in ticks
|
||||||
system.physmem.bytes_read::cpu.inst 504000 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.inst 503872 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::total 504000 # Number of bytes read from this memory
|
system.physmem.bytes_read::total 503872 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::cpu.inst 249408 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::total 249408 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory
|
||||||
system.physmem.num_reads::cpu.inst 7875 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.inst 7873 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::total 7875 # Number of read requests responded to by this memory
|
system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory
|
||||||
system.physmem.bw_read::cpu.inst 2281148 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.inst 2221474 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::total 2281148 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::total 2221474 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu.inst 1128843 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu.inst 1099027 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::total 1128843 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::total 1099027 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.inst 2281148 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 2221474 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 2281148 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 2221474 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.readReqs 7875 # Number of read requests accepted
|
system.physmem.readReqs 7873 # Number of read requests accepted
|
||||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||||
system.physmem.readBursts 7875 # Number of DRAM read bursts, including those serviced by the write queue
|
system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue
|
||||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||||
system.physmem.bytesReadDRAM 504000 # Total number of bytes read from DRAM
|
system.physmem.bytesReadDRAM 503872 # Total number of bytes read from DRAM
|
||||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||||
system.physmem.bytesReadSys 504000 # Total read bytes from the system interface side
|
system.physmem.bytesReadSys 503872 # Total read bytes from the system interface side
|
||||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||||
system.physmem.perBankRdBursts::0 551 # Per bank write bursts
|
system.physmem.perBankRdBursts::0 551 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::1 675 # Per bank write bursts
|
system.physmem.perBankRdBursts::1 676 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::2 471 # Per bank write bursts
|
system.physmem.perBankRdBursts::2 471 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::3 633 # Per bank write bursts
|
system.physmem.perBankRdBursts::3 633 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::4 475 # Per bank write bursts
|
system.physmem.perBankRdBursts::4 475 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::5 478 # Per bank write bursts
|
system.physmem.perBankRdBursts::5 478 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::6 564 # Per bank write bursts
|
system.physmem.perBankRdBursts::6 563 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::7 560 # Per bank write bursts
|
system.physmem.perBankRdBursts::7 560 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::8 471 # Per bank write bursts
|
system.physmem.perBankRdBursts::8 469 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::9 437 # Per bank write bursts
|
system.physmem.perBankRdBursts::9 437 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::10 354 # Per bank write bursts
|
system.physmem.perBankRdBursts::10 354 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::11 324 # Per bank write bursts
|
system.physmem.perBankRdBursts::11 323 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::12 430 # Per bank write bursts
|
system.physmem.perBankRdBursts::12 430 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::13 556 # Per bank write bursts
|
system.physmem.perBankRdBursts::13 556 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::14 473 # Per bank write bursts
|
system.physmem.perBankRdBursts::14 473 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::15 423 # Per bank write bursts
|
system.physmem.perBankRdBursts::15 424 # Per bank write bursts
|
||||||
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
||||||
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
||||||
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
||||||
|
|
@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
||||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||||
system.physmem.totGap 220941260000 # Total gap between requests
|
system.physmem.totGap 226818689500 # Total gap between requests
|
||||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::6 7875 # Read request sizes (log2)
|
system.physmem.readPktSize::6 7873 # Read request sizes (log2)
|
||||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||||
|
|
@ -86,9 +86,9 @@ system.physmem.writePktSize::3 0 # Wr
|
||||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||||
system.physmem.rdQLenPdf::0 6821 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::0 6808 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::1 971 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::1 980 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||||
|
|
@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
||||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||||
system.physmem.bytesPerActivate::samples 1518 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::mean 330.160738 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::mean 329.076822 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::gmean 197.894458 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::gmean 197.330219 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::stdev 332.998951 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::stdev 334.077184 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::0-127 519 34.19% 34.19% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::0-127 516 33.88% 33.88% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::128-255 336 22.13% 56.32% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::128-255 348 22.85% 56.73% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::256-383 186 12.25% 68.58% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::256-383 193 12.67% 69.40% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::384-511 110 7.25% 75.82% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::384-511 104 6.83% 76.23% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::512-639 56 3.69% 79.51% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::512-639 58 3.81% 80.04% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::640-767 56 3.69% 83.20% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::640-767 41 2.69% 82.73% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::768-895 37 2.44% 85.64% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::768-895 32 2.10% 84.83% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::896-1023 28 1.84% 87.48% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::896-1023 40 2.63% 87.46% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::1024-1151 190 12.52% 100.00% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::1024-1151 191 12.54% 100.00% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::total 1518 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation
|
||||||
system.physmem.totQLat 53358500 # Total ticks spent queuing
|
system.physmem.totQLat 50615750 # Total ticks spent queuing
|
||||||
system.physmem.totMemAccLat 201014750 # Total ticks spent from burst creation until serviced by the DRAM
|
system.physmem.totMemAccLat 198234500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||||
system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers
|
system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers
|
||||||
system.physmem.avgQLat 6775.68 # Average queueing delay per DRAM burst
|
system.physmem.avgQLat 6429.03 # Average queueing delay per DRAM burst
|
||||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||||
system.physmem.avgMemAccLat 25525.68 # Average memory access latency per DRAM burst
|
system.physmem.avgMemAccLat 25179.03 # Average memory access latency per DRAM burst
|
||||||
system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s
|
system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||||
system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s
|
system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||||
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
||||||
|
|
@ -212,88 +212,65 @@ system.physmem.busUtilRead 0.02 # Da
|
||||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||||
system.physmem.readRowHits 6348 # Number of row buffer hits during reads
|
system.physmem.readRowHits 6341 # Number of row buffer hits during reads
|
||||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||||
system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads
|
system.physmem.readRowHitRate 80.54 # Row buffer hit rate for reads
|
||||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||||
system.physmem.avgGap 28056033.02 # Average gap between requests
|
system.physmem.avgGap 28809690.02 # Average gap between requests
|
||||||
system.physmem.pageHitRate 80.61 # Row buffer hit rate, read and write combined
|
system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined
|
||||||
system.physmem.memoryStateTime::IDLE 211835989750 # Time in different power states
|
system.physmem.memoryStateTime::IDLE 217525128250 # Time in different power states
|
||||||
system.physmem.memoryStateTime::REF 7377500000 # Time in different power states
|
system.physmem.memoryStateTime::REF 7573800000 # Time in different power states
|
||||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT 1721627750 # Time in different power states
|
system.physmem.memoryStateTime::ACT 1714919250 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||||
system.physmem.actEnergy::0 6743520 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::0 6698160 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem.actEnergy::1 4717440 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::1 4808160 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem.preEnergy::0 3679500 # Energy for precharge commands per rank (pJ)
|
system.physmem.preEnergy::0 3654750 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem.preEnergy::1 2574000 # Energy for precharge commands per rank (pJ)
|
system.physmem.preEnergy::1 2623500 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem.readEnergy::0 34164000 # Energy for read commands per rank (pJ)
|
system.physmem.readEnergy::0 34164000 # Energy for read commands per rank (pJ)
|
||||||
system.physmem.readEnergy::1 26902200 # Energy for read commands per rank (pJ)
|
system.physmem.readEnergy::1 26910000 # Energy for read commands per rank (pJ)
|
||||||
system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
||||||
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
|
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
|
||||||
system.physmem.refreshEnergy::0 14430390000 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::0 14814352800 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.refreshEnergy::1 14430390000 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::1 14814352800 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.actBackEnergy::0 5688842535 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::0 5823022815 # Energy for active background per rank (pJ)
|
||||||
system.physmem.actBackEnergy::1 5444083395 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::1 5572463355 # Energy for active background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::0 127570849500 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::0 130980318750 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::1 127785550500 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::1 131200107750 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.totalEnergy::0 147734669055 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::0 151662211275 # Total energy per rank (pJ)
|
||||||
system.physmem.totalEnergy::1 147694217535 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::1 151621265565 # Total energy per rank (pJ)
|
||||||
system.physmem.averagePower::0 668.679022 # Core power per rank (mW)
|
system.physmem.averagePower::0 668.664178 # Core power per rank (mW)
|
||||||
system.physmem.averagePower::1 668.495929 # Core power per rank (mW)
|
system.physmem.averagePower::1 668.483652 # Core power per rank (mW)
|
||||||
system.membus.trans_dist::ReadReq 4737 # Transaction distribution
|
system.cpu.branchPred.lookups 46273762 # Number of BP lookups
|
||||||
system.membus.trans_dist::ReadResp 4737 # Transaction distribution
|
system.cpu.branchPred.condPredicted 26730646 # Number of conditional branches predicted
|
||||||
system.membus.trans_dist::ReadExReq 3138 # Transaction distribution
|
system.cpu.branchPred.condIncorrect 1017469 # Number of conditional branches incorrect
|
||||||
system.membus.trans_dist::ReadExResp 3138 # Transaction distribution
|
system.cpu.branchPred.BTBLookups 25595417 # Number of BTB lookups
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15750 # Packet count per connected master and slave (bytes)
|
system.cpu.branchPred.BTBHits 21359944 # Number of BTB hits
|
||||||
system.membus.pkt_count::total 15750 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 7875 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 7875 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 7875 # Request fanout histogram
|
|
||||||
system.membus.reqLayer0.occupancy 9512000 # Layer occupancy (ticks)
|
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.membus.respLayer1.occupancy 74011500 # Layer occupancy (ticks)
|
|
||||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
||||||
system.cpu.branchPred.lookups 46221231 # Number of BP lookups
|
|
||||||
system.cpu.branchPred.condPredicted 26710053 # Number of conditional branches predicted
|
|
||||||
system.cpu.branchPred.condIncorrect 1012987 # Number of conditional branches incorrect
|
|
||||||
system.cpu.branchPred.BTBLookups 25408308 # Number of BTB lookups
|
|
||||||
system.cpu.branchPred.BTBHits 21330923 # Number of BTB hits
|
|
||||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.branchPred.BTBHitPct 83.952552 # BTB Hit Percentage
|
system.cpu.branchPred.BTBHitPct 83.452221 # BTB Hit Percentage
|
||||||
system.cpu.branchPred.usedRAS 8326726 # Number of times the RAS was used to get a target.
|
system.cpu.branchPred.usedRAS 8341649 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions.
|
system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions.
|
||||||
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 95595776 # DTB read hits
|
system.cpu.dtb.read_hits 95585470 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 118 # DTB read misses
|
system.cpu.dtb.read_misses 115 # DTB read misses
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.read_accesses 95595894 # DTB read accesses
|
system.cpu.dtb.read_accesses 95585585 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 73604420 # DTB write hits
|
system.cpu.dtb.write_hits 73606436 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 858 # DTB write misses
|
system.cpu.dtb.write_misses 857 # DTB write misses
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.dtb.write_accesses 73605278 # DTB write accesses
|
system.cpu.dtb.write_accesses 73607293 # DTB write accesses
|
||||||
system.cpu.dtb.data_hits 169200196 # DTB hits
|
system.cpu.dtb.data_hits 169191906 # DTB hits
|
||||||
system.cpu.dtb.data_misses 976 # DTB misses
|
system.cpu.dtb.data_misses 972 # DTB misses
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.dtb.data_accesses 169201172 # DTB accesses
|
system.cpu.dtb.data_accesses 169192878 # DTB accesses
|
||||||
system.cpu.itb.fetch_hits 98242303 # ITB hits
|
system.cpu.itb.fetch_hits 98781228 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 1225 # ITB misses
|
system.cpu.itb.fetch_misses 1237 # ITB misses
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.fetch_accesses 98243528 # ITB accesses
|
system.cpu.itb.fetch_accesses 98782465 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
|
|
@ -307,253 +284,26 @@ system.cpu.itb.data_misses 0 # DT
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||||
system.cpu.numCycles 441882683 # number of cpu cycles simulated
|
system.cpu.numCycles 453637542 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.committedInsts 398664665 # Number of instructions committed
|
system.cpu.committedInsts 398664665 # Number of instructions committed
|
||||||
system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed
|
system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed
|
||||||
system.cpu.discardedOps 4446127 # Number of ops (including micro ops) which were discarded before commit
|
system.cpu.discardedOps 4467797 # Number of ops (including micro ops) which were discarded before commit
|
||||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||||
system.cpu.cpi 1.108407 # CPI: cycles per instruction
|
system.cpu.cpi 1.137893 # CPI: cycles per instruction
|
||||||
system.cpu.ipc 0.902196 # IPC: instructions per cycle
|
system.cpu.ipc 0.878818 # IPC: instructions per cycle
|
||||||
system.cpu.tickCycles 437732110 # Number of cycles that the object actually ticked
|
system.cpu.tickCycles 450174331 # Number of cycles that the object actually ticked
|
||||||
system.cpu.idleCycles 4150573 # Total number of cycles that the object has spent stopped
|
system.cpu.idleCycles 3463211 # Total number of cycles that the object has spent stopped
|
||||||
system.cpu.icache.tags.replacements 3195 # number of replacements
|
|
||||||
system.cpu.icache.tags.tagsinuse 1919.708570 # Cycle average of tags in use
|
|
||||||
system.cpu.icache.tags.total_refs 98237130 # Total number of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.sampled_refs 5173 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.avg_refs 18990.359559 # Average number of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708570 # Average occupied blocks per requestor
|
|
||||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.937358 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.tags.occ_percent::total 0.937358 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1282 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.icache.tags.tag_accesses 196489779 # Number of tag accesses
|
|
||||||
system.cpu.icache.tags.data_accesses 196489779 # Number of data accesses
|
|
||||||
system.cpu.icache.ReadReq_hits::cpu.inst 98237130 # number of ReadReq hits
|
|
||||||
system.cpu.icache.ReadReq_hits::total 98237130 # number of ReadReq hits
|
|
||||||
system.cpu.icache.demand_hits::cpu.inst 98237130 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.demand_hits::total 98237130 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.overall_hits::cpu.inst 98237130 # number of overall hits
|
|
||||||
system.cpu.icache.overall_hits::total 98237130 # number of overall hits
|
|
||||||
system.cpu.icache.ReadReq_misses::cpu.inst 5173 # number of ReadReq misses
|
|
||||||
system.cpu.icache.ReadReq_misses::total 5173 # number of ReadReq misses
|
|
||||||
system.cpu.icache.demand_misses::cpu.inst 5173 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses
|
|
||||||
system.cpu.icache.overall_misses::total 5173 # number of overall misses
|
|
||||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 293560000 # number of ReadReq miss cycles
|
|
||||||
system.cpu.icache.ReadReq_miss_latency::total 293560000 # number of ReadReq miss cycles
|
|
||||||
system.cpu.icache.demand_miss_latency::cpu.inst 293560000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.demand_miss_latency::total 293560000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.overall_miss_latency::cpu.inst 293560000 # number of overall miss cycles
|
|
||||||
system.cpu.icache.overall_miss_latency::total 293560000 # number of overall miss cycles
|
|
||||||
system.cpu.icache.ReadReq_accesses::cpu.inst 98242303 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.icache.ReadReq_accesses::total 98242303 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.icache.demand_accesses::cpu.inst 98242303 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.demand_accesses::total 98242303 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.overall_accesses::cpu.inst 98242303 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.overall_accesses::total 98242303 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56748.501836 # average ReadReq miss latency
|
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56748.501836 # average ReadReq miss latency
|
|
||||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56748.501836 # average overall miss latency
|
|
||||||
system.cpu.icache.demand_avg_miss_latency::total 56748.501836 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56748.501836 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_miss_latency::total 56748.501836 # average overall miss latency
|
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5173 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses::total 5173 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.demand_mshr_misses::cpu.inst 5173 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 5173 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_misses::total 5173 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281592000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281592000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281592000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency::total 281592000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281592000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency::total 281592000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54434.950706 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54434.950706 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54434.950706 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54434.950706 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54434.950706 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54434.950706 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3199 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3199 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10346 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count::total 19330 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 9992 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 9992 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 9992 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer0.occupancy 8570500 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer1.occupancy 6975500 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
||||||
system.cpu.l2cache.tags.tagsinuse 4427.627399 # Cycle average of tags in use
|
|
||||||
system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.tags.occ_blocks::writebacks 373.083919 # Average occupied blocks per requestor
|
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543479 # Average occupied blocks per requestor
|
|
||||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123735 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_percent::total 0.135120 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4444 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.l2cache.tags.tag_accesses 88409 # Number of tag accesses
|
|
||||||
system.cpu.l2cache.tags.data_accesses 88409 # Number of data accesses
|
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1402 # number of ReadReq hits
|
|
||||||
system.cpu.l2cache.ReadReq_hits::total 1402 # number of ReadReq hits
|
|
||||||
system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits
|
|
||||||
system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits
|
|
||||||
system.cpu.l2cache.ReadExReq_hits::cpu.inst 61 # number of ReadExReq hits
|
|
||||||
system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits
|
|
||||||
system.cpu.l2cache.demand_hits::cpu.inst 1463 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_hits::total 1463 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.overall_hits::cpu.inst 1463 # number of overall hits
|
|
||||||
system.cpu.l2cache.overall_hits::total 1463 # number of overall hits
|
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 4737 # number of ReadReq misses
|
|
||||||
system.cpu.l2cache.ReadReq_misses::total 4737 # number of ReadReq misses
|
|
||||||
system.cpu.l2cache.ReadExReq_misses::cpu.inst 3138 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.ReadExReq_misses::total 3138 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.demand_misses::cpu.inst 7875 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_misses::total 7875 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.overall_misses::cpu.inst 7875 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_misses::total 7875 # number of overall misses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325756750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::total 325756750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212895750 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::total 212895750 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 538652500 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::total 538652500 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 538652500 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::total 538652500 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6139 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::total 6139 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 3199 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::total 3199 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.demand_accesses::cpu.inst 9338 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_accesses::total 9338 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::cpu.inst 9338 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::total 9338 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.771624 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.771624 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.980932 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.980932 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843328 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::total 0.843328 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843328 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::total 0.843328 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68768.577159 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68768.577159 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67844.407266 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67844.407266 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68400.317460 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::total 68400.317460 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68400.317460 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::total 68400.317460 # average overall miss latency
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4737 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4737 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 3138 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 3138 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7875 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::total 7875 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7875 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 7875 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266376250 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266376250 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173100750 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173100750 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439477000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::total 439477000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439477000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::total 439477000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771624 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771624 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980932 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980932 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.843328 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843328 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56233.111674 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56233.111674 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55162.762906 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55162.762906 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55806.603175 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55806.603175 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55806.603175 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55806.603175 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.tags.replacements 771 # number of replacements
|
system.cpu.dcache.tags.replacements 771 # number of replacements
|
||||||
system.cpu.dcache.tags.tagsinuse 3291.748199 # Cycle average of tags in use
|
system.cpu.dcache.tags.tagsinuse 3291.955317 # Cycle average of tags in use
|
||||||
system.cpu.dcache.tags.total_refs 168007181 # Total number of references to valid blocks.
|
system.cpu.dcache.tags.total_refs 168028615 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
|
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.tags.avg_refs 40337.858583 # Average number of references to valid blocks.
|
system.cpu.dcache.tags.avg_refs 40343.004802 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.748199 # Average occupied blocks per requestor
|
system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.955317 # Average occupied blocks per requestor
|
||||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.803649 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::cpu.inst 0.803700 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.tags.occ_percent::total 0.803649 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::total 0.803700 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
||||||
|
|
@ -561,40 +311,40 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 216
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
|
||||||
system.cpu.dcache.tags.tag_accesses 336032765 # Number of tag accesses
|
system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses
|
||||||
system.cpu.dcache.tags.data_accesses 336032765 # Number of data accesses
|
system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses
|
||||||
system.cpu.dcache.ReadReq_hits::cpu.inst 94492394 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::cpu.inst 94513823 # number of ReadReq hits
|
||||||
system.cpu.dcache.ReadReq_hits::total 94492394 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::total 94513823 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::cpu.inst 73514787 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::cpu.inst 73514792 # number of WriteReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::total 73514787 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::total 73514792 # number of WriteReq hits
|
||||||
system.cpu.dcache.demand_hits::cpu.inst 168007181 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::cpu.inst 168028615 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.demand_hits::total 168007181 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::total 168028615 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits::cpu.inst 168007181 # number of overall hits
|
system.cpu.dcache.overall_hits::cpu.inst 168028615 # number of overall hits
|
||||||
system.cpu.dcache.overall_hits::total 168007181 # number of overall hits
|
system.cpu.dcache.overall_hits::total 168028615 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses::cpu.inst 1176 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses
|
||||||
system.cpu.dcache.ReadReq_misses::total 1176 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::total 1181 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses::cpu.inst 5943 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses::cpu.inst 5938 # number of WriteReq misses
|
||||||
system.cpu.dcache.WriteReq_misses::total 5943 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses::total 5938 # number of WriteReq misses
|
||||||
system.cpu.dcache.demand_misses::cpu.inst 7119 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses::cpu.inst 7119 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses
|
system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses
|
||||||
system.cpu.dcache.overall_misses::total 7119 # number of overall misses
|
system.cpu.dcache.overall_misses::total 7119 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81019000 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81052500 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_latency::total 81019000 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::total 81052500 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 393760000 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 391543250 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::total 393760000 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::total 391543250 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::cpu.inst 474779000 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::cpu.inst 472595750 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::total 474779000 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::total 472595750 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::cpu.inst 474779000 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::cpu.inst 472595750 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::total 474779000 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::total 472595750 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 94493570 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::cpu.inst 94515004 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_accesses::total 94493570 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses::cpu.inst 168014300 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::cpu.inst 168035734 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.demand_accesses::total 168014300 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::total 168035734 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::cpu.inst 168014300 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::cpu.inst 168035734 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::total 168014300 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::total 168035734 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses
|
||||||
|
|
@ -603,14 +353,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042
|
||||||
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68893.707483 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68630.397968 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 68893.707483 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 68630.397968 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66256.099613 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65938.573594 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 66256.099613 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 65938.573594 # average WriteReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66691.810648 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.131339 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::total 66691.810648 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::total 66385.131339 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66691.810648 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.131339 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::total 66691.810648 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::total 66385.131339 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -621,30 +371,30 @@ system.cpu.dcache.fast_writes 0 # nu
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks::writebacks 654 # number of writebacks
|
system.cpu.dcache.writebacks::writebacks 654 # number of writebacks
|
||||||
system.cpu.dcache.writebacks::total 654 # number of writebacks
|
system.cpu.dcache.writebacks::total 654 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 211 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2746 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2743 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits::total 2746 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits::total 2743 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits::cpu.inst 2954 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits::cpu.inst 2954 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits::cpu.inst 2954 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits::cpu.inst 2954 # number of overall MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 970 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses::total 970 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3197 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3195 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses::total 3197 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64462750 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64327500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 64462750 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 64327500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 216604250 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 214316000 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 216604250 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 214316000 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281067000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 278643500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::total 281067000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::total 278643500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281067000 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 278643500 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::total 281067000 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::total 278643500 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses
|
||||||
|
|
@ -653,14 +403,264 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025
|
||||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66593.750000 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66317.010309 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66593.750000 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66317.010309 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67752.345949 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67078.560250 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67752.345949 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67078.560250 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67483.073229 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66901.200480 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67483.073229 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66901.200480 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67483.073229 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66901.200480 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67483.073229 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66901.200480 # average overall mshr miss latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.tags.replacements 3196 # number of replacements
|
||||||
|
system.cpu.icache.tags.tagsinuse 1918.781810 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.tags.total_refs 98776054 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.sampled_refs 5174 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.avg_refs 19090.849246 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1918.781810 # Average occupied blocks per requestor
|
||||||
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.936905 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_percent::total 0.936905 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.icache.tags.tag_accesses 197567630 # Number of tag accesses
|
||||||
|
system.cpu.icache.tags.data_accesses 197567630 # Number of data accesses
|
||||||
|
system.cpu.icache.ReadReq_hits::cpu.inst 98776054 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_hits::total 98776054 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits::cpu.inst 98776054 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_hits::total 98776054 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits::cpu.inst 98776054 # number of overall hits
|
||||||
|
system.cpu.icache.overall_hits::total 98776054 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses::cpu.inst 5174 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_misses::total 5174 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses::cpu.inst 5174 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_misses::total 5174 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses::cpu.inst 5174 # number of overall misses
|
||||||
|
system.cpu.icache.overall_misses::total 5174 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 293010500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.ReadReq_miss_latency::total 293010500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency::cpu.inst 293010500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency::total 293010500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency::cpu.inst 293010500 # number of overall miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency::total 293010500 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses::cpu.inst 98781228 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_accesses::total 98781228 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses::cpu.inst 98781228 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_accesses::total 98781228 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::cpu.inst 98781228 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::total 98781228 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.329726 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency::total 56631.329726 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.329726 # average overall miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency::total 56631.329726 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.329726 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency::total 56631.329726 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5174 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses::total 5174 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses::cpu.inst 5174 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses::total 5174 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses::cpu.inst 5174 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses::total 5174 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281053500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 281053500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281053500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency::total 281053500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281053500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency::total 281053500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.351759 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.351759 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.351759 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.351759 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.351759 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.351759 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.tags.tagsinuse 4426.924710 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.tags.total_refs 1494 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.avg_refs 0.283330 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::writebacks 373.138333 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4053.786377 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.011387 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123712 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::total 0.135099 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.l2cache.tags.tag_accesses 88415 # Number of tag accesses
|
||||||
|
system.cpu.l2cache.tags.data_accesses 88415 # Number of data accesses
|
||||||
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1405 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_hits::total 1405 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits::cpu.inst 61 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits::cpu.inst 1466 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_hits::total 1466 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits::cpu.inst 1466 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_hits::total 1466 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 4736 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_misses::total 4736 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::cpu.inst 3137 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses::cpu.inst 7873 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_misses::total 7873 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses::cpu.inst 7873 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_misses::total 7873 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 324986750 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::total 324986750 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 210671750 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::total 210671750 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 535658500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::total 535658500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 535658500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::total 535658500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6141 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 3198 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses::cpu.inst 9339 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_accesses::total 9339 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::cpu.inst 9339 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::total 9339 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.771210 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.771210 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.980926 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843024 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::total 0.843024 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843024 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::total 0.843024 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68620.513091 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68620.513091 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67157.076825 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67157.076825 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68037.406325 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::total 68037.406325 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68037.406325 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::total 68037.406325 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4736 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4736 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 3137 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7873 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::total 7873 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7873 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 265636250 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265636250 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 170998250 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 170998250 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 436634500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::total 436634500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 436634500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::total 436634500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771210 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980926 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843024 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843024 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56088.735220 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56088.735220 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54510.121135 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54510.121135 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55459.735806 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55459.735806 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55459.735806 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55459.735806 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadResp 6141 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10348 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count::total 19332 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331136 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size::total 639552 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::samples 9993 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::1 9993 100.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::total 9993 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.reqLayer0.occupancy 5650500 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.cpu.toL2Bus.respLayer0.occupancy 8565500 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.cpu.toL2Bus.respLayer1.occupancy 6972500 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.membus.trans_dist::ReadReq 4736 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadResp 4736 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadExReq 3137 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadExResp 3137 # Transaction distribution
|
||||||
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15746 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count::total 15746 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503872 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size::total 503872 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
|
system.membus.snoop_fanout::samples 7873 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::0 7873 100.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::total 7873 # Request fanout histogram
|
||||||
|
system.membus.reqLayer0.occupancy 9387500 # Layer occupancy (ticks)
|
||||||
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.membus.respLayer1.occupancy 73875500 # Layer occupancy (ticks)
|
||||||
|
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,38 +1,38 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.212377 # Number of seconds simulated
|
sim_seconds 0.216828 # Number of seconds simulated
|
||||||
sim_ticks 212377413000 # Number of ticks simulated
|
sim_ticks 216828260500 # Number of ticks simulated
|
||||||
final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 195363 # Simulator instruction rate (inst/s)
|
host_inst_rate 172164 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 234555 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 206702 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 151959329 # Simulator tick rate (ticks/s)
|
host_tick_rate 136721287 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 264884 # Number of bytes of host memory used
|
host_mem_usage 262128 # Number of bytes of host memory used
|
||||||
host_seconds 1397.59 # Real time elapsed on the host
|
host_seconds 1585.91 # Real time elapsed on the host
|
||||||
sim_insts 273037856 # Number of instructions simulated
|
sim_insts 273037856 # Number of instructions simulated
|
||||||
sim_ops 327812213 # Number of ops (including micro ops) simulated
|
sim_ops 327812213 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
system.clk_domain.clock 1000 # Clock period in ticks
|
system.clk_domain.clock 1000 # Clock period in ticks
|
||||||
system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.inst 485440 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::total 485312 # Number of bytes read from this memory
|
system.physmem.bytes_read::total 485440 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory
|
||||||
system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.inst 7585 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
|
system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory
|
||||||
system.physmem.bw_read::cpu.inst 2285139 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.inst 2238823 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::total 2285139 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu.inst 1031221 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu.inst 1010348 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::total 1031221 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.inst 2285139 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 2238823 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 2285139 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.readReqs 7583 # Number of read requests accepted
|
system.physmem.readReqs 7585 # Number of read requests accepted
|
||||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||||
system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue
|
system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue
|
||||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||||
system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM
|
system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM
|
||||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||||
system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side
|
system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side
|
||||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||||
|
|
@ -43,16 +43,16 @@ system.physmem.perBankRdBursts::2 628 # Pe
|
||||||
system.physmem.perBankRdBursts::3 541 # Per bank write bursts
|
system.physmem.perBankRdBursts::3 541 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::4 466 # Per bank write bursts
|
system.physmem.perBankRdBursts::4 466 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::5 349 # Per bank write bursts
|
system.physmem.perBankRdBursts::5 349 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::6 173 # Per bank write bursts
|
system.physmem.perBankRdBursts::6 172 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::7 228 # Per bank write bursts
|
system.physmem.perBankRdBursts::7 228 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::8 209 # Per bank write bursts
|
system.physmem.perBankRdBursts::8 209 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::9 310 # Per bank write bursts
|
system.physmem.perBankRdBursts::9 311 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::10 342 # Per bank write bursts
|
system.physmem.perBankRdBursts::10 342 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::11 428 # Per bank write bursts
|
system.physmem.perBankRdBursts::11 428 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::12 554 # Per bank write bursts
|
system.physmem.perBankRdBursts::12 554 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::13 705 # Per bank write bursts
|
system.physmem.perBankRdBursts::13 706 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::14 637 # Per bank write bursts
|
system.physmem.perBankRdBursts::14 637 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::15 540 # Per bank write bursts
|
system.physmem.perBankRdBursts::15 541 # Per bank write bursts
|
||||||
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
||||||
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
||||||
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
||||||
|
|
@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
||||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||||
system.physmem.totGap 212377186000 # Total gap between requests
|
system.physmem.totGap 216828031000 # Total gap between requests
|
||||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::6 7583 # Read request sizes (log2)
|
system.physmem.readPktSize::6 7585 # Read request sizes (log2)
|
||||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||||
|
|
@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr
|
||||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||||
system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||||
|
|
@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
||||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||||
system.physmem.bytesPerActivate::samples 1498 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::mean 322.691589 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::gmean 189.527839 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::gmean 189.317321 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::stdev 333.553355 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::stdev 333.826076 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::0-127 554 36.98% 36.98% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::0-127 548 36.41% 36.41% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::128-255 333 22.23% 59.21% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::128-255 349 23.19% 59.60% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::256-383 160 10.68% 69.89% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::256-383 163 10.83% 70.43% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::384-511 67 4.47% 74.37% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::512-639 72 4.81% 79.17% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::512-639 69 4.58% 79.53% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::640-767 61 4.07% 83.24% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::640-767 60 3.99% 83.52% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::768-895 33 2.19% 85.71% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation
|
||||||
system.physmem.totQLat 52768250 # Total ticks spent queuing
|
system.physmem.totQLat 50683250 # Total ticks spent queuing
|
||||||
system.physmem.totMemAccLat 194949500 # Total ticks spent from burst creation until serviced by the DRAM
|
system.physmem.totMemAccLat 192902000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||||
system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers
|
system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers
|
||||||
system.physmem.avgQLat 6958.76 # Average queueing delay per DRAM burst
|
system.physmem.avgQLat 6682.04 # Average queueing delay per DRAM burst
|
||||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||||
system.physmem.avgMemAccLat 25708.76 # Average memory access latency per DRAM burst
|
system.physmem.avgMemAccLat 25432.04 # Average memory access latency per DRAM burst
|
||||||
system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
|
system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||||
system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
|
system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||||
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
||||||
|
|
@ -212,68 +212,45 @@ system.physmem.busUtilRead 0.02 # Da
|
||||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||||
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
|
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
|
||||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||||
system.physmem.readRowHits 6077 # Number of row buffer hits during reads
|
system.physmem.readRowHits 6073 # Number of row buffer hits during reads
|
||||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||||
system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads
|
system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads
|
||||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||||
system.physmem.avgGap 28007013.85 # Average gap between requests
|
system.physmem.avgGap 28586424.65 # Average gap between requests
|
||||||
system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined
|
system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined
|
||||||
system.physmem.memoryStateTime::IDLE 202838268250 # Time in different power states
|
system.physmem.memoryStateTime::IDLE 207228229000 # Time in different power states
|
||||||
system.physmem.memoryStateTime::REF 7091500000 # Time in different power states
|
system.physmem.memoryStateTime::REF 7240220000 # Time in different power states
|
||||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states
|
system.physmem.memoryStateTime::ACT 2356912000 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||||
system.physmem.actEnergy::0 4921560 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::0 5012280 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem.actEnergy::1 6380640 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::1 6342840 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem.preEnergy::0 2685375 # Energy for precharge commands per rank (pJ)
|
system.physmem.preEnergy::0 2734875 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem.preEnergy::1 3481500 # Energy for precharge commands per rank (pJ)
|
system.physmem.preEnergy::1 3460875 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem.readEnergy::0 29897400 # Energy for read commands per rank (pJ)
|
system.physmem.readEnergy::0 29905200 # Energy for read commands per rank (pJ)
|
||||||
system.physmem.readEnergy::1 28977000 # Energy for read commands per rank (pJ)
|
system.physmem.readEnergy::1 29000400 # Energy for read commands per rank (pJ)
|
||||||
system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
||||||
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
|
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
|
||||||
system.physmem.refreshEnergy::0 13870974000 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::0 14161870320 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.refreshEnergy::1 13870974000 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::1 14161870320 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.actBackEnergy::0 5549858010 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::0 5651949285 # Energy for active background per rank (pJ)
|
||||||
system.physmem.actBackEnergy::1 5731608780 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::1 5745162240 # Energy for active background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::0 122553840750 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::0 125136528000 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::1 122394410250 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::1 125054762250 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.totalEnergy::0 142012177095 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::0 144987999960 # Total energy per rank (pJ)
|
||||||
system.physmem.totalEnergy::1 142035832170 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::1 145000598925 # Total energy per rank (pJ)
|
||||||
system.physmem.averagePower::0 668.700966 # Core power per rank (mW)
|
system.physmem.averagePower::0 668.689925 # Core power per rank (mW)
|
||||||
system.physmem.averagePower::1 668.812352 # Core power per rank (mW)
|
system.physmem.averagePower::1 668.748031 # Core power per rank (mW)
|
||||||
system.membus.trans_dist::ReadReq 4730 # Transaction distribution
|
system.cpu.branchPred.lookups 33221230 # Number of BP lookups
|
||||||
system.membus.trans_dist::ReadResp 4730 # Transaction distribution
|
system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted
|
||||||
system.membus.trans_dist::ReadExReq 2853 # Transaction distribution
|
system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect
|
||||||
system.membus.trans_dist::ReadExResp 2853 # Transaction distribution
|
system.cpu.branchPred.BTBLookups 17995686 # Number of BTB lookups
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes)
|
system.cpu.branchPred.BTBHits 15666979 # Number of BTB hits
|
||||||
system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 7583 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 7583 # Request fanout histogram
|
|
||||||
system.membus.reqLayer0.occupancy 8812500 # Layer occupancy (ticks)
|
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.membus.respLayer1.occupancy 70869750 # Layer occupancy (ticks)
|
|
||||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
||||||
system.cpu.branchPred.lookups 33146132 # Number of BP lookups
|
|
||||||
system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted
|
|
||||||
system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect
|
|
||||||
system.cpu.branchPred.BTBLookups 18038080 # Number of BTB lookups
|
|
||||||
system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits
|
|
||||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.branchPred.BTBHitPct 86.605842 # BTB Hit Percentage
|
system.cpu.branchPred.BTBHitPct 87.059638 # BTB Hit Percentage
|
||||||
system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target.
|
system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
|
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
|
||||||
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||||
|
|
@ -359,314 +336,75 @@ system.cpu.itb.hits 0 # DT
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||||
system.cpu.numCycles 424754826 # number of cpu cycles simulated
|
system.cpu.numCycles 433656521 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.committedInsts 273037856 # Number of instructions committed
|
system.cpu.committedInsts 273037856 # Number of instructions committed
|
||||||
system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed
|
system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed
|
||||||
system.cpu.discardedOps 4318159 # Number of ops (including micro ops) which were discarded before commit
|
system.cpu.discardedOps 4064410 # Number of ops (including micro ops) which were discarded before commit
|
||||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||||
system.cpu.cpi 1.555663 # CPI: cycles per instruction
|
system.cpu.cpi 1.588265 # CPI: cycles per instruction
|
||||||
system.cpu.ipc 0.642813 # IPC: instructions per cycle
|
system.cpu.ipc 0.629618 # IPC: instructions per cycle
|
||||||
system.cpu.tickCycles 420995875 # Number of cycles that the object actually ticked
|
system.cpu.tickCycles 430211091 # Number of cycles that the object actually ticked
|
||||||
system.cpu.idleCycles 3758951 # Total number of cycles that the object has spent stopped
|
system.cpu.idleCycles 3445430 # Total number of cycles that the object has spent stopped
|
||||||
system.cpu.icache.tags.replacements 36952 # number of replacements
|
system.cpu.dcache.tags.replacements 1354 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 1924.941243 # Cycle average of tags in use
|
system.cpu.dcache.tags.tagsinuse 3086.009332 # Cycle average of tags in use
|
||||||
system.cpu.icache.tags.total_refs 73208046 # Total number of references to valid blocks.
|
system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks.
|
system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.tags.avg_refs 1882.487233 # Average number of references to valid blocks.
|
system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941243 # Average occupied blocks per requestor
|
|
||||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.icache.tags.tag_accesses 146532761 # Number of tag accesses
|
|
||||||
system.cpu.icache.tags.data_accesses 146532761 # Number of data accesses
|
|
||||||
system.cpu.icache.ReadReq_hits::cpu.inst 73208046 # number of ReadReq hits
|
|
||||||
system.cpu.icache.ReadReq_hits::total 73208046 # number of ReadReq hits
|
|
||||||
system.cpu.icache.demand_hits::cpu.inst 73208046 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.demand_hits::total 73208046 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.overall_hits::cpu.inst 73208046 # number of overall hits
|
|
||||||
system.cpu.icache.overall_hits::total 73208046 # number of overall hits
|
|
||||||
system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses
|
|
||||||
system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses
|
|
||||||
system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses
|
|
||||||
system.cpu.icache.overall_misses::total 38890 # number of overall misses
|
|
||||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 705005996 # number of ReadReq miss cycles
|
|
||||||
system.cpu.icache.ReadReq_miss_latency::total 705005996 # number of ReadReq miss cycles
|
|
||||||
system.cpu.icache.demand_miss_latency::cpu.inst 705005996 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.demand_miss_latency::total 705005996 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.overall_miss_latency::cpu.inst 705005996 # number of overall miss cycles
|
|
||||||
system.cpu.icache.overall_miss_latency::total 705005996 # number of overall miss cycles
|
|
||||||
system.cpu.icache.ReadReq_accesses::cpu.inst 73246936 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.icache.ReadReq_accesses::total 73246936 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.icache.demand_accesses::cpu.inst 73246936 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.demand_accesses::total 73246936 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.overall_accesses::cpu.inst 73246936 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.overall_accesses::total 73246936 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18128.207663 # average ReadReq miss latency
|
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::total 18128.207663 # average ReadReq miss latency
|
|
||||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
|
|
||||||
system.cpu.icache.demand_avg_miss_latency::total 18128.207663 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_miss_latency::total 18128.207663 # average overall miss latency
|
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38890 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses::total 38890 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.demand_mshr_misses::cpu.inst 38890 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625833004 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 625833004 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625833004 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency::total 625833004 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625833004 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency::total 625833004 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16092.388892 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16092.388892 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2869 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 44409 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::5 44409 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 44409 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer0.occupancy 59030996 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer1.occupancy 7495960 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
||||||
system.cpu.l2cache.tags.tagsinuse 4198.136942 # Cycle average of tags in use
|
|
||||||
system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.tags.occ_blocks::writebacks 353.492030 # Average occupied blocks per requestor
|
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644913 # Average occupied blocks per requestor
|
|
||||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172241 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.l2cache.tags.tag_accesses 363785 # Number of tag accesses
|
|
||||||
system.cpu.l2cache.tags.data_accesses 363785 # Number of data accesses
|
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 35758 # number of ReadReq hits
|
|
||||||
system.cpu.l2cache.ReadReq_hits::total 35758 # number of ReadReq hits
|
|
||||||
system.cpu.l2cache.Writeback_hits::writebacks 1009 # number of Writeback hits
|
|
||||||
system.cpu.l2cache.Writeback_hits::total 1009 # number of Writeback hits
|
|
||||||
system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits
|
|
||||||
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
|
|
||||||
system.cpu.l2cache.demand_hits::cpu.inst 35774 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_hits::total 35774 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.overall_hits::cpu.inst 35774 # number of overall hits
|
|
||||||
system.cpu.l2cache.overall_hits::total 35774 # number of overall hits
|
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 4773 # number of ReadReq misses
|
|
||||||
system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses
|
|
||||||
system.cpu.l2cache.ReadExReq_misses::cpu.inst 2853 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.ReadExReq_misses::total 2853 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.demand_misses::cpu.inst 7626 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_misses::total 7626 # number of overall misses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328394750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::total 328394750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194183750 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::total 194183750 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 522578500 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::total 522578500 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 522578500 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::total 522578500 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.Writeback_accesses::total 1009 # number of Writeback accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2869 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::total 2869 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.demand_accesses::cpu.inst 43400 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_accesses::total 43400 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::cpu.inst 43400 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::total 43400 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117762 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.117762 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994423 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994423 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::total 0.175714 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.587471 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.587471 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68063.003856 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68063.003856 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::total 68525.898243 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::total 68525.898243 # average overall miss latency
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 43 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_hits::total 43 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 43 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 43 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4730 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2853 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 2853 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266721500 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266721500 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158370750 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158370750 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425092250 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::total 425092250 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425092250 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::total 425092250 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116701 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116701 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994423 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994423 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56389.323467 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56389.323467 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55510.252366 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55510.252366 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.tags.replacements 1353 # number of replacements
|
|
||||||
system.cpu.dcache.tags.tagsinuse 3085.890938 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890938 # Average occupied blocks per requestor
|
system.cpu.dcache.tags.occ_blocks::cpu.inst 3086.009332 # Average occupied blocks per requestor
|
||||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::cpu.inst 0.753420 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 671 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2433 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
|
||||||
system.cpu.dcache.tags.tag_accesses 337568172 # Number of tag accesses
|
system.cpu.dcache.tags.tag_accesses 337586705 # Number of tag accesses
|
||||||
system.cpu.dcache.tags.data_accesses 337568172 # Number of data accesses
|
system.cpu.dcache.tags.data_accesses 337586705 # Number of data accesses
|
||||||
system.cpu.dcache.ReadReq_hits::cpu.inst 86705299 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::cpu.inst 86714567 # number of ReadReq hits
|
||||||
system.cpu.dcache.ReadReq_hits::total 86705299 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::total 86714567 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::cpu.inst 82047451 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::cpu.inst 82047450 # number of WriteReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::total 82047450 # number of WriteReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.demand_hits::cpu.inst 168752750 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::cpu.inst 168762017 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.demand_hits::total 168752750 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::total 168762017 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits::cpu.inst 168752750 # number of overall hits
|
system.cpu.dcache.overall_hits::cpu.inst 168762017 # number of overall hits
|
||||||
system.cpu.dcache.overall_hits::total 168752750 # number of overall hits
|
system.cpu.dcache.overall_hits::total 168762017 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::cpu.inst 2063 # number of ReadReq misses
|
||||||
system.cpu.dcache.ReadReq_misses::total 2065 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::total 2063 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses::cpu.inst 5226 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses::cpu.inst 5227 # number of WriteReq misses
|
||||||
system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses::total 5227 # number of WriteReq misses
|
||||||
system.cpu.dcache.demand_misses::cpu.inst 7291 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses::cpu.inst 7290 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses
|
system.cpu.dcache.overall_misses::cpu.inst 7290 # number of overall misses
|
||||||
system.cpu.dcache.overall_misses::total 7291 # number of overall misses
|
system.cpu.dcache.overall_misses::total 7290 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127168958 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 126122956 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_latency::total 127168958 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::total 126122956 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358839500 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 360338500 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::total 358839500 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::total 360338500 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::cpu.inst 486008458 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::cpu.inst 486461456 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::total 486008458 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::total 486461456 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::cpu.inst 486008458 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::cpu.inst 486461456 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::total 486008458 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::total 486461456 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::cpu.inst 86716630 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses::cpu.inst 168760041 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::cpu.inst 168769307 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.demand_accesses::total 168760041 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::total 168769307 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::cpu.inst 168760041 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::cpu.inst 168769307 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::total 168760041 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::total 168769307 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses
|
||||||
|
|
@ -675,14 +413,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043
|
||||||
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61135.703345 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 61135.703345 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68937.918500 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 68937.918500 # average WriteReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::total 66658.683034 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::total 66729.966529 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::total 66658.683034 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::total 66729.966529 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -691,32 +429,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks::writebacks 1009 # number of writebacks
|
system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks
|
||||||
system.cpu.dcache.writebacks::total 1009 # number of writebacks
|
system.cpu.dcache.writebacks::total 1010 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 422 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits::cpu.inst 2781 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits::cpu.inst 2779 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits::total 2781 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits::cpu.inst 2781 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits::cpu.inst 2779 # number of overall MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits::total 2781 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2869 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2870 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses::total 2869 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::cpu.inst 4511 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.inst 4511 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100686290 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 99847542 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 100686290 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 99847542 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197251750 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197786250 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 197251750 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 197786250 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297938040 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297633792 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::total 297938040 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::total 297633792 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297938040 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297633792 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::total 297938040 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::total 297633792 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses
|
||||||
|
|
@ -725,14 +463,276 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027
|
||||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60845.546618 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60845.546618 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68915.069686 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68915.069686 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.tags.replacements 36927 # number of replacements
|
||||||
|
system.cpu.icache.tags.tagsinuse 1924.993605 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.tags.total_refs 73270396 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.avg_refs 1885.302491 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993605 # Average occupied blocks per requestor
|
||||||
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.icache.tags.tag_accesses 146657386 # Number of tag accesses
|
||||||
|
system.cpu.icache.tags.data_accesses 146657386 # Number of data accesses
|
||||||
|
system.cpu.icache.ReadReq_hits::cpu.inst 73270396 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_hits::total 73270396 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits::cpu.inst 73270396 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_hits::total 73270396 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits::cpu.inst 73270396 # number of overall hits
|
||||||
|
system.cpu.icache.overall_hits::total 73270396 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses
|
||||||
|
system.cpu.icache.overall_misses::total 38865 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 703294747 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.ReadReq_miss_latency::total 703294747 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency::cpu.inst 703294747 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency::total 703294747 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency::cpu.inst 703294747 # number of overall miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency::total 703294747 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses::cpu.inst 73309261 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_accesses::total 73309261 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses::cpu.inst 73309261 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_accesses::total 73309261 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::cpu.inst 73309261 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::total 73309261 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18095.838081 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency::total 18095.838081 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency::total 18095.838081 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency::total 18095.838081 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38865 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses::total 38865 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses::cpu.inst 38865 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses::total 38865 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses::cpu.inst 38865 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses::total 38865 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624165253 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 624165253 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624165253 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency::total 624165253 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624165253 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency::total 624165253 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16059.828972 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16059.828972 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.tags.tagsinuse 4198.559652 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.tags.total_refs 35809 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.sampled_refs 5647 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::writebacks 353.760812 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.798840 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117334 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5647 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1252 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172333 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.l2cache.tags.tag_accesses 363605 # Number of tag accesses
|
||||||
|
system.cpu.l2cache.tags.data_accesses 363605 # Number of data accesses
|
||||||
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 35730 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_hits::total 35730 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits::cpu.inst 35746 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_hits::total 35746 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits::cpu.inst 35746 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_hits::total 35746 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 4776 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_misses::total 4776 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::cpu.inst 2854 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses::cpu.inst 7630 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses::cpu.inst 7630 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_misses::total 7630 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 326194750 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::total 326194750 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194720750 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::total 194720750 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 520915500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::total 520915500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 520915500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::total 520915500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 40506 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2870 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses::cpu.inst 43376 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_accesses::total 43376 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::cpu.inst 43376 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::total 43376 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117908 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.117908 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994425 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175904 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175904 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68298.733250 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68298.733250 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68227.312544 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68227.312544 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::total 68272.018349 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::total 68272.018349 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 45 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 45 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 45 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits::total 45 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4731 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4731 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2854 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7585 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7585 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 264387500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264387500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158755250 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158755250 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 423142750 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::total 423142750 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 423142750 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::total 423142750 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116798 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994425 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55884.062566 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55884.062566 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55625.525578 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55625.525578 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77729 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count::total 87761 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487296 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size::total 2840640 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::samples 44386 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::5 44386 100.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::total 44386 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.cpu.toL2Bus.respLayer1.occupancy 7500208 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.membus.trans_dist::ReadReq 4731 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadResp 4731 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadExReq 2854 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadExResp 2854 # Transaction distribution
|
||||||
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
|
system.membus.snoop_fanout::samples 7585 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::total 7585 # Request fanout histogram
|
||||||
|
system.membus.reqLayer0.occupancy 8963500 # Layer occupancy (ticks)
|
||||||
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.membus.respLayer1.occupancy 71030250 # Layer occupancy (ticks)
|
||||||
|
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,46 +1,46 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.051523 # Number of seconds simulated
|
sim_seconds 0.052167 # Number of seconds simulated
|
||||||
sim_ticks 51522973500 # Number of ticks simulated
|
sim_ticks 52167245000 # Number of ticks simulated
|
||||||
final_tick 51522973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 52167245000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 234694 # Simulator instruction rate (inst/s)
|
host_inst_rate 231551 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 234694 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 231551 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 131574801 # Simulator tick rate (ticks/s)
|
host_tick_rate 131435822 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 241032 # Number of bytes of host memory used
|
host_mem_usage 240584 # Number of bytes of host memory used
|
||||||
host_seconds 391.59 # Real time elapsed on the host
|
host_seconds 396.90 # Real time elapsed on the host
|
||||||
sim_insts 91903089 # Number of instructions simulated
|
sim_insts 91903089 # Number of instructions simulated
|
||||||
sim_ops 91903089 # Number of ops (including micro ops) simulated
|
sim_ops 91903089 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
system.clk_domain.clock 1000 # Clock period in ticks
|
system.clk_domain.clock 1000 # Clock period in ticks
|
||||||
system.physmem.bytes_read::cpu.inst 340096 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.inst 340352 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::total 340096 # Number of bytes read from this memory
|
system.physmem.bytes_read::total 340352 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::cpu.inst 202432 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::total 202432 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory
|
||||||
system.physmem.num_reads::cpu.inst 5314 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.inst 5318 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::total 5314 # Number of read requests responded to by this memory
|
system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory
|
||||||
system.physmem.bw_read::cpu.inst 6600861 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.inst 6524247 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::total 6600861 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::total 6524247 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu.inst 3928966 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu.inst 3885350 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::total 3928966 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::total 3885350 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.inst 6600861 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 6524247 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 6600861 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 6524247 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.readReqs 5314 # Number of read requests accepted
|
system.physmem.readReqs 5318 # Number of read requests accepted
|
||||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||||
system.physmem.readBursts 5314 # Number of DRAM read bursts, including those serviced by the write queue
|
system.physmem.readBursts 5318 # Number of DRAM read bursts, including those serviced by the write queue
|
||||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||||
system.physmem.bytesReadDRAM 340096 # Total number of bytes read from DRAM
|
system.physmem.bytesReadDRAM 340352 # Total number of bytes read from DRAM
|
||||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||||
system.physmem.bytesReadSys 340096 # Total read bytes from the system interface side
|
system.physmem.bytesReadSys 340352 # Total read bytes from the system interface side
|
||||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||||
system.physmem.perBankRdBursts::0 468 # Per bank write bursts
|
system.physmem.perBankRdBursts::0 469 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::1 295 # Per bank write bursts
|
system.physmem.perBankRdBursts::1 295 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::2 307 # Per bank write bursts
|
system.physmem.perBankRdBursts::2 307 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::3 523 # Per bank write bursts
|
system.physmem.perBankRdBursts::3 524 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::4 224 # Per bank write bursts
|
system.physmem.perBankRdBursts::4 224 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::5 238 # Per bank write bursts
|
system.physmem.perBankRdBursts::5 238 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::6 222 # Per bank write bursts
|
system.physmem.perBankRdBursts::6 222 # Per bank write bursts
|
||||||
|
|
@ -48,8 +48,8 @@ system.physmem.perBankRdBursts::7 289 # Pe
|
||||||
system.physmem.perBankRdBursts::8 251 # Per bank write bursts
|
system.physmem.perBankRdBursts::8 251 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::9 282 # Per bank write bursts
|
system.physmem.perBankRdBursts::9 282 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::10 255 # Per bank write bursts
|
system.physmem.perBankRdBursts::10 255 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::11 260 # Per bank write bursts
|
system.physmem.perBankRdBursts::11 261 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::12 408 # Per bank write bursts
|
system.physmem.perBankRdBursts::12 409 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::13 344 # Per bank write bursts
|
system.physmem.perBankRdBursts::13 344 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::14 500 # Per bank write bursts
|
system.physmem.perBankRdBursts::14 500 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::15 448 # Per bank write bursts
|
system.physmem.perBankRdBursts::15 448 # Per bank write bursts
|
||||||
|
|
@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
||||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||||
system.physmem.totGap 51522892000 # Total gap between requests
|
system.physmem.totGap 52167163500 # Total gap between requests
|
||||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::6 5314 # Read request sizes (log2)
|
system.physmem.readPktSize::6 5318 # Read request sizes (log2)
|
||||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||||
|
|
@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr
|
||||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||||
system.physmem.rdQLenPdf::0 4906 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::0 4912 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::1 389 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::1 387 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||||
|
|
@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
||||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||||
system.physmem.bytesPerActivate::samples 963 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::samples 974 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::mean 352.232606 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::mean 348.254620 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::gmean 215.271932 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::gmean 211.254822 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::stdev 332.609683 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::stdev 332.143137 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::0-127 308 31.98% 31.98% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::0-127 322 33.06% 33.06% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::128-255 198 20.56% 52.54% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::128-255 190 19.51% 52.57% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::256-383 99 10.28% 62.82% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::256-383 96 9.86% 62.42% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::384-511 77 8.00% 70.82% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::384-511 102 10.47% 72.90% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::512-639 83 8.62% 79.44% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::512-639 61 6.26% 79.16% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::640-767 29 3.01% 82.45% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::640-767 36 3.70% 82.85% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::768-895 26 2.70% 85.15% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::768-895 25 2.57% 85.42% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::896-1023 28 2.91% 88.06% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::896-1023 25 2.57% 87.99% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::1024-1151 115 11.94% 100.00% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::1024-1151 117 12.01% 100.00% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::total 963 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::total 974 # Bytes accessed per row activation
|
||||||
system.physmem.totQLat 35638500 # Total ticks spent queuing
|
system.physmem.totQLat 31955000 # Total ticks spent queuing
|
||||||
system.physmem.totMemAccLat 135276000 # Total ticks spent from burst creation until serviced by the DRAM
|
system.physmem.totMemAccLat 131667500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||||
system.physmem.totBusLat 26570000 # Total ticks spent in databus transfers
|
system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers
|
||||||
system.physmem.avgQLat 6706.53 # Average queueing delay per DRAM burst
|
system.physmem.avgQLat 6008.84 # Average queueing delay per DRAM burst
|
||||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||||
system.physmem.avgMemAccLat 25456.53 # Average memory access latency per DRAM burst
|
system.physmem.avgMemAccLat 24758.84 # Average memory access latency per DRAM burst
|
||||||
system.physmem.avgRdBW 6.60 # Average DRAM read bandwidth in MiByte/s
|
system.physmem.avgRdBW 6.52 # Average DRAM read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||||
system.physmem.avgRdBWSys 6.60 # Average system read bandwidth in MiByte/s
|
system.physmem.avgRdBWSys 6.52 # Average system read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||||
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
||||||
|
|
@ -212,88 +212,65 @@ system.physmem.busUtilRead 0.05 # Da
|
||||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||||
system.physmem.readRowHits 4346 # Number of row buffer hits during reads
|
system.physmem.readRowHits 4336 # Number of row buffer hits during reads
|
||||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||||
system.physmem.readRowHitRate 81.78 # Row buffer hit rate for reads
|
system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads
|
||||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||||
system.physmem.avgGap 9695689.12 # Average gap between requests
|
system.physmem.avgGap 9809545.60 # Average gap between requests
|
||||||
system.physmem.pageHitRate 81.78 # Row buffer hit rate, read and write combined
|
system.physmem.pageHitRate 81.53 # Row buffer hit rate, read and write combined
|
||||||
system.physmem.memoryStateTime::IDLE 48467499750 # Time in different power states
|
system.physmem.memoryStateTime::IDLE 49062382500 # Time in different power states
|
||||||
system.physmem.memoryStateTime::REF 1720420000 # Time in different power states
|
system.physmem.memoryStateTime::REF 1741740000 # Time in different power states
|
||||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT 1333970250 # Time in different power states
|
system.physmem.memoryStateTime::ACT 1356240000 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||||
system.physmem.actEnergy::0 3470040 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::0 3530520 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem.actEnergy::1 3810240 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::1 3787560 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem.preEnergy::0 1893375 # Energy for precharge commands per rank (pJ)
|
system.physmem.preEnergy::0 1926375 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem.preEnergy::1 2079000 # Energy for precharge commands per rank (pJ)
|
system.physmem.preEnergy::1 2066625 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem.readEnergy::0 19999200 # Energy for read commands per rank (pJ)
|
system.physmem.readEnergy::0 19827600 # Energy for read commands per rank (pJ)
|
||||||
system.physmem.readEnergy::1 21340800 # Energy for read commands per rank (pJ)
|
system.physmem.readEnergy::1 21216000 # Energy for read commands per rank (pJ)
|
||||||
system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
||||||
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
|
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
|
||||||
system.physmem.refreshEnergy::0 3365141520 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::0 3406843440 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.refreshEnergy::1 3365141520 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::1 3406843440 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.actBackEnergy::0 1727742960 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::0 1740241350 # Energy for active background per rank (pJ)
|
||||||
system.physmem.actBackEnergy::1 1771093170 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::1 1807017705 # Energy for active background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::0 29397561750 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::0 29769681750 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::1 29359535250 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::1 29711106000 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.totalEnergy::0 34515808845 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::0 34942051035 # Total energy per rank (pJ)
|
||||||
system.physmem.totalEnergy::1 34522999980 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::1 34952037330 # Total energy per rank (pJ)
|
||||||
system.physmem.averagePower::0 669.925309 # Core power per rank (mW)
|
system.physmem.averagePower::0 669.896806 # Core power per rank (mW)
|
||||||
system.physmem.averagePower::1 670.064883 # Core power per rank (mW)
|
system.physmem.averagePower::1 670.088260 # Core power per rank (mW)
|
||||||
system.membus.trans_dist::ReadReq 3595 # Transaction distribution
|
system.cpu.branchPred.lookups 11476347 # Number of BP lookups
|
||||||
system.membus.trans_dist::ReadResp 3595 # Transaction distribution
|
system.cpu.branchPred.condPredicted 8235349 # Number of conditional branches predicted
|
||||||
system.membus.trans_dist::ReadExReq 1719 # Transaction distribution
|
system.cpu.branchPred.condIncorrect 785844 # Number of conditional branches incorrect
|
||||||
system.membus.trans_dist::ReadExResp 1719 # Transaction distribution
|
system.cpu.branchPred.BTBLookups 6672654 # Number of BTB lookups
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10628 # Packet count per connected master and slave (bytes)
|
system.cpu.branchPred.BTBHits 5371509 # Number of BTB hits
|
||||||
system.membus.pkt_count::total 10628 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340096 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 5314 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 5314 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 5314 # Request fanout histogram
|
|
||||||
system.membus.reqLayer0.occupancy 6106500 # Layer occupancy (ticks)
|
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.membus.respLayer1.occupancy 49715250 # Layer occupancy (ticks)
|
|
||||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
||||||
system.cpu.branchPred.lookups 11407319 # Number of BP lookups
|
|
||||||
system.cpu.branchPred.condPredicted 8177175 # Number of conditional branches predicted
|
|
||||||
system.cpu.branchPred.condIncorrect 788662 # Number of conditional branches incorrect
|
|
||||||
system.cpu.branchPred.BTBLookups 6672694 # Number of BTB lookups
|
|
||||||
system.cpu.branchPred.BTBHits 5348459 # Number of BTB hits
|
|
||||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.branchPred.BTBHitPct 80.154417 # BTB Hit Percentage
|
system.cpu.branchPred.BTBHitPct 80.500338 # BTB Hit Percentage
|
||||||
system.cpu.branchPred.usedRAS 1172952 # Number of times the RAS was used to get a target.
|
system.cpu.branchPred.usedRAS 1176736 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
|
system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
|
||||||
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 20390003 # DTB read hits
|
system.cpu.dtb.read_hits 20396755 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 46972 # DTB read misses
|
system.cpu.dtb.read_misses 47141 # DTB read misses
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.read_accesses 20436975 # DTB read accesses
|
system.cpu.dtb.read_accesses 20443896 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 6579991 # DTB write hits
|
system.cpu.dtb.write_hits 6580249 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 273 # DTB write misses
|
system.cpu.dtb.write_misses 266 # DTB write misses
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.dtb.write_accesses 6580264 # DTB write accesses
|
system.cpu.dtb.write_accesses 6580515 # DTB write accesses
|
||||||
system.cpu.dtb.data_hits 26969994 # DTB hits
|
system.cpu.dtb.data_hits 26977004 # DTB hits
|
||||||
system.cpu.dtb.data_misses 47245 # DTB misses
|
system.cpu.dtb.data_misses 47407 # DTB misses
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.dtb.data_accesses 27017239 # DTB accesses
|
system.cpu.dtb.data_accesses 27024411 # DTB accesses
|
||||||
system.cpu.itb.fetch_hits 22956157 # ITB hits
|
system.cpu.itb.fetch_hits 23068125 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 88 # ITB misses
|
system.cpu.itb.fetch_misses 88 # ITB misses
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.fetch_accesses 22956245 # ITB accesses
|
system.cpu.itb.fetch_accesses 23068213 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
|
|
@ -307,255 +284,26 @@ system.cpu.itb.data_misses 0 # DT
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||||
system.cpu.numCycles 103045947 # number of cpu cycles simulated
|
system.cpu.numCycles 104334490 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.committedInsts 91903089 # Number of instructions committed
|
system.cpu.committedInsts 91903089 # Number of instructions committed
|
||||||
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
|
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
|
||||||
system.cpu.discardedOps 2250214 # Number of ops (including micro ops) which were discarded before commit
|
system.cpu.discardedOps 2153944 # Number of ops (including micro ops) which were discarded before commit
|
||||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||||
system.cpu.cpi 1.121246 # CPI: cycles per instruction
|
system.cpu.cpi 1.135266 # CPI: cycles per instruction
|
||||||
system.cpu.ipc 0.891865 # IPC: instructions per cycle
|
system.cpu.ipc 0.880851 # IPC: instructions per cycle
|
||||||
system.cpu.tickCycles 100852672 # Number of cycles that the object actually ticked
|
system.cpu.tickCycles 102681426 # Number of cycles that the object actually ticked
|
||||||
system.cpu.idleCycles 2193275 # Total number of cycles that the object has spent stopped
|
system.cpu.idleCycles 1653064 # Total number of cycles that the object has spent stopped
|
||||||
system.cpu.icache.tags.replacements 13697 # number of replacements
|
|
||||||
system.cpu.icache.tags.tagsinuse 1640.302767 # Cycle average of tags in use
|
|
||||||
system.cpu.icache.tags.total_refs 22940496 # Total number of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.sampled_refs 15661 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.avg_refs 1464.816806 # Average number of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.302767 # Average occupied blocks per requestor
|
|
||||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.800929 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.tags.occ_percent::total 0.800929 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 670 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.icache.tags.tag_accesses 45927975 # Number of tag accesses
|
|
||||||
system.cpu.icache.tags.data_accesses 45927975 # Number of data accesses
|
|
||||||
system.cpu.icache.ReadReq_hits::cpu.inst 22940496 # number of ReadReq hits
|
|
||||||
system.cpu.icache.ReadReq_hits::total 22940496 # number of ReadReq hits
|
|
||||||
system.cpu.icache.demand_hits::cpu.inst 22940496 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.demand_hits::total 22940496 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.overall_hits::cpu.inst 22940496 # number of overall hits
|
|
||||||
system.cpu.icache.overall_hits::total 22940496 # number of overall hits
|
|
||||||
system.cpu.icache.ReadReq_misses::cpu.inst 15661 # number of ReadReq misses
|
|
||||||
system.cpu.icache.ReadReq_misses::total 15661 # number of ReadReq misses
|
|
||||||
system.cpu.icache.demand_misses::cpu.inst 15661 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.demand_misses::total 15661 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.overall_misses::cpu.inst 15661 # number of overall misses
|
|
||||||
system.cpu.icache.overall_misses::total 15661 # number of overall misses
|
|
||||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 386976750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.icache.ReadReq_miss_latency::total 386976750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.icache.demand_miss_latency::cpu.inst 386976750 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.demand_miss_latency::total 386976750 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.overall_miss_latency::cpu.inst 386976750 # number of overall miss cycles
|
|
||||||
system.cpu.icache.overall_miss_latency::total 386976750 # number of overall miss cycles
|
|
||||||
system.cpu.icache.ReadReq_accesses::cpu.inst 22956157 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.icache.ReadReq_accesses::total 22956157 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.icache.demand_accesses::cpu.inst 22956157 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.demand_accesses::total 22956157 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.overall_accesses::cpu.inst 22956157 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.overall_accesses::total 22956157 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24709.581125 # average ReadReq miss latency
|
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::total 24709.581125 # average ReadReq miss latency
|
|
||||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24709.581125 # average overall miss latency
|
|
||||||
system.cpu.icache.demand_avg_miss_latency::total 24709.581125 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24709.581125 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_miss_latency::total 24709.581125 # average overall miss latency
|
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15661 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses::total 15661 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.demand_mshr_misses::cpu.inst 15661 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.demand_mshr_misses::total 15661 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15661 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_misses::total 15661 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 354287250 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 354287250 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 354287250 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency::total 354287250 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 354287250 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency::total 354287250 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22622.262308 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22622.262308 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22622.262308 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22622.262308 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22622.262308 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22622.262308 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 16146 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 16146 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31322 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count::total 35889 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1002304 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size::total 1151872 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 17998 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 17998 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 17998 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 9106000 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer0.occupancy 24175250 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
||||||
system.cpu.l2cache.tags.tagsinuse 2477.584038 # Cycle average of tags in use
|
|
||||||
system.cpu.l2cache.tags.total_refs 12565 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.sampled_refs 3661 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.avg_refs 3.432122 # Average number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.790277 # Average occupied blocks per requestor
|
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.793761 # Average occupied blocks per requestor
|
|
||||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075067 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_percent::total 0.075610 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3661 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 768 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 181 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2504 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111725 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.l2cache.tags.tag_accesses 149390 # Number of tag accesses
|
|
||||||
system.cpu.l2cache.tags.data_accesses 149390 # Number of data accesses
|
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 12551 # number of ReadReq hits
|
|
||||||
system.cpu.l2cache.ReadReq_hits::total 12551 # number of ReadReq hits
|
|
||||||
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
|
|
||||||
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
|
|
||||||
system.cpu.l2cache.ReadExReq_hits::cpu.inst 26 # number of ReadExReq hits
|
|
||||||
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
|
||||||
system.cpu.l2cache.demand_hits::cpu.inst 12577 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_hits::total 12577 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.overall_hits::cpu.inst 12577 # number of overall hits
|
|
||||||
system.cpu.l2cache.overall_hits::total 12577 # number of overall hits
|
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 3595 # number of ReadReq misses
|
|
||||||
system.cpu.l2cache.ReadReq_misses::total 3595 # number of ReadReq misses
|
|
||||||
system.cpu.l2cache.ReadExReq_misses::cpu.inst 1719 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.demand_misses::cpu.inst 5314 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_misses::total 5314 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.overall_misses::cpu.inst 5314 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_misses::total 5314 # number of overall misses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 246128750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::total 246128750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 116497000 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::total 116497000 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 362625750 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::total 362625750 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 362625750 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::total 362625750 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 16146 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::total 16146 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1745 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.demand_accesses::cpu.inst 17891 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_accesses::total 17891 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::cpu.inst 17891 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::total 17891 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.222656 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.222656 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.985100 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.297021 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::total 0.297021 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.297021 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::total 0.297021 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68464.186370 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68464.186370 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67770.215241 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67770.215241 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68239.697027 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::total 68239.697027 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68239.697027 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::total 68239.697027 # average overall miss latency
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3595 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::total 3595 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1719 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 5314 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::total 5314 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 5314 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 5314 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 200952250 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200952250 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 94943500 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94943500 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295895750 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::total 295895750 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295895750 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::total 295895750 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222656 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222656 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.297021 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.297021 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55897.705146 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55897.705146 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55231.820826 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55231.820826 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55682.301468 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55682.301468 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55682.301468 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55682.301468 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||||
system.cpu.dcache.tags.tagsinuse 1448.555792 # Cycle average of tags in use
|
system.cpu.dcache.tags.tagsinuse 1448.700924 # Cycle average of tags in use
|
||||||
system.cpu.dcache.tags.total_refs 26545428 # Total number of references to valid blocks.
|
system.cpu.dcache.tags.total_refs 26568138 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
|
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.tags.avg_refs 11903.779372 # Average number of references to valid blocks.
|
system.cpu.dcache.tags.avg_refs 11913.963229 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.555792 # Average occupied blocks per requestor
|
system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.700924 # Average occupied blocks per requestor
|
||||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.353651 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::cpu.inst 0.353687 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.tags.occ_percent::total 0.353651 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::total 0.353687 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
|
||||||
|
|
@ -563,16 +311,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id
|
||||||
system.cpu.dcache.tags.tag_accesses 53099946 # Number of tag accesses
|
system.cpu.dcache.tags.tag_accesses 53145366 # Number of tag accesses
|
||||||
system.cpu.dcache.tags.data_accesses 53099946 # Number of data accesses
|
system.cpu.dcache.tags.data_accesses 53145366 # Number of data accesses
|
||||||
system.cpu.dcache.ReadReq_hits::cpu.inst 20047236 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::cpu.inst 20069946 # number of ReadReq hits
|
||||||
system.cpu.dcache.ReadReq_hits::total 20047236 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::total 20069946 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::cpu.inst 6498192 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::cpu.inst 6498192 # number of WriteReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits
|
||||||
system.cpu.dcache.demand_hits::cpu.inst 26545428 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::cpu.inst 26568138 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.demand_hits::total 26545428 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::total 26568138 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits::cpu.inst 26545428 # number of overall hits
|
system.cpu.dcache.overall_hits::cpu.inst 26568138 # number of overall hits
|
||||||
system.cpu.dcache.overall_hits::total 26545428 # number of overall hits
|
system.cpu.dcache.overall_hits::total 26568138 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses
|
||||||
system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses::cpu.inst 2911 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses::cpu.inst 2911 # number of WriteReq misses
|
||||||
|
|
@ -581,22 +329,22 @@ system.cpu.dcache.demand_misses::cpu.inst 3430 # n
|
||||||
system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses
|
system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses
|
||||||
system.cpu.dcache.overall_misses::total 3430 # number of overall misses
|
system.cpu.dcache.overall_misses::total 3430 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 37054000 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 37712750 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_latency::total 37054000 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::total 37712750 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 196991000 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 194587500 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::total 196991000 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::total 194587500 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::cpu.inst 234045000 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::cpu.inst 232300250 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::total 234045000 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::total 232300250 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::cpu.inst 234045000 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::cpu.inst 232300250 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::total 234045000 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::total 232300250 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 20047755 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::cpu.inst 20070465 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_accesses::total 20047755 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::total 20070465 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses::cpu.inst 26548858 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::cpu.inst 26571568 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.demand_accesses::total 26548858 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::total 26571568 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::cpu.inst 26548858 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::cpu.inst 26571568 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::total 26548858 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::total 26571568 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses
|
||||||
|
|
@ -605,14 +353,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129
|
||||||
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71394.990366 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72664.258189 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 71394.990366 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 72664.258189 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67671.246994 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66845.585709 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 67671.246994 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 66845.585709 # average WriteReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68234.693878 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67726.020408 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::total 68234.693878 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::total 67726.020408 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68234.693878 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67726.020408 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::total 68234.693878 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::total 67726.020408 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -639,14 +387,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 2230
|
||||||
system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 33506000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 34134000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33506000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 34134000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 118502500 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 117191500 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 118502500 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 117191500 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152008500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 151325500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::total 152008500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::total 151325500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152008500 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 151325500 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::total 152008500 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::total 151325500 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses
|
||||||
|
|
@ -655,14 +403,266 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084
|
||||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69084.536082 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 70379.381443 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69084.536082 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70379.381443 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67909.742120 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67158.452722 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67909.742120 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67158.452722 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68165.246637 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67858.968610 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68165.246637 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67858.968610 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68165.246637 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67858.968610 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68165.246637 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67858.968610 # average overall mshr miss latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.tags.replacements 13871 # number of replacements
|
||||||
|
system.cpu.icache.tags.tagsinuse 1640.666168 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.tags.total_refs 23052289 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.sampled_refs 15835 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.avg_refs 1455.780802 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.666168 # Average occupied blocks per requestor
|
||||||
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.801107 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_percent::total 0.801107 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 669 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.icache.tags.tag_accesses 46152085 # Number of tag accesses
|
||||||
|
system.cpu.icache.tags.data_accesses 46152085 # Number of data accesses
|
||||||
|
system.cpu.icache.ReadReq_hits::cpu.inst 23052289 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_hits::total 23052289 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits::cpu.inst 23052289 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_hits::total 23052289 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits::cpu.inst 23052289 # number of overall hits
|
||||||
|
system.cpu.icache.overall_hits::total 23052289 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses::cpu.inst 15836 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_misses::total 15836 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses::cpu.inst 15836 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_misses::total 15836 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses::cpu.inst 15836 # number of overall misses
|
||||||
|
system.cpu.icache.overall_misses::total 15836 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 386603500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.ReadReq_miss_latency::total 386603500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency::cpu.inst 386603500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency::total 386603500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency::cpu.inst 386603500 # number of overall miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency::total 386603500 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses::cpu.inst 23068125 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_accesses::total 23068125 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses::cpu.inst 23068125 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_accesses::total 23068125 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::cpu.inst 23068125 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::total 23068125 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24412.951503 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency::total 24412.951503 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24412.951503 # average overall miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency::total 24412.951503 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24412.951503 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency::total 24412.951503 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15836 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses::total 15836 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses::cpu.inst 15836 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses::total 15836 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses::cpu.inst 15836 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses::total 15836 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353567500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 353567500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353567500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency::total 353567500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353567500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency::total 353567500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22326.818641 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22326.818641 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22326.818641 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 22326.818641 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22326.818641 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 22326.818641 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.tags.tagsinuse 2479.834280 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.tags.total_refs 12735 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.sampled_refs 3665 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::writebacks 17.780071 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.054210 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075136 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3665 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 768 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 182 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2506 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111847 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.l2cache.tags.tag_accesses 150786 # Number of tag accesses
|
||||||
|
system.cpu.l2cache.tags.data_accesses 150786 # Number of data accesses
|
||||||
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 12721 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_hits::total 12721 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits::cpu.inst 26 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits::cpu.inst 12747 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_hits::total 12747 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits::cpu.inst 12747 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_hits::total 12747 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3599 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_misses::total 3599 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::cpu.inst 1719 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses::cpu.inst 5318 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_misses::total 5318 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses::cpu.inst 5318 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_misses::total 5318 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 244164500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::total 244164500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 115186000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::total 115186000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 359350500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::total 359350500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 359350500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::total 359350500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 16320 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::total 16320 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1745 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses::cpu.inst 18065 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_accesses::total 18065 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::cpu.inst 18065 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::total 18065 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.220527 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.220527 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.985100 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.294381 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::total 0.294381 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.294381 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::total 0.294381 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67842.317310 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67842.317310 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67007.562536 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67007.562536 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67572.489658 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::total 67572.489658 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67572.489658 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::total 67572.489658 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3599 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::total 3599 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1719 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 5318 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::total 5318 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 5318 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 198927000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198927000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 93369000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93369000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 292296000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::total 292296000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 292296000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::total 292296000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.220527 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.294381 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.294381 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55272.853570 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55272.853570 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54315.881326 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54315.881326 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54963.520120 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54963.520120 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54963.520120 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54963.520120 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadResp 16320 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31670 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count::total 36237 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013440 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size::total 1163008 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::samples 18172 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::1 18172 100.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::total 18172 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.reqLayer0.occupancy 9193000 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.cpu.toL2Bus.respLayer0.occupancy 24435500 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.cpu.toL2Bus.respLayer1.occupancy 3734500 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.membus.trans_dist::ReadReq 3599 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadResp 3599 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadExReq 1719 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadExResp 1719 # Transaction distribution
|
||||||
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10636 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count::total 10636 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340352 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size::total 340352 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
|
system.membus.snoop_fanout::samples 5318 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::0 5318 100.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::total 5318 # Request fanout histogram
|
||||||
|
system.membus.reqLayer0.occupancy 6477500 # Layer occupancy (ticks)
|
||||||
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.membus.respLayer1.occupancy 50028000 # Layer occupancy (ticks)
|
||||||
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,38 +1,38 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.131652 # Number of seconds simulated
|
sim_seconds 0.131746 # Number of seconds simulated
|
||||||
sim_ticks 131652469500 # Number of ticks simulated
|
sim_ticks 131745950000 # Number of ticks simulated
|
||||||
final_tick 131652469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 162179 # Simulator instruction rate (inst/s)
|
host_inst_rate 190259 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 170963 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 200564 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 123906567 # Simulator tick rate (ticks/s)
|
host_tick_rate 145463120 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 259776 # Number of bytes of host memory used
|
host_mem_usage 256996 # Number of bytes of host memory used
|
||||||
host_seconds 1062.51 # Real time elapsed on the host
|
host_seconds 905.70 # Real time elapsed on the host
|
||||||
sim_insts 172317809 # Number of instructions simulated
|
sim_insts 172317809 # Number of instructions simulated
|
||||||
sim_ops 181650742 # Number of ops (including micro ops) simulated
|
sim_ops 181650742 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
system.clk_domain.clock 1000 # Clock period in ticks
|
system.clk_domain.clock 1000 # Clock period in ticks
|
||||||
system.physmem.bytes_read::cpu.inst 247616 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.inst 247488 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::total 247616 # Number of bytes read from this memory
|
system.physmem.bytes_read::total 247488 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory
|
||||||
system.physmem.num_reads::cpu.inst 3869 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.inst 3867 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory
|
system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory
|
||||||
system.physmem.bw_read::cpu.inst 1880831 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.inst 1878525 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::total 1880831 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu.inst 1050523 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::total 1050523 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.inst 1880831 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 1878525 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 1880831 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.readReqs 3869 # Number of read requests accepted
|
system.physmem.readReqs 3867 # Number of read requests accepted
|
||||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||||
system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue
|
system.physmem.readBursts 3867 # Number of DRAM read bursts, including those serviced by the write queue
|
||||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||||
system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM
|
system.physmem.bytesReadDRAM 247488 # Total number of bytes read from DRAM
|
||||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||||
system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side
|
system.physmem.bytesReadSys 247488 # Total read bytes from the system interface side
|
||||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||||
|
|
@ -42,14 +42,14 @@ system.physmem.perBankRdBursts::1 217 # Pe
|
||||||
system.physmem.perBankRdBursts::2 135 # Per bank write bursts
|
system.physmem.perBankRdBursts::2 135 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::3 313 # Per bank write bursts
|
system.physmem.perBankRdBursts::3 313 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::4 308 # Per bank write bursts
|
system.physmem.perBankRdBursts::4 308 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::5 306 # Per bank write bursts
|
system.physmem.perBankRdBursts::5 305 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::6 273 # Per bank write bursts
|
system.physmem.perBankRdBursts::6 273 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::7 222 # Per bank write bursts
|
system.physmem.perBankRdBursts::7 222 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::8 249 # Per bank write bursts
|
system.physmem.perBankRdBursts::8 249 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::9 218 # Per bank write bursts
|
system.physmem.perBankRdBursts::9 218 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::10 295 # Per bank write bursts
|
system.physmem.perBankRdBursts::10 295 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::11 201 # Per bank write bursts
|
system.physmem.perBankRdBursts::11 199 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::12 182 # Per bank write bursts
|
system.physmem.perBankRdBursts::12 183 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::13 218 # Per bank write bursts
|
system.physmem.perBankRdBursts::13 218 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::14 224 # Per bank write bursts
|
system.physmem.perBankRdBursts::14 224 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::15 203 # Per bank write bursts
|
system.physmem.perBankRdBursts::15 203 # Per bank write bursts
|
||||||
|
|
@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
||||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||||
system.physmem.totGap 131652381500 # Total gap between requests
|
system.physmem.totGap 131745861500 # Total gap between requests
|
||||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::6 3869 # Read request sizes (log2)
|
system.physmem.readPktSize::6 3867 # Read request sizes (log2)
|
||||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||||
|
|
@ -87,8 +87,8 @@ system.physmem.writePktSize::4 0 # Wr
|
||||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||||
system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::1 241 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||||
|
|
@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
||||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||||
system.physmem.bytesPerActivate::samples 904 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::mean 272.070796 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::mean 269.543860 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::gmean 178.793599 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::gmean 178.691365 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::stdev 280.048713 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::stdev 273.658023 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::0-127 264 29.20% 29.20% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::0-127 266 29.17% 29.17% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::128-255 351 38.83% 68.03% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::128-255 353 38.71% 67.87% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::256-383 86 9.51% 77.54% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::256-383 82 8.99% 76.86% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::384-511 48 5.31% 82.85% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::384-511 61 6.69% 83.55% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::512-639 35 3.87% 86.73% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::512-639 33 3.62% 87.17% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::640-767 23 2.54% 89.27% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::640-767 27 2.96% 90.13% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::768-895 17 1.88% 91.15% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::896-1023 16 1.77% 92.92% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::1024-1151 64 7.08% 100.00% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::total 904 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation
|
||||||
system.physmem.totQLat 27698500 # Total ticks spent queuing
|
system.physmem.totQLat 28129500 # Total ticks spent queuing
|
||||||
system.physmem.totMemAccLat 100242250 # Total ticks spent from burst creation until serviced by the DRAM
|
system.physmem.totMemAccLat 100635750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||||
system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers
|
system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers
|
||||||
system.physmem.avgQLat 7159.09 # Average queueing delay per DRAM burst
|
system.physmem.avgQLat 7274.24 # Average queueing delay per DRAM burst
|
||||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||||
system.physmem.avgMemAccLat 25909.09 # Average memory access latency per DRAM burst
|
system.physmem.avgMemAccLat 26024.24 # Average memory access latency per DRAM burst
|
||||||
system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s
|
system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||||
system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s
|
system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s
|
||||||
|
|
@ -212,68 +212,45 @@ system.physmem.busUtilRead 0.01 # Da
|
||||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||||
system.physmem.readRowHits 2960 # Number of row buffer hits during reads
|
system.physmem.readRowHits 2950 # Number of row buffer hits during reads
|
||||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||||
system.physmem.readRowHitRate 76.51 # Row buffer hit rate for reads
|
system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads
|
||||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||||
system.physmem.avgGap 34027495.86 # Average gap between requests
|
system.physmem.avgGap 34069268.55 # Average gap between requests
|
||||||
system.physmem.pageHitRate 76.51 # Row buffer hit rate, read and write combined
|
system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined
|
||||||
system.physmem.memoryStateTime::IDLE 125800686500 # Time in different power states
|
system.physmem.memoryStateTime::IDLE 125856871250 # Time in different power states
|
||||||
system.physmem.memoryStateTime::REF 4396080000 # Time in different power states
|
system.physmem.memoryStateTime::REF 4399200000 # Time in different power states
|
||||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT 1453435500 # Time in different power states
|
system.physmem.memoryStateTime::ACT 1487617250 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||||
system.physmem.actEnergy::0 3039120 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::0 3092040 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem.actEnergy::1 3780000 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::1 3787560 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem.preEnergy::0 1658250 # Energy for precharge commands per rank (pJ)
|
system.physmem.preEnergy::0 1687125 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem.preEnergy::1 2062500 # Energy for precharge commands per rank (pJ)
|
system.physmem.preEnergy::1 2066625 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem.readEnergy::0 16185000 # Energy for read commands per rank (pJ)
|
system.physmem.readEnergy::0 16177200 # Energy for read commands per rank (pJ)
|
||||||
system.physmem.readEnergy::1 13774800 # Energy for read commands per rank (pJ)
|
system.physmem.readEnergy::1 13767000 # Energy for read commands per rank (pJ)
|
||||||
system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
||||||
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
|
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
|
||||||
system.physmem.refreshEnergy::0 8598732480 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::0 8604835200 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.refreshEnergy::1 8598732480 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::1 8604835200 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.actBackEnergy::0 3574139400 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::0 3575888730 # Energy for active background per rank (pJ)
|
||||||
system.physmem.actBackEnergy::1 3578406705 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::1 3595740120 # Energy for active background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::0 75854895000 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::0 75909421500 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::1 75851151750 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::1 75892008000 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.totalEnergy::0 88048649250 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::0 88111101795 # Total energy per rank (pJ)
|
||||||
system.physmem.totalEnergy::1 88047908235 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::1 88112204505 # Total energy per rank (pJ)
|
||||||
system.physmem.averagePower::0 668.807689 # Core power per rank (mW)
|
system.physmem.averagePower::0 668.807404 # Core power per rank (mW)
|
||||||
system.physmem.averagePower::1 668.802060 # Core power per rank (mW)
|
system.physmem.averagePower::1 668.815774 # Core power per rank (mW)
|
||||||
system.membus.trans_dist::ReadReq 2779 # Transaction distribution
|
system.cpu.branchPred.lookups 49935043 # Number of BP lookups
|
||||||
system.membus.trans_dist::ReadResp 2779 # Transaction distribution
|
system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted
|
||||||
system.membus.trans_dist::ReadExReq 1090 # Transaction distribution
|
system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect
|
||||||
system.membus.trans_dist::ReadExResp 1090 # Transaction distribution
|
system.cpu.branchPred.BTBLookups 24405530 # Number of BTB lookups
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes)
|
system.cpu.branchPred.BTBHits 23309445 # Number of BTB hits
|
||||||
system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 3869 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 3869 # Request fanout histogram
|
|
||||||
system.membus.reqLayer0.occupancy 4528000 # Layer occupancy (ticks)
|
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.membus.respLayer1.occupancy 36225250 # Layer occupancy (ticks)
|
|
||||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
||||||
system.cpu.branchPred.lookups 49915423 # Number of BP lookups
|
|
||||||
system.cpu.branchPred.condPredicted 39661220 # Number of conditional branches predicted
|
|
||||||
system.cpu.branchPred.condIncorrect 5747038 # Number of conditional branches incorrect
|
|
||||||
system.cpu.branchPred.BTBLookups 24423675 # Number of BTB lookups
|
|
||||||
system.cpu.branchPred.BTBHits 23301282 # Number of BTB hits
|
|
||||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.branchPred.BTBHitPct 95.404488 # BTB Hit Percentage
|
system.cpu.branchPred.BTBHitPct 95.508866 # BTB Hit Percentage
|
||||||
system.cpu.branchPred.usedRAS 1905800 # Number of times the RAS was used to get a target.
|
system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions.
|
system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions.
|
||||||
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||||
|
|
@ -359,330 +336,91 @@ system.cpu.itb.hits 0 # DT
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||||
system.cpu.numCycles 263304939 # number of cpu cycles simulated
|
system.cpu.numCycles 263491900 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.committedInsts 172317809 # Number of instructions committed
|
system.cpu.committedInsts 172317809 # Number of instructions committed
|
||||||
system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed
|
system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed
|
||||||
system.cpu.discardedOps 11787313 # Number of ops (including micro ops) which were discarded before commit
|
system.cpu.discardedOps 11758002 # Number of ops (including micro ops) which were discarded before commit
|
||||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||||
system.cpu.cpi 1.528019 # CPI: cycles per instruction
|
system.cpu.cpi 1.529104 # CPI: cycles per instruction
|
||||||
system.cpu.ipc 0.654442 # IPC: instructions per cycle
|
system.cpu.ipc 0.653978 # IPC: instructions per cycle
|
||||||
system.cpu.tickCycles 255940225 # Number of cycles that the object actually ticked
|
system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked
|
||||||
system.cpu.idleCycles 7364714 # Total number of cycles that the object has spent stopped
|
system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped
|
||||||
system.cpu.icache.tags.replacements 2881 # number of replacements
|
|
||||||
system.cpu.icache.tags.tagsinuse 1424.983856 # Cycle average of tags in use
|
|
||||||
system.cpu.icache.tags.total_refs 71509873 # Total number of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.sampled_refs 4678 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.avg_refs 15286.420051 # Average number of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983856 # Average occupied blocks per requestor
|
|
||||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.695793 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.tags.occ_percent::total 0.695793 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 114 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.icache.tags.tag_accesses 143033782 # Number of tag accesses
|
|
||||||
system.cpu.icache.tags.data_accesses 143033782 # Number of data accesses
|
|
||||||
system.cpu.icache.ReadReq_hits::cpu.inst 71509873 # number of ReadReq hits
|
|
||||||
system.cpu.icache.ReadReq_hits::total 71509873 # number of ReadReq hits
|
|
||||||
system.cpu.icache.demand_hits::cpu.inst 71509873 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.demand_hits::total 71509873 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.overall_hits::cpu.inst 71509873 # number of overall hits
|
|
||||||
system.cpu.icache.overall_hits::total 71509873 # number of overall hits
|
|
||||||
system.cpu.icache.ReadReq_misses::cpu.inst 4679 # number of ReadReq misses
|
|
||||||
system.cpu.icache.ReadReq_misses::total 4679 # number of ReadReq misses
|
|
||||||
system.cpu.icache.demand_misses::cpu.inst 4679 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.demand_misses::total 4679 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.overall_misses::cpu.inst 4679 # number of overall misses
|
|
||||||
system.cpu.icache.overall_misses::total 4679 # number of overall misses
|
|
||||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 184816496 # number of ReadReq miss cycles
|
|
||||||
system.cpu.icache.ReadReq_miss_latency::total 184816496 # number of ReadReq miss cycles
|
|
||||||
system.cpu.icache.demand_miss_latency::cpu.inst 184816496 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.demand_miss_latency::total 184816496 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.overall_miss_latency::cpu.inst 184816496 # number of overall miss cycles
|
|
||||||
system.cpu.icache.overall_miss_latency::total 184816496 # number of overall miss cycles
|
|
||||||
system.cpu.icache.ReadReq_accesses::cpu.inst 71514552 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.icache.ReadReq_accesses::total 71514552 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.icache.demand_accesses::cpu.inst 71514552 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.demand_accesses::total 71514552 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.overall_accesses::cpu.inst 71514552 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.overall_accesses::total 71514552 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39499.144262 # average ReadReq miss latency
|
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::total 39499.144262 # average ReadReq miss latency
|
|
||||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency
|
|
||||||
system.cpu.icache.demand_avg_miss_latency::total 39499.144262 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_miss_latency::total 39499.144262 # average overall miss latency
|
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4679 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses::total 4679 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4679 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.demand_mshr_misses::total 4679 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4679 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_misses::total 4679 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174539504 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 174539504 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174539504 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency::total 174539504 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174539504 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency::total 174539504 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37302.736482 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37302.736482 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 5390 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9357 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3634 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count::total 12991 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 6504 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::5 6504 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 6504 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 3268000 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer0.occupancy 7477496 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer1.occupancy 2996735 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
||||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
||||||
system.cpu.l2cache.tags.tagsinuse 2001.642948 # Cycle average of tags in use
|
|
||||||
system.cpu.l2cache.tags.total_refs 2592 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.avg_refs 0.930032 # Average number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.028976 # Average occupied blocks per requestor
|
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613972 # Average occupied blocks per requestor
|
|
||||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060993 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_percent::total 0.061085 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.l2cache.tags.tag_accesses 55917 # Number of tag accesses
|
|
||||||
system.cpu.l2cache.tags.data_accesses 55917 # Number of data accesses
|
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2591 # number of ReadReq hits
|
|
||||||
system.cpu.l2cache.ReadReq_hits::total 2591 # number of ReadReq hits
|
|
||||||
system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
|
|
||||||
system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
|
|
||||||
system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits
|
|
||||||
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
|
|
||||||
system.cpu.l2cache.demand_hits::cpu.inst 2599 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_hits::total 2599 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.overall_hits::cpu.inst 2599 # number of overall hits
|
|
||||||
system.cpu.l2cache.overall_hits::total 2599 # number of overall hits
|
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2799 # number of ReadReq misses
|
|
||||||
system.cpu.l2cache.ReadReq_misses::total 2799 # number of ReadReq misses
|
|
||||||
system.cpu.l2cache.ReadExReq_misses::cpu.inst 1090 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.demand_misses::cpu.inst 3889 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_misses::total 3889 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.overall_misses::cpu.inst 3889 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_misses::total 3889 # number of overall misses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190706250 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::total 190706250 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75951500 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::total 75951500 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 266657750 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::total 266657750 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 266657750 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::total 266657750 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 5390 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::total 5390 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1098 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.demand_accesses::cpu.inst 6488 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_accesses::total 6488 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::cpu.inst 6488 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::total 6488 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.519295 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.519295 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992714 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.599414 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::total 0.599414 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.599414 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::total 0.599414 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68133.708467 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68133.708467 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69680.275229 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69680.275229 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::total 68567.176652 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::total 68567.176652 # average overall miss latency
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 19 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_hits::total 19 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2780 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1090 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3870 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3870 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154681250 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154681250 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62286000 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62286000 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216967250 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::total 216967250 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216967250 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::total 216967250 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515770 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515770 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.596486 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.596486 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55640.737410 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55640.737410 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57143.119266 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57143.119266 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.tags.replacements 42 # number of replacements
|
system.cpu.dcache.tags.replacements 42 # number of replacements
|
||||||
system.cpu.dcache.tags.tagsinuse 1376.810186 # Cycle average of tags in use
|
system.cpu.dcache.tags.tagsinuse 1377.772721 # Cycle average of tags in use
|
||||||
system.cpu.dcache.tags.total_refs 40745471 # Total number of references to valid blocks.
|
system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.sampled_refs 1809 # Sample count of references to valid blocks.
|
system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.tags.avg_refs 22523.754008 # Average number of references to valid blocks.
|
system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810186 # Average occupied blocks per requestor
|
system.cpu.dcache.tags.occ_blocks::cpu.inst 1377.772721 # Average occupied blocks per requestor
|
||||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.336135 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::cpu.inst 0.336370 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.tags.occ_percent::total 0.336135 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1767 # Occupied blocks per task id
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1357 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431396 # Percentage of cache occupancy per task id
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id
|
||||||
system.cpu.dcache.tags.tag_accesses 81497573 # Number of tag accesses
|
system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses
|
||||||
system.cpu.dcache.tags.data_accesses 81497573 # Number of data accesses
|
system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses
|
||||||
system.cpu.dcache.ReadReq_hits::cpu.inst 28338014 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::cpu.inst 28355530 # number of ReadReq hits
|
||||||
system.cpu.dcache.ReadReq_hits::total 28338014 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::cpu.inst 12362643 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::cpu.inst 12362643 # number of WriteReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.demand_hits::cpu.inst 40700657 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::cpu.inst 40718173 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.demand_hits::total 40700657 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits::cpu.inst 40700657 # number of overall hits
|
system.cpu.dcache.overall_hits::cpu.inst 40718173 # number of overall hits
|
||||||
system.cpu.dcache.overall_hits::total 40700657 # number of overall hits
|
system.cpu.dcache.overall_hits::total 40718173 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses::cpu.inst 767 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::cpu.inst 792 # number of ReadReq misses
|
||||||
system.cpu.dcache.ReadReq_misses::total 767 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses::cpu.inst 1644 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses::cpu.inst 1644 # number of WriteReq misses
|
||||||
system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses
|
||||||
system.cpu.dcache.demand_misses::cpu.inst 2411 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses::cpu.inst 2436 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.demand_misses::total 2411 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses::cpu.inst 2411 # number of overall misses
|
system.cpu.dcache.overall_misses::cpu.inst 2436 # number of overall misses
|
||||||
system.cpu.dcache.overall_misses::total 2411 # number of overall misses
|
system.cpu.dcache.overall_misses::total 2436 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 52005983 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 54011984 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_latency::total 52005983 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115743750 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115580250 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::total 115743750 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::total 115580250 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::cpu.inst 167749733 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::cpu.inst 169592234 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::total 167749733 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::total 169592234 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::cpu.inst 167749733 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::cpu.inst 169592234 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::total 167749733 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::total 169592234 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 28338781 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::cpu.inst 28356322 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_accesses::total 28338781 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 22407 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 22407 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 22407 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 22407 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses::cpu.inst 40703068 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::cpu.inst 40720609 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.demand_accesses::total 40703068 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::cpu.inst 40703068 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::cpu.inst 40720609 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::total 40703068 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::total 40720609 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate::cpu.inst 0.000059 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate::cpu.inst 0.000060 # miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000059 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000060 # miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 67804.410691 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68196.949495 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 67804.410691 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70403.740876 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70304.288321 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 70403.740876 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 70304.288321 # average WriteReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69619.143678 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::total 69576.828287 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::total 69619.143678 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69619.143678 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::total 69576.828287 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::total 69619.143678 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -693,30 +431,30 @@ system.cpu.dcache.fast_writes 0 # nu
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
|
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
|
||||||
system.cpu.dcache.writebacks::total 16 # number of writebacks
|
system.cpu.dcache.writebacks::total 16 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 546 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 546 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits::cpu.inst 602 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits::cpu.inst 626 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits::total 602 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits::cpu.inst 602 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits::cpu.inst 626 # number of overall MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits::total 602 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits::total 626 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 711 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 712 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses::total 712 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1098 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1098 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::cpu.inst 1810 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.inst 1810 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 1809 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47475265 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47293264 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 47475265 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77131500 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76493500 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 77131500 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 76493500 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124606765 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 123786764 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::total 124606765 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::total 123786764 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124606765 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 123786764 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::total 124606765 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::total 123786764 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses
|
||||||
|
|
@ -725,14 +463,276 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000044
|
||||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66772.524613 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66423.123596 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66772.524613 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70247.267760 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69666.211293 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70247.267760 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69666.211293 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68390.477348 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68390.477348 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68390.477348 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68390.477348 # average overall mshr miss latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.tags.replacements 2909 # number of replacements
|
||||||
|
system.cpu.icache.tags.tagsinuse 1424.880839 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880839 # Average occupied blocks per requestor
|
||||||
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.icache.tags.tag_accesses 143242775 # Number of tag accesses
|
||||||
|
system.cpu.icache.tags.data_accesses 143242775 # Number of data accesses
|
||||||
|
system.cpu.icache.ReadReq_hits::cpu.inst 71614329 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_hits::total 71614329 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits::cpu.inst 71614329 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_hits::total 71614329 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits::cpu.inst 71614329 # number of overall hits
|
||||||
|
system.cpu.icache.overall_hits::total 71614329 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses::cpu.inst 4706 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_misses::total 4706 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses::cpu.inst 4706 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses
|
||||||
|
system.cpu.icache.overall_misses::total 4706 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 186392247 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.ReadReq_miss_latency::total 186392247 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency::cpu.inst 186392247 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency::total 186392247 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency::cpu.inst 186392247 # number of overall miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency::total 186392247 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_accesses::total 71619035 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::cpu.inst 71619035 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::total 71619035 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39607.362303 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency::total 39607.362303 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 39607.362303 # average overall miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency::total 39607.362303 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 39607.362303 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency::total 39607.362303 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4706 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses::total 4706 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses::cpu.inst 4706 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses::total 4706 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses::cpu.inst 4706 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses::total 4706 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176061753 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 176061753 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176061753 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency::total 176061753 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176061753 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency::total 176061753 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37412.187208 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37412.187208 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37412.187208 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 37412.187208 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37412.187208 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 37412.187208 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.tags.tagsinuse 2001.520468 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.tags.total_refs 2624 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.491284 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060989 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.l2cache.tags.tag_accesses 56139 # Number of tag accesses
|
||||||
|
system.cpu.l2cache.tags.data_accesses 56139 # Number of data accesses
|
||||||
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2623 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_hits::total 2623 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits::cpu.inst 2631 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_hits::total 2631 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits::cpu.inst 2631 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_hits::total 2631 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2795 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_misses::total 2795 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::cpu.inst 1090 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses::cpu.inst 3885 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses::cpu.inst 3885 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_misses::total 3885 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191698500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::total 191698500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75314000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::total 75314000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 267012500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::total 267012500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 267012500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::total 267012500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 5418 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1098 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses::cpu.inst 6516 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_accesses::total 6516 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::cpu.inst 6516 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::total 6516 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.515873 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.515873 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992714 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.596225 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.596225 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68586.225403 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68586.225403 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.412844 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.412844 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::total 68729.086229 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::total 68729.086229 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2778 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::total 2778 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1090 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3868 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3868 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155803750 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155803750 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 61486500 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61486500 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217290250 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::total 217290250 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217290250 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::total 217290250 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512735 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56084.863211 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56084.863211 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56409.633028 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56409.633028 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9411 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count::total 13047 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301120 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size::total 417984 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::samples 6532 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::5 6532 100.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.cpu.toL2Bus.respLayer0.occupancy 7517747 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.membus.trans_dist::ReadReq 2777 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadResp 2777 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadExReq 1090 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadExResp 1090 # Transaction distribution
|
||||||
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7734 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count::total 7734 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247488 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size::total 247488 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
|
system.membus.snoop_fanout::samples 3867 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::0 3867 100.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::total 3867 # Request fanout histogram
|
||||||
|
system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks)
|
||||||
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
system.membus.respLayer1.occupancy 36361250 # Layer occupancy (ticks)
|
||||||
|
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,146 +1,51 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 1.829332 # Number of seconds simulated
|
sim_seconds 1.829332 # Number of seconds simulated
|
||||||
sim_ticks 1829331993500 # Number of ticks simulated
|
sim_ticks 1829332273500 # Number of ticks simulated
|
||||||
final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 2920462 # Simulator instruction rate (inst/s)
|
host_inst_rate 1690642 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 2920460 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1690641 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 88984410684 # Simulator tick rate (ticks/s)
|
host_tick_rate 51512796649 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 366200 # Number of bytes of host memory used
|
host_mem_usage 313048 # Number of bytes of host memory used
|
||||||
host_seconds 20.56 # Real time elapsed on the host
|
host_seconds 35.51 # Real time elapsed on the host
|
||||||
sim_insts 60038469 # Number of instructions simulated
|
sim_insts 60038341 # Number of instructions simulated
|
||||||
sim_ops 60038469 # Number of ops (including micro ops) simulated
|
sim_ops 60038341 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
system.clk_domain.clock 1000 # Clock period in ticks
|
system.clk_domain.clock 1000 # Clock period in ticks
|
||||||
system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu.data 66856000 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.data 66839040 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::total 67714944 # Number of bytes read from this memory
|
system.physmem.bytes_read::total 67697984 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written::writebacks 4753856 # Number of bytes written to this memory
|
system.physmem.bytes_written::writebacks 7411008 # Number of bytes written to this memory
|
||||||
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
|
system.physmem.bytes_written::total 7411008 # Number of bytes written to this memory
|
||||||
system.physmem.bytes_written::total 7413184 # Number of bytes written to this memory
|
|
||||||
system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu.data 1044625 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.data 1044360 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
|
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::total 1058046 # Number of read requests responded to by this memory
|
system.physmem.num_reads::total 1057781 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes::writebacks 74279 # Number of write requests responded to by this memory
|
system.physmem.num_writes::writebacks 115797 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
|
system.physmem.num_writes::total 115797 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_writes::total 115831 # Number of write requests responded to by this memory
|
|
||||||
system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu.data 36546674 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.data 36537397 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::total 37016214 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::total 37006937 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write::writebacks 2598684 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write::writebacks 4051209 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write::total 4051209 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write::total 4052399 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_total::writebacks 4051209 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::writebacks 2598684 # Total bandwidth to/from this memory (bytes/s)
|
|
||||||
system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.data 36546674 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.data 36537397 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 41068613 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 41058146 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.membus.trans_dist::ReadReq 948404 # Transaction distribution
|
|
||||||
system.membus.trans_dist::ReadResp 948404 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteReq 9838 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteResp 9838 # Transaction distribution
|
|
||||||
system.membus.trans_dist::Writeback 74279 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
|
|
||||||
system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
|
|
||||||
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
|
|
||||||
system.membus.trans_dist::ReadExReq 116985 # Transaction distribution
|
|
||||||
system.membus.trans_dist::ReadExResp 116985 # Transaction distribution
|
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190605 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224649 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83452 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.iocache.mem_side::total 83452 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count::total 2308101 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72467840 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513966 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670464 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 2670464 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 75184430 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 1174168 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 1174168 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 1174168 # Request fanout histogram
|
|
||||||
system.iocache.tags.replacements 41686 # number of replacements
|
|
||||||
system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use
|
|
||||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
||||||
system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
|
|
||||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
||||||
system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit.
|
|
||||||
system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor
|
|
||||||
system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
|
|
||||||
system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
|
|
||||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
||||||
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
||||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
||||||
system.iocache.tags.tag_accesses 375534 # Number of tag accesses
|
|
||||||
system.iocache.tags.data_accesses 375534 # Number of data accesses
|
|
||||||
system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
|
|
||||||
system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
|
|
||||||
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
|
|
||||||
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
|
|
||||||
system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses
|
|
||||||
system.iocache.demand_misses::total 174 # number of demand (read+write) misses
|
|
||||||
system.iocache.overall_misses::tsunami.ide 174 # number of overall misses
|
|
||||||
system.iocache.overall_misses::total 174 # number of overall misses
|
|
||||||
system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
|
|
||||||
system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
|
|
||||||
system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses
|
|
||||||
system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses
|
|
||||||
system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses
|
|
||||||
system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses
|
|
||||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
||||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
||||||
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
||||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
||||||
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
||||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
||||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.iocache.fast_writes 41552 # number of fast writes performed
|
|
||||||
system.iocache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
||||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
||||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
||||||
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
||||||
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
||||||
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
||||||
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
||||||
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
||||||
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
||||||
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
||||||
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
||||||
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 9710423 # DTB read hits
|
system.cpu.dtb.read_hits 9710422 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 10329 # DTB read misses
|
system.cpu.dtb.read_misses 10329 # DTB read misses
|
||||||
system.cpu.dtb.read_acv 210 # DTB read access violations
|
system.cpu.dtb.read_acv 210 # DTB read access violations
|
||||||
system.cpu.dtb.read_accesses 728856 # DTB read accesses
|
system.cpu.dtb.read_accesses 728856 # DTB read accesses
|
||||||
|
|
@ -148,14 +53,14 @@ system.cpu.dtb.write_hits 6352496 # DT
|
||||||
system.cpu.dtb.write_misses 1142 # DTB write misses
|
system.cpu.dtb.write_misses 1142 # DTB write misses
|
||||||
system.cpu.dtb.write_acv 157 # DTB write access violations
|
system.cpu.dtb.write_acv 157 # DTB write access violations
|
||||||
system.cpu.dtb.write_accesses 291931 # DTB write accesses
|
system.cpu.dtb.write_accesses 291931 # DTB write accesses
|
||||||
system.cpu.dtb.data_hits 16062919 # DTB hits
|
system.cpu.dtb.data_hits 16062918 # DTB hits
|
||||||
system.cpu.dtb.data_misses 11471 # DTB misses
|
system.cpu.dtb.data_misses 11471 # DTB misses
|
||||||
system.cpu.dtb.data_acv 367 # DTB access violations
|
system.cpu.dtb.data_acv 367 # DTB access violations
|
||||||
system.cpu.dtb.data_accesses 1020787 # DTB accesses
|
system.cpu.dtb.data_accesses 1020787 # DTB accesses
|
||||||
system.cpu.itb.fetch_hits 4974637 # ITB hits
|
system.cpu.itb.fetch_hits 4974648 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 5006 # ITB misses
|
system.cpu.itb.fetch_misses 5006 # ITB misses
|
||||||
system.cpu.itb.fetch_acv 184 # ITB acv
|
system.cpu.itb.fetch_acv 184 # ITB acv
|
||||||
system.cpu.itb.fetch_accesses 4979643 # ITB accesses
|
system.cpu.itb.fetch_accesses 4979654 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
|
|
@ -168,31 +73,31 @@ system.cpu.itb.data_hits 0 # DT
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
system.cpu.numCycles 3658670345 # number of cpu cycles simulated
|
system.cpu.numCycles 3658670905 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.committedInsts 60038469 # Number of instructions committed
|
system.cpu.committedInsts 60038341 # Number of instructions committed
|
||||||
system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed
|
system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed
|
||||||
system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses
|
system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses
|
||||||
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
|
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
|
||||||
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
|
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
|
||||||
system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls
|
system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls
|
||||||
system.cpu.num_int_insts 55913692 # number of integer instructions
|
system.cpu.num_int_insts 55913563 # number of integer instructions
|
||||||
system.cpu.num_fp_insts 324460 # number of float instructions
|
system.cpu.num_fp_insts 324460 # number of float instructions
|
||||||
system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read
|
system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read
|
||||||
system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written
|
system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written
|
||||||
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
|
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
|
||||||
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
|
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
|
||||||
system.cpu.num_mem_refs 16115703 # number of memory refs
|
system.cpu.num_mem_refs 16115702 # number of memory refs
|
||||||
system.cpu.num_load_insts 9747509 # Number of load instructions
|
system.cpu.num_load_insts 9747508 # Number of load instructions
|
||||||
system.cpu.num_store_insts 6368194 # Number of store instructions
|
system.cpu.num_store_insts 6368194 # Number of store instructions
|
||||||
system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles
|
system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles
|
||||||
system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles
|
system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles
|
||||||
system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
|
||||||
system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
|
system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
|
||||||
system.cpu.Branches 9064428 # Number of branches fetched
|
system.cpu.Branches 9064400 # Number of branches fetched
|
||||||
system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction
|
system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction
|
||||||
system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction
|
system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction
|
||||||
system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
|
system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
|
||||||
system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
|
system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
|
||||||
system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
|
system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
|
||||||
|
|
@ -221,34 +126,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl
|
||||||
system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
|
system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
|
||||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||||
system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction
|
system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction
|
||||||
system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction
|
system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction
|
||||||
system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
|
system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::total 60050307 # Class of executed instruction
|
system.cpu.op_class::total 60050179 # Class of executed instruction
|
||||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||||
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
|
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
|
||||||
system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed
|
system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
|
||||||
system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
|
system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
|
||||||
system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
|
system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
|
||||||
system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
|
system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
|
||||||
system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl
|
system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl
|
||||||
system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl
|
system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl
|
||||||
system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
|
system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
|
||||||
system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
|
system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
|
||||||
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
|
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
|
||||||
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
||||||
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
|
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
|
||||||
system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl
|
system.cpu.kern.ipl_ticks::0 1811929473000 99.05% 99.05% # number of cycles we spent at this ipl
|
||||||
system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
|
system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||||
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
|
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||||
system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl
|
system.cpu.kern.ipl_ticks::31 17302245000 0.95% 100.00% # number of cycles we spent at this ipl
|
||||||
system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl
|
system.cpu.kern.ipl_ticks::total 1829332066000 # number of cycles we spent at this ipl
|
||||||
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
|
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
|
||||||
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||||
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||||
system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl
|
system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl
|
||||||
system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl
|
system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl
|
||||||
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
||||||
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
||||||
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
||||||
|
|
@ -287,7 +192,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu
|
||||||
system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
|
system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
|
||||||
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
||||||
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
||||||
system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed
|
system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed
|
||||||
system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
|
system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
|
||||||
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
|
||||||
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
|
||||||
|
|
@ -296,52 +201,269 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu
|
||||||
system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
|
system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
|
||||||
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
||||||
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
||||||
system.cpu.kern.callpal::total 192179 # number of callpals executed
|
system.cpu.kern.callpal::total 192180 # number of callpals executed
|
||||||
system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
|
system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
|
||||||
system.cpu.kern.mode_switch::user 1737 # number of protection mode switches
|
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
|
||||||
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
|
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
|
||||||
system.cpu.kern.mode_good::kernel 1908
|
system.cpu.kern.mode_good::kernel 1909
|
||||||
system.cpu.kern.mode_good::user 1737
|
system.cpu.kern.mode_good::user 1738
|
||||||
system.cpu.kern.mode_good::idle 171
|
system.cpu.kern.mode_good::idle 171
|
||||||
system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches
|
system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches
|
||||||
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||||
system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
|
system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
|
||||||
system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches
|
system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches
|
||||||
system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode
|
system.cpu.kern.mode_ticks::kernel 26833319500 1.47% 1.47% # number of ticks spent at the given mode
|
||||||
system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
|
system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
|
||||||
system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode
|
system.cpu.kern.mode_ticks::idle 1801033671500 98.45% 100.00% # number of ticks spent at the given mode
|
||||||
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
||||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
system.cpu.dcache.tags.replacements 2042728 # number of replacements
|
||||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
|
||||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
system.cpu.dcache.tags.total_refs 14038398 # Total number of references to valid blocks.
|
||||||
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
system.cpu.dcache.tags.sampled_refs 2043240 # Sample count of references to valid blocks.
|
||||||
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
system.cpu.dcache.tags.avg_refs 6.870655 # Average number of references to valid blocks.
|
||||||
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||||
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
|
||||||
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
|
||||||
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
||||||
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||||
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id
|
||||||
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
|
||||||
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
||||||
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||||
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
system.cpu.dcache.tags.tag_accesses 66369797 # Number of tag accesses
|
||||||
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
system.cpu.dcache.tags.data_accesses 66369797 # Number of data accesses
|
||||||
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
system.cpu.dcache.ReadReq_hits::cpu.data 7807758 # number of ReadReq hits
|
||||||
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
system.cpu.dcache.ReadReq_hits::total 7807758 # number of ReadReq hits
|
||||||
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
system.cpu.dcache.WriteReq_hits::cpu.data 5848202 # number of WriteReq hits
|
||||||
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
system.cpu.dcache.WriteReq_hits::total 5848202 # number of WriteReq hits
|
||||||
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
|
||||||
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
|
||||||
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
|
||||||
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
|
||||||
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
system.cpu.dcache.demand_hits::cpu.data 13655960 # number of demand (read+write) hits
|
||||||
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
system.cpu.dcache.demand_hits::total 13655960 # number of demand (read+write) hits
|
||||||
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
system.cpu.dcache.overall_hits::cpu.data 13655960 # number of overall hits
|
||||||
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
system.cpu.dcache.overall_hits::total 13655960 # number of overall hits
|
||||||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
system.cpu.dcache.ReadReq_misses::cpu.data 1721724 # number of ReadReq misses
|
||||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
system.cpu.dcache.ReadReq_misses::total 1721724 # number of ReadReq misses
|
||||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17163 # number of LoadLockedReq misses
|
||||||
|
system.cpu.dcache.LoadLockedReq_misses::total 17163 # number of LoadLockedReq misses
|
||||||
|
system.cpu.dcache.demand_misses::cpu.data 2026094 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.demand_misses::total 2026094 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses::cpu.data 2026094 # number of overall misses
|
||||||
|
system.cpu.dcache.overall_misses::total 2026094 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_accesses::cpu.data 9529482 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.ReadReq_accesses::total 9529482 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses::cpu.data 15682054 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.demand_accesses::total 15682054 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses::cpu.data 15682054 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses::total 15682054 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180673 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate::total 0.180673 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085685 # miss rate for LoadLockedReq accesses
|
||||||
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085685 # miss rate for LoadLockedReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.129198 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate::total 0.129198 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.129198 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate::total 0.129198 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks::writebacks 833501 # number of writebacks
|
||||||
|
system.cpu.dcache.writebacks::total 833501 # number of writebacks
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.tags.replacements 919605 # number of replacements
|
||||||
|
system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.tags.total_refs 59129947 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.avg_refs 64.263509 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.tags.occ_blocks::cpu.inst 511.215260 # Average occupied blocks per requestor
|
||||||
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.icache.tags.tag_accesses 60970411 # Number of tag accesses
|
||||||
|
system.cpu.icache.tags.data_accesses 60970411 # Number of data accesses
|
||||||
|
system.cpu.icache.ReadReq_hits::cpu.inst 59129947 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_hits::total 59129947 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits::cpu.inst 59129947 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_hits::total 59129947 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits::cpu.inst 59129947 # number of overall hits
|
||||||
|
system.cpu.icache.overall_hits::total 59129947 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses
|
||||||
|
system.cpu.icache.overall_misses::total 920232 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_accesses::cpu.inst 60050179 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_accesses::total 60050179 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses::cpu.inst 60050179 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_accesses::total 60050179 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::cpu.inst 60050179 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::total 60050179 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.tags.replacements 992295 # number of replacements
|
||||||
|
system.cpu.l2cache.tags.tagsinuse 65424.374284 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.tags.total_refs 2433284 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.avg_refs 2.301069 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::writebacks 56310.352234 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.099732 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922318 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3055 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54043 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.l2cache.tags.tag_accesses 31737815 # Number of tag accesses
|
||||||
|
system.cpu.l2cache.tags.data_accesses 31737815 # Number of data accesses
|
||||||
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 906808 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_hits::cpu.data 811247 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_hits::total 1718055 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits::writebacks 833501 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.Writeback_hits::total 833501 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
||||||
|
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 187243 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits::total 187243 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits::cpu.inst 906808 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_hits::cpu.data 998490 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_hits::total 1905298 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits::cpu.inst 906808 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_hits::cpu.data 998490 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_hits::total 1905298 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 920214 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1738887 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::total 2659101 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses::writebacks 833501 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses::total 833501 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::total 304354 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_accesses::cpu.data 2043241 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_accesses::total 2963455 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::cpu.data 2043241 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::total 2963455 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533468 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.353896 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384785 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384785 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511320 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511320 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks
|
||||||
|
system.cpu.l2cache.writebacks::total 74285 # number of writebacks
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadReq 2666303 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::Writeback 833501 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840464 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954059 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count::total 6794523 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157614 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size::total 243052462 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.snoops 41883 # Total snoops (count)
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::samples 3838716 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.103690 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::1 3796990 98.91% 98.91% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::total 3838716 # Request fanout histogram
|
||||||
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||||
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||||
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||||
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
||||||
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
||||||
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
||||||
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||||
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||||
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||||
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||||
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
||||||
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
||||||
system.iobus.trans_dist::ReadReq 7358 # Transaction distribution
|
system.iobus.trans_dist::ReadReq 7358 # Transaction distribution
|
||||||
system.iobus.trans_dist::ReadResp 7358 # Transaction distribution
|
system.iobus.trans_dist::ReadResp 7358 # Transaction distribution
|
||||||
system.iobus.trans_dist::WriteReq 51390 # Transaction distribution
|
system.iobus.trans_dist::WriteReq 51390 # Transaction distribution
|
||||||
|
|
@ -379,241 +501,120 @@ system.iobus.pkt_size_system.bridge.master::total 46126
|
||||||
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes)
|
system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.icache.tags.replacements 919603 # number of replacements
|
system.iocache.tags.replacements 41686 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use
|
system.iocache.tags.tagsinuse 1.225572 # Cycle average of tags in use
|
||||||
system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks.
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks.
|
system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks.
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit.
|
system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor
|
system.iocache.tags.occ_blocks::tsunami.ide 1.225572 # Average occupied blocks per requestor
|
||||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
|
system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
|
system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id
|
system.iocache.tags.tag_accesses 375534 # Number of tag accesses
|
||||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
system.iocache.tags.data_accesses 375534 # Number of data accesses
|
||||||
system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses
|
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
|
||||||
system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses
|
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
|
||||||
system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits
|
system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
|
||||||
system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits
|
system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
|
||||||
system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits
|
system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses
|
||||||
system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits
|
system.iocache.demand_misses::total 174 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits
|
system.iocache.overall_misses::tsunami.ide 174 # number of overall misses
|
||||||
system.cpu.icache.overall_hits::total 59130077 # number of overall hits
|
system.iocache.overall_misses::total 174 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses
|
system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses
|
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses
|
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses
|
system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
|
||||||
system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses
|
system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_misses::total 920230 # number of overall misses
|
system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses)
|
system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses)
|
system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses
|
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
|
||||||
system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
||||||
system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
system.iocache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
system.iocache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.iocache.writebacks::total 41512 # number of writebacks
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.tags.replacements 992289 # number of replacements
|
system.membus.trans_dist::ReadReq 948404 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.tagsinuse 65424.374569 # Cycle average of tags in use
|
system.membus.trans_dist::ReadResp 948404 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.total_refs 2433258 # Total number of references to valid blocks.
|
system.membus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.sampled_refs 1057452 # Sample count of references to valid blocks.
|
system.membus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.avg_refs 2.301058 # Average number of references to valid blocks.
|
system.membus.trans_dist::Writeback 115797 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56310.337833 # Average occupied blocks per requestor
|
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.106258 # Average occupied blocks per requestor
|
system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930478 # Average occupied blocks per requestor
|
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy
|
system.membus.trans_dist::ReadExReq 116991 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy
|
system.membus.trans_dist::ReadExResp 116991 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190623 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224667 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124964 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id
|
system.membus.pkt_count_system.iocache.mem_side::total 124964 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id
|
system.membus.pkt_count::total 2349631 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72468608 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72514734 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.tag_accesses 31737481 # Number of tag accesses
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5327232 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.data_accesses 31737481 # Number of data accesses
|
system.membus.pkt_size_system.iocache.mem_side::total 5327232 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 906806 # number of ReadReq hits
|
system.membus.pkt_size::total 77841966 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.data 811234 # number of ReadReq hits
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.l2cache.ReadReq_hits::total 1718040 # number of ReadReq hits
|
system.membus.snoop_fanout::samples 1215692 # Request fanout histogram
|
||||||
system.cpu.l2cache.Writeback_hits::writebacks 833484 # number of Writeback hits
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.l2cache.Writeback_hits::total 833484 # number of Writeback hits
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187241 # number of ReadExReq hits
|
system.membus.snoop_fanout::1 1215692 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.l2cache.ReadExReq_hits::total 187241 # number of ReadExReq hits
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.l2cache.demand_hits::cpu.inst 906806 # number of demand (read+write) hits
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.l2cache.demand_hits::cpu.data 998475 # number of demand (read+write) hits
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.l2cache.demand_hits::total 1905281 # number of demand (read+write) hits
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.l2cache.overall_hits::cpu.inst 906806 # number of overall hits
|
system.membus.snoop_fanout::total 1215692 # Request fanout histogram
|
||||||
system.cpu.l2cache.overall_hits::cpu.data 998475 # number of overall hits
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||||
system.cpu.l2cache.overall_hits::total 1905281 # number of overall hits
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||||
system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
||||||
system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117105 # number of ReadExReq misses
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||||
system.cpu.l2cache.ReadExReq_misses::total 117105 # number of ReadExReq misses
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
||||||
system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||||
system.cpu.l2cache.demand_misses::cpu.data 1044745 # number of demand (read+write) misses
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||||
system.cpu.l2cache.demand_misses::total 1058151 # number of demand (read+write) misses
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
||||||
system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||||
system.cpu.l2cache.overall_misses::cpu.data 1044745 # number of overall misses
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||||||
system.cpu.l2cache.overall_misses::total 1058151 # number of overall misses
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 920212 # number of ReadReq accesses(hits+misses)
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1738874 # number of ReadReq accesses(hits+misses)
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||||
system.cpu.l2cache.ReadReq_accesses::total 2659086 # number of ReadReq accesses(hits+misses)
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
||||||
system.cpu.l2cache.Writeback_accesses::writebacks 833484 # number of Writeback accesses(hits+misses)
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||||
system.cpu.l2cache.Writeback_accesses::total 833484 # number of Writeback accesses(hits+misses)
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
||||||
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||||
system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
||||||
system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||||
system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||||
system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
||||||
system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||||
system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||||
system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
|
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384776 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384776 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511323 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511323 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.writebacks::writebacks 74279 # number of writebacks
|
|
||||||
system.cpu.l2cache.writebacks::total 74279 # number of writebacks
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.tags.replacements 2042707 # number of replacements
|
|
||||||
system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
|
|
||||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id
|
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
|
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
|
||||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses
|
|
||||||
system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses
|
|
||||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits
|
|
||||||
system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits
|
|
||||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
|
|
||||||
system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
|
|
||||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
|
|
||||||
system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
|
|
||||||
system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_hits::total 13655981 # number of overall hits
|
|
||||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
|
|
||||||
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
|
|
||||||
system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
|
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
|
|
||||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
|
|
||||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.writebacks::writebacks 833484 # number of writebacks
|
|
||||||
system.cpu.dcache.writebacks::total 833484 # number of writebacks
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 2666288 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::Writeback 833484 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840460 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954000 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count::total 6794460 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894720 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184155182 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size::total 243049902 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.snoops 41883 # Total snoops (count)
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 3838676 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.103691 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 3796950 98.91% 98.91% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 3838676 # Request fanout histogram
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,59 +1,56 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 2.783854 # Number of seconds simulated
|
sim_seconds 2.783867 # Number of seconds simulated
|
||||||
sim_ticks 2783854461500 # Number of ticks simulated
|
sim_ticks 2783867165000 # Number of ticks simulated
|
||||||
final_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1414038 # Simulator instruction rate (inst/s)
|
host_inst_rate 1064003 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1721363 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1295252 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 27571822204 # Simulator tick rate (ticks/s)
|
host_tick_rate 20746494205 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 560116 # Number of bytes of host memory used
|
host_mem_usage 558936 # Number of bytes of host memory used
|
||||||
host_seconds 100.97 # Real time elapsed on the host
|
host_seconds 134.19 # Real time elapsed on the host
|
||||||
sim_insts 142771592 # Number of instructions simulated
|
sim_insts 142773109 # Number of instructions simulated
|
||||||
sim_ops 173801445 # Number of ops (including micro ops) simulated
|
sim_ops 173803334 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
system.clk_domain.clock 1000 # Clock period in ticks
|
system.clk_domain.clock 1000 # Clock period in ticks
|
||||||
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu.inst 1210980 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu.data 10345892 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory
|
system.physmem.bytes_read::total 11540680 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::cpu.inst 1210852 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory
|
system.physmem.bytes_written::writebacks 8837632 # Number of bytes written to this memory
|
||||||
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
|
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
|
||||||
system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
|
system.physmem.bytes_written::total 8855156 # Number of bytes written to this memory
|
||||||
system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory
|
|
||||||
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.inst 27373 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory
|
system.physmem.num_reads::total 189296 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory
|
system.physmem.num_writes::writebacks 138088 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
|
system.physmem.num_writes::total 142469 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory
|
|
||||||
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.inst 434953 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::total 4145557 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu.inst 434953 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write::writebacks 3174588 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write::total 3180883 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write::total 3181702 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_total::writebacks 3174588 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s)
|
|
||||||
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 434953 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 7333646 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 7326440 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||||
|
|
@ -96,9 +93,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT
|
||||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dtb.read_hits 31525959 # DTB read hits
|
system.cpu.dtb.read_hits 31526301 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 8580 # DTB read misses
|
system.cpu.dtb.read_misses 8581 # DTB read misses
|
||||||
system.cpu.dtb.write_hits 23124081 # DTB write hits
|
system.cpu.dtb.write_hits 23124463 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 1448 # DTB write misses
|
system.cpu.dtb.write_misses 1448 # DTB write misses
|
||||||
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
|
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
|
||||||
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||||
|
|
@ -109,12 +106,12 @@ system.cpu.dtb.align_faults 0 # Nu
|
||||||
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
|
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
|
||||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||||
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
|
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
|
||||||
system.cpu.dtb.read_accesses 31534539 # DTB read accesses
|
system.cpu.dtb.read_accesses 31534882 # DTB read accesses
|
||||||
system.cpu.dtb.write_accesses 23125529 # DTB write accesses
|
system.cpu.dtb.write_accesses 23125911 # DTB write accesses
|
||||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||||
system.cpu.dtb.hits 54650040 # DTB hits
|
system.cpu.dtb.hits 54650764 # DTB hits
|
||||||
system.cpu.dtb.misses 10028 # DTB misses
|
system.cpu.dtb.misses 10029 # DTB misses
|
||||||
system.cpu.dtb.accesses 54660068 # DTB accesses
|
system.cpu.dtb.accesses 54660793 # DTB accesses
|
||||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||||
|
|
@ -136,7 +133,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
||||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||||
system.cpu.itb.inst_hits 147038107 # ITB inst hits
|
system.cpu.itb.inst_hits 147039592 # ITB inst hits
|
||||||
system.cpu.itb.inst_misses 4762 # ITB inst misses
|
system.cpu.itb.inst_misses 4762 # ITB inst misses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
|
|
@ -153,38 +150,38 @@ system.cpu.itb.domain_faults 0 # Nu
|
||||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
system.cpu.itb.inst_accesses 147042869 # ITB inst accesses
|
system.cpu.itb.inst_accesses 147044354 # ITB inst accesses
|
||||||
system.cpu.itb.hits 147038107 # DTB hits
|
system.cpu.itb.hits 147039592 # DTB hits
|
||||||
system.cpu.itb.misses 4762 # DTB misses
|
system.cpu.itb.misses 4762 # DTB misses
|
||||||
system.cpu.itb.accesses 147042869 # DTB accesses
|
system.cpu.itb.accesses 147044354 # DTB accesses
|
||||||
system.cpu.numCycles 5567712004 # number of cpu cycles simulated
|
system.cpu.numCycles 5567737414 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.committedInsts 142771592 # Number of instructions committed
|
system.cpu.committedInsts 142773109 # Number of instructions committed
|
||||||
system.cpu.committedOps 173801445 # Number of ops (including micro ops) committed
|
system.cpu.committedOps 173803334 # Number of ops (including micro ops) committed
|
||||||
system.cpu.num_int_alu_accesses 153161099 # Number of integer alu accesses
|
system.cpu.num_int_alu_accesses 153162826 # Number of integer alu accesses
|
||||||
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
|
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
|
||||||
system.cpu.num_func_calls 16873874 # number of times a function call or return occured
|
system.cpu.num_func_calls 16873879 # number of times a function call or return occured
|
||||||
system.cpu.num_conditional_control_insts 18730301 # number of instructions that are conditional controls
|
system.cpu.num_conditional_control_insts 18730390 # number of instructions that are conditional controls
|
||||||
system.cpu.num_int_insts 153161099 # number of integer instructions
|
system.cpu.num_int_insts 153162826 # number of integer instructions
|
||||||
system.cpu.num_fp_insts 11484 # number of float instructions
|
system.cpu.num_fp_insts 11484 # number of float instructions
|
||||||
system.cpu.num_int_register_reads 285057250 # number of times the integer registers were read
|
system.cpu.num_int_register_reads 285060124 # number of times the integer registers were read
|
||||||
system.cpu.num_int_register_writes 107178308 # number of times the integer registers were written
|
system.cpu.num_int_register_writes 107179564 # number of times the integer registers were written
|
||||||
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
|
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
|
||||||
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
||||||
system.cpu.num_cc_register_reads 530849099 # number of times the CC registers were read
|
system.cpu.num_cc_register_reads 530854681 # number of times the CC registers were read
|
||||||
system.cpu.num_cc_register_writes 62363961 # number of times the CC registers were written
|
system.cpu.num_cc_register_writes 62364458 # number of times the CC registers were written
|
||||||
system.cpu.num_mem_refs 55938603 # number of memory refs
|
system.cpu.num_mem_refs 55939365 # number of memory refs
|
||||||
system.cpu.num_load_insts 31855595 # Number of load instructions
|
system.cpu.num_load_insts 31855962 # Number of load instructions
|
||||||
system.cpu.num_store_insts 24083008 # Number of store instructions
|
system.cpu.num_store_insts 24083403 # Number of store instructions
|
||||||
system.cpu.num_idle_cycles 5389630193.939086 # Number of idle cycles
|
system.cpu.num_idle_cycles 5389653746.932553 # Number of idle cycles
|
||||||
system.cpu.num_busy_cycles 178081810.060914 # Number of busy cycles
|
system.cpu.num_busy_cycles 178083667.067447 # Number of busy cycles
|
||||||
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
|
||||||
system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
|
system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
|
||||||
system.cpu.Branches 36396923 # Number of branches fetched
|
system.cpu.Branches 36397028 # Number of branches fetched
|
||||||
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
||||||
system.cpu.op_class::IntAlu 121151902 68.36% 68.36% # Class of executed instruction
|
system.cpu.op_class::IntAlu 121152975 68.36% 68.36% # Class of executed instruction
|
||||||
system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
|
system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction
|
||||||
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
|
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
|
||||||
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
|
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
|
||||||
system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
|
system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
|
||||||
|
|
@ -212,18 +209,18 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl
|
||||||
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
|
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
|
||||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
|
||||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
|
||||||
system.cpu.op_class::MemRead 31855595 17.98% 86.41% # Class of executed instruction
|
system.cpu.op_class::MemRead 31855962 17.98% 86.41% # Class of executed instruction
|
||||||
system.cpu.op_class::MemWrite 24083008 13.59% 100.00% # Class of executed instruction
|
system.cpu.op_class::MemWrite 24083403 13.59% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::total 177218284 # Class of executed instruction
|
system.cpu.op_class::total 177220138 # Class of executed instruction
|
||||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||||
system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed
|
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||||
system.cpu.dcache.tags.replacements 819396 # number of replacements
|
system.cpu.dcache.tags.replacements 819403 # number of replacements
|
||||||
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||||
system.cpu.dcache.tags.total_refs 53783832 # Total number of references to valid blocks.
|
system.cpu.dcache.tags.total_refs 53784550 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.sampled_refs 819908 # Sample count of references to valid blocks.
|
system.cpu.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.tags.avg_refs 65.597399 # Average number of references to valid blocks.
|
system.cpu.dcache.tags.avg_refs 65.597714 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
|
||||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||||
|
|
@ -233,58 +230,58 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||||
system.cpu.dcache.tags.tag_accesses 219234948 # Number of tag accesses
|
system.cpu.dcache.tags.tag_accesses 219237855 # Number of tag accesses
|
||||||
system.cpu.dcache.tags.data_accesses 219234948 # Number of data accesses
|
system.cpu.dcache.tags.data_accesses 219237855 # Number of data accesses
|
||||||
system.cpu.dcache.ReadReq_hits::cpu.data 30128799 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::cpu.data 30129122 # number of ReadReq hits
|
||||||
system.cpu.dcache.ReadReq_hits::total 30128799 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::total 30129122 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::cpu.data 22339754 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::cpu.data 22340107 # number of WriteReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::total 22339754 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits
|
||||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits
|
||||||
system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
|
system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.demand_hits::cpu.data 52468553 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::cpu.data 52469229 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.demand_hits::total 52468553 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::total 52469229 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits::cpu.data 52863618 # number of overall hits
|
system.cpu.dcache.overall_hits::cpu.data 52864309 # number of overall hits
|
||||||
system.cpu.dcache.overall_hits::total 52863618 # number of overall hits
|
system.cpu.dcache.overall_hits::total 52864309 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses::cpu.data 396285 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses
|
||||||
system.cpu.dcache.ReadReq_misses::total 396285 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses
|
||||||
system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses
|
||||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses
|
||||||
system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
|
system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses
|
||||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
|
||||||
system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses
|
system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
|
||||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
||||||
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
||||||
system.cpu.dcache.demand_misses::cpu.data 697948 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses::cpu.data 697955 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.demand_misses::total 697948 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses::total 697955 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses::cpu.data 814069 # number of overall misses
|
system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses
|
||||||
system.cpu.dcache.overall_misses::total 814069 # number of overall misses
|
system.cpu.dcache.overall_misses::total 814075 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::cpu.data 30525399 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641417 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::cpu.data 22641785 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::total 22641417 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses)
|
||||||
system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
|
system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses::cpu.data 53166501 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::cpu.data 53167184 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.demand_accesses::total 53166501 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::cpu.data 53677687 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::cpu.data 53678384 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::total 53677687 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::total 53678384 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses
|
||||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses
|
||||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses
|
||||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses
|
||||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
|
||||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses
|
||||||
|
|
@ -299,16 +296,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks::writebacks 682037 # number of writebacks
|
system.cpu.dcache.writebacks::writebacks 682060 # number of writebacks
|
||||||
system.cpu.dcache.writebacks::total 682037 # number of writebacks
|
system.cpu.dcache.writebacks::total 682060 # number of writebacks
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.tags.replacements 1699006 # number of replacements
|
system.cpu.icache.tags.replacements 1699220 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
|
system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use
|
||||||
system.cpu.icache.tags.total_refs 145341690 # Total number of references to valid blocks.
|
system.cpu.icache.tags.total_refs 145342961 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks.
|
system.cpu.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.tags.avg_refs 85.519359 # Average number of references to valid blocks.
|
system.cpu.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor
|
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor
|
||||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
|
system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||||
|
|
@ -317,32 +314,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
||||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||||
system.cpu.icache.tags.tag_accesses 148740738 # Number of tag accesses
|
system.cpu.icache.tags.tag_accesses 148742437 # Number of tag accesses
|
||||||
system.cpu.icache.tags.data_accesses 148740738 # Number of data accesses
|
system.cpu.icache.tags.data_accesses 148742437 # Number of data accesses
|
||||||
system.cpu.icache.ReadReq_hits::cpu.inst 145341690 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits::cpu.inst 145342961 # number of ReadReq hits
|
||||||
system.cpu.icache.ReadReq_hits::total 145341690 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits::total 145342961 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits::cpu.inst 145341690 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits::cpu.inst 145342961 # number of demand (read+write) hits
|
||||||
system.cpu.icache.demand_hits::total 145341690 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits::total 145342961 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits::cpu.inst 145341690 # number of overall hits
|
system.cpu.icache.overall_hits::cpu.inst 145342961 # number of overall hits
|
||||||
system.cpu.icache.overall_hits::total 145341690 # number of overall hits
|
system.cpu.icache.overall_hits::total 145342961 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses::cpu.inst 1699738 # number of ReadReq misses
|
||||||
system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses::total 1699738 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses::cpu.inst 1699738 # number of demand (read+write) misses
|
||||||
system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses::total 1699738 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses
|
system.cpu.icache.overall_misses::cpu.inst 1699738 # number of overall misses
|
||||||
system.cpu.icache.overall_misses::total 1699524 # number of overall misses
|
system.cpu.icache.overall_misses::total 1699738 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147041214 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses::cpu.inst 147042699 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.ReadReq_accesses::total 147041214 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses::cpu.inst 147041214 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses::cpu.inst 147042699 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.demand_accesses::total 147041214 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses::cpu.inst 147041214 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses::cpu.inst 147042699 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses::total 147041214 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses
|
||||||
system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses
|
||||||
system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -353,21 +350,21 @@ system.cpu.icache.fast_writes 0 # nu
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.tags.replacements 110027 # number of replacements
|
system.cpu.l2cache.tags.replacements 110027 # number of replacements
|
||||||
system.cpu.l2cache.tags.tagsinuse 65155.314992 # Cycle average of tags in use
|
system.cpu.l2cache.tags.tagsinuse 65155.309065 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.tags.total_refs 2727662 # Total number of references to valid blocks.
|
system.cpu.l2cache.tags.total_refs 2727894 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks.
|
system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.tags.avg_refs 15.559256 # Average number of references to valid blocks.
|
system.cpu.l2cache.tags.avg_refs 15.560579 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.tags.occ_blocks::writebacks 48893.413815 # Average occupied blocks per requestor
|
system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928 # Average occupied blocks per requestor
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654834 # Average occupied blocks per requestor
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.659727 # Average occupied blocks per requestor
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.310003 # Average occupied blocks per requestor
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.315067 # Average occupied blocks per requestor
|
||||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.109776 # Average percentage of cache occupancy
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.109777 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy
|
system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
||||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id
|
||||||
|
|
@ -379,29 +376,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id
|
||||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
||||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
|
||||||
system.cpu.l2cache.tags.tag_accesses 26202418 # Number of tag accesses
|
system.cpu.l2cache.tags.tag_accesses 26204409 # Number of tag accesses
|
||||||
system.cpu.l2cache.tags.data_accesses 26202418 # Number of data accesses
|
system.cpu.l2cache.tags.data_accesses 26204409 # Number of data accesses
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1681362 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.data 505483 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::cpu.data 505475 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_hits::total 2197850 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::total 2198059 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits::writebacks 682037 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits::writebacks 682060 # number of Writeback hits
|
||||||
system.cpu.l2cache.Writeback_hits::total 682037 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits::total 682060 # number of Writeback hits
|
||||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
||||||
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151043 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits::total 151043 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::cpu.inst 1681362 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_hits::cpu.data 656526 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::cpu.data 656533 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_hits::total 2348893 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::total 2349117 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits
|
||||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
|
||||||
system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits
|
system.cpu.l2cache.overall_hits::cpu.inst 1681362 # number of overall hits
|
||||||
system.cpu.l2cache.overall_hits::cpu.data 656526 # number of overall hits
|
system.cpu.l2cache.overall_hits::cpu.data 656533 # number of overall hits
|
||||||
system.cpu.l2cache.overall_hits::total 2348893 # number of overall hits
|
system.cpu.l2cache.overall_hits::total 2349117 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses
|
||||||
|
|
@ -423,50 +420,50 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 2
|
||||||
system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses
|
system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses
|
||||||
system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses
|
system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses
|
||||||
system.cpu.l2cache.overall_misses::total 181765 # number of overall misses
|
system.cpu.l2cache.overall_misses::total 181765 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699720 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 521017 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 521009 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::total 2231751 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::total 2231960 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses::writebacks 682037 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses::writebacks 682060 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses::total 682037 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses::total 682060 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses::cpu.inst 1699720 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_accesses::cpu.data 819924 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses::cpu.data 819931 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_accesses::total 2530658 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses::total 2530882 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses::cpu.inst 1699720 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses::cpu.data 819924 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses::cpu.data 819931 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses::total 2530658 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses::total 2530882 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010801 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.015189 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494682 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494682 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010801 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199284 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010801 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199284 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -475,45 +472,45 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks
|
system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks
|
||||||
system.cpu.l2cache.writebacks::total 101899 # number of writebacks
|
system.cpu.l2cache.writebacks::total 101898 # number of writebacks
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 2288348 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 2288556 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288348 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 2288556 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::Writeback 682037 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::Writeback 682060 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417520 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444665 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444702 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count::total 5917183 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count::total 5917652 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308299 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310219 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 205224775 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 205240399 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 36632 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 3268420 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 3268666 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.105033 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.105029 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::5 3231956 98.88% 98.88% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::5 3232202 98.88% 98.88% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 3268420 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 3268666 # Request fanout histogram
|
||||||
system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
|
system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
|
||||||
system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
|
system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
|
||||||
system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
|
system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
|
||||||
|
|
@ -570,23 +567,23 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321
|
||||||
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
|
system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.iocache.tags.replacements 36430 # number of replacements
|
system.iocache.tags.replacements 36430 # number of replacements
|
||||||
system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use
|
system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use
|
||||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||||
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
|
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
|
||||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||||
system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
|
system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
|
||||||
system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor
|
system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor
|
||||||
system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
|
system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy
|
||||||
system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
|
system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy
|
||||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||||
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
||||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||||
system.iocache.tags.tag_accesses 328176 # Number of tag accesses
|
system.iocache.tags.tag_accesses 328176 # Number of tag accesses
|
||||||
system.iocache.tags.data_accesses 328176 # Number of data accesses
|
system.iocache.tags.data_accesses 328176 # Number of data accesses
|
||||||
system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
|
|
||||||
system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
|
|
||||||
system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
|
system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
|
||||||
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
|
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
|
||||||
|
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
|
||||||
|
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
|
||||||
system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses
|
system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses
|
||||||
system.iocache.demand_misses::total 240 # number of demand (read+write) misses
|
system.iocache.demand_misses::total 240 # number of demand (read+write) misses
|
||||||
system.iocache.overall_misses::realview.ide 240 # number of overall misses
|
system.iocache.overall_misses::realview.ide 240 # number of overall misses
|
||||||
|
|
@ -601,6 +598,8 @@ system.iocache.overall_accesses::realview.ide 240
|
||||||
system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses
|
system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses
|
||||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||||
|
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
|
||||||
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
||||||
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
||||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||||
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
||||||
|
|
@ -611,14 +610,16 @@ system.iocache.blocked::no_mshrs 0 # nu
|
||||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
system.iocache.fast_writes 36224 # number of fast writes performed
|
system.iocache.fast_writes 0 # number of fast writes performed
|
||||||
system.iocache.cache_copies 0 # number of cache copies performed
|
system.iocache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||||
|
system.iocache.writebacks::total 36190 # number of writebacks
|
||||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.membus.trans_dist::ReadReq 74235 # Transaction distribution
|
system.membus.trans_dist::ReadReq 74235 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadResp 74235 # Transaction distribution
|
system.membus.trans_dist::ReadResp 74235 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteReq 27560 # Transaction distribution
|
system.membus.trans_dist::WriteReq 27560 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteResp 27560 # Transaction distribution
|
system.membus.trans_dist::WriteResp 27560 # Transaction distribution
|
||||||
system.membus.trans_dist::Writeback 101899 # Transaction distribution
|
system.membus.trans_dist::Writeback 138088 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
||||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||||
|
|
@ -629,31 +630,31 @@ system.membus.trans_dist::ReadExResp 146085 # Tr
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606196 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count::total 715314 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259459 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 22909315 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 322858 # Request fanout histogram
|
system.membus.snoop_fanout::samples 359047 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 359047 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 322858 # Request fanout histogram
|
system.membus.snoop_fanout::total 359047 # Request fanout histogram
|
||||||
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||||
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||||
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,87 +1,84 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 5.112155 # Number of seconds simulated
|
sim_seconds 5.112156 # Number of seconds simulated
|
||||||
sim_ticks 5112155173500 # Number of ticks simulated
|
sim_ticks 5112155738500 # Number of ticks simulated
|
||||||
final_tick 5112155173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 5112155738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1977176 # Simulator instruction rate (inst/s)
|
host_inst_rate 1511003 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 4047982 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 3093560 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 50529549296 # Simulator tick rate (ticks/s)
|
host_tick_rate 38615908446 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 594968 # Number of bytes of host memory used
|
host_mem_usage 595640 # Number of bytes of host memory used
|
||||||
host_seconds 101.17 # Real time elapsed on the host
|
host_seconds 132.38 # Real time elapsed on the host
|
||||||
sim_insts 200033988 # Number of instructions simulated
|
sim_insts 200033669 # Number of instructions simulated
|
||||||
sim_ops 409540726 # Number of ops (including micro ops) simulated
|
sim_ops 409539941 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
system.clk_domain.clock 1000 # Clock period in ticks
|
system.clk_domain.clock 1000 # Clock period in ticks
|
||||||
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu.inst 852288 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.inst 852224 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu.data 10678208 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.data 10636736 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
|
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::total 11559232 # Number of bytes read from this memory
|
system.physmem.bytes_read::total 11517696 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::cpu.inst 852288 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::cpu.inst 852224 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::total 852288 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::total 852224 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written::writebacks 6294336 # Number of bytes written to this memory
|
system.physmem.bytes_written::writebacks 9281152 # Number of bytes written to this memory
|
||||||
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
|
system.physmem.bytes_written::total 9281152 # Number of bytes written to this memory
|
||||||
system.physmem.bytes_written::total 9284416 # Number of bytes written to this memory
|
|
||||||
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu.inst 13317 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.inst 13316 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu.data 166847 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.data 166199 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
|
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::total 180613 # Number of read requests responded to by this memory
|
system.physmem.num_reads::total 179964 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes::writebacks 98349 # Number of write requests responded to by this memory
|
system.physmem.num_writes::writebacks 145018 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
|
system.physmem.num_writes::total 145018 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_writes::total 145069 # Number of write requests responded to by this memory
|
|
||||||
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu.inst 166718 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.inst 166705 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu.data 2088788 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.data 2080675 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::total 2261127 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::total 2253002 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu.inst 166718 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu.inst 166705 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::total 166718 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::total 166705 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write::writebacks 1231249 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write::writebacks 1815507 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write::pc.south_bridge.ide 584896 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write::total 1815507 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write::total 1816145 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_total::writebacks 1815507 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::writebacks 1231249 # Total bandwidth to/from this memory (bytes/s)
|
|
||||||
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.inst 166718 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 166705 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.data 2088788 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.data 2080675 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::pc.south_bridge.ide 590442 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 4077272 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 4068508 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||||
system.cpu.numCycles 10224314318 # number of cpu cycles simulated
|
system.cpu.numCycles 10224315447 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.committedInsts 200033988 # Number of instructions committed
|
system.cpu.committedInsts 200033669 # Number of instructions committed
|
||||||
system.cpu.committedOps 409540726 # Number of ops (including micro ops) committed
|
system.cpu.committedOps 409539941 # Number of ops (including micro ops) committed
|
||||||
system.cpu.num_int_alu_accesses 374550150 # Number of integer alu accesses
|
system.cpu.num_int_alu_accesses 374549395 # Number of integer alu accesses
|
||||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||||
system.cpu.num_func_calls 2308777 # number of times a function call or return occured
|
system.cpu.num_func_calls 2308749 # number of times a function call or return occured
|
||||||
system.cpu.num_conditional_control_insts 39994865 # number of instructions that are conditional controls
|
system.cpu.num_conditional_control_insts 39994798 # number of instructions that are conditional controls
|
||||||
system.cpu.num_int_insts 374550150 # number of integer instructions
|
system.cpu.num_int_insts 374549395 # number of integer instructions
|
||||||
system.cpu.num_fp_insts 0 # number of float instructions
|
system.cpu.num_fp_insts 0 # number of float instructions
|
||||||
system.cpu.num_int_register_reads 682630172 # number of times the integer registers were read
|
system.cpu.num_int_register_reads 682628451 # number of times the integer registers were read
|
||||||
system.cpu.num_int_register_writes 323525861 # number of times the integer registers were written
|
system.cpu.num_int_register_writes 323525110 # number of times the integer registers were written
|
||||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||||
system.cpu.num_cc_register_reads 233820803 # number of times the CC registers were read
|
system.cpu.num_cc_register_reads 233820400 # number of times the CC registers were read
|
||||||
system.cpu.num_cc_register_writes 157313619 # number of times the CC registers were written
|
system.cpu.num_cc_register_writes 157313425 # number of times the CC registers were written
|
||||||
system.cpu.num_mem_refs 35680563 # number of memory refs
|
system.cpu.num_mem_refs 35680406 # number of memory refs
|
||||||
system.cpu.num_load_insts 27249389 # Number of load instructions
|
system.cpu.num_load_insts 27249300 # Number of load instructions
|
||||||
system.cpu.num_store_insts 8431174 # Number of store instructions
|
system.cpu.num_store_insts 8431106 # Number of store instructions
|
||||||
system.cpu.num_idle_cycles 9770366809.410368 # Number of idle cycles
|
system.cpu.num_idle_cycles 9770368815.449127 # Number of idle cycles
|
||||||
system.cpu.num_busy_cycles 453947508.589632 # Number of busy cycles
|
system.cpu.num_busy_cycles 453946631.550873 # Number of busy cycles
|
||||||
system.cpu.not_idle_fraction 0.044399 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 0.044399 # Percentage of non-idle cycles
|
||||||
system.cpu.idle_fraction 0.955601 # Percentage of idle cycles
|
system.cpu.idle_fraction 0.955601 # Percentage of idle cycles
|
||||||
system.cpu.Branches 43145769 # Number of branches fetched
|
system.cpu.Branches 43145649 # Number of branches fetched
|
||||||
system.cpu.op_class::No_OpClass 175400 0.04% 0.04% # Class of executed instruction
|
system.cpu.op_class::No_OpClass 175370 0.04% 0.04% # Class of executed instruction
|
||||||
system.cpu.op_class::IntAlu 373418196 91.18% 91.22% # Class of executed instruction
|
system.cpu.op_class::IntAlu 373417675 91.18% 91.22% # Class of executed instruction
|
||||||
system.cpu.op_class::IntMult 144548 0.04% 91.26% # Class of executed instruction
|
system.cpu.op_class::IntMult 144551 0.04% 91.26% # Class of executed instruction
|
||||||
system.cpu.op_class::IntDiv 123054 0.03% 91.29% # Class of executed instruction
|
system.cpu.op_class::IntDiv 122974 0.03% 91.29% # Class of executed instruction
|
||||||
system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
|
system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
|
||||||
system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
|
system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
|
||||||
system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction
|
system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction
|
||||||
|
|
@ -108,18 +105,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl
|
||||||
system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
|
system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
|
||||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
|
||||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
|
||||||
system.cpu.op_class::MemRead 27249389 6.65% 97.94% # Class of executed instruction
|
system.cpu.op_class::MemRead 27249300 6.65% 97.94% # Class of executed instruction
|
||||||
system.cpu.op_class::MemWrite 8431174 2.06% 100.00% # Class of executed instruction
|
system.cpu.op_class::MemWrite 8431106 2.06% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::total 409541761 # Class of executed instruction
|
system.cpu.op_class::total 409540976 # Class of executed instruction
|
||||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||||
system.cpu.dcache.tags.replacements 1623441 # number of replacements
|
system.cpu.dcache.tags.replacements 1623460 # number of replacements
|
||||||
system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use
|
system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use
|
||||||
system.cpu.dcache.tags.total_refs 20193263 # Total number of references to valid blocks.
|
system.cpu.dcache.tags.total_refs 20193083 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.sampled_refs 1623953 # Sample count of references to valid blocks.
|
system.cpu.dcache.tags.sampled_refs 1623972 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.tags.avg_refs 12.434635 # Average number of references to valid blocks.
|
system.cpu.dcache.tags.avg_refs 12.434379 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor
|
||||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||||
|
|
@ -129,48 +126,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 233
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||||
system.cpu.dcache.tags.tag_accesses 88892882 # Number of tag accesses
|
system.cpu.dcache.tags.tag_accesses 88892257 # Number of tag accesses
|
||||||
system.cpu.dcache.tags.data_accesses 88892882 # Number of data accesses
|
system.cpu.dcache.tags.data_accesses 88892257 # Number of data accesses
|
||||||
system.cpu.dcache.ReadReq_hits::cpu.data 12028464 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::cpu.data 12028370 # number of ReadReq hits
|
||||||
system.cpu.dcache.ReadReq_hits::total 12028464 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::total 12028370 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::cpu.data 8103633 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::cpu.data 8103548 # number of WriteReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::total 8103633 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::total 8103548 # number of WriteReq hits
|
||||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 58902 # number of SoftPFReq hits
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 58901 # number of SoftPFReq hits
|
||||||
system.cpu.dcache.SoftPFReq_hits::total 58902 # number of SoftPFReq hits
|
system.cpu.dcache.SoftPFReq_hits::total 58901 # number of SoftPFReq hits
|
||||||
system.cpu.dcache.demand_hits::cpu.data 20132097 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::cpu.data 20131918 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.demand_hits::total 20132097 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::total 20131918 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits::cpu.data 20190999 # number of overall hits
|
system.cpu.dcache.overall_hits::cpu.data 20190819 # number of overall hits
|
||||||
system.cpu.dcache.overall_hits::total 20190999 # number of overall hits
|
system.cpu.dcache.overall_hits::total 20190819 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses::cpu.data 905998 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::cpu.data 906001 # number of ReadReq misses
|
||||||
system.cpu.dcache.ReadReq_misses::total 905998 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::total 906001 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses::cpu.data 317173 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses::cpu.data 317188 # number of WriteReq misses
|
||||||
system.cpu.dcache.WriteReq_misses::total 317173 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses::total 317188 # number of WriteReq misses
|
||||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 403059 # number of SoftPFReq misses
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 403060 # number of SoftPFReq misses
|
||||||
system.cpu.dcache.SoftPFReq_misses::total 403059 # number of SoftPFReq misses
|
system.cpu.dcache.SoftPFReq_misses::total 403060 # number of SoftPFReq misses
|
||||||
system.cpu.dcache.demand_misses::cpu.data 1223171 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses::cpu.data 1223189 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.demand_misses::total 1223171 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses::total 1223189 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses::cpu.data 1626230 # number of overall misses
|
system.cpu.dcache.overall_misses::cpu.data 1626249 # number of overall misses
|
||||||
system.cpu.dcache.overall_misses::total 1626230 # number of overall misses
|
system.cpu.dcache.overall_misses::total 1626249 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.data 12934462 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::cpu.data 12934371 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_accesses::total 12934462 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::total 12934371 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8420806 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::cpu.data 8420736 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::total 8420806 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::total 8420736 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses)
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses)
|
||||||
system.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses)
|
system.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses::cpu.data 21355268 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::cpu.data 21355107 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.demand_accesses::total 21355268 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::total 21355107 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::cpu.data 21817229 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::cpu.data 21817068 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::total 21817229 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::total 21817068 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070045 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070046 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::total 0.070045 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::total 0.070046 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037665 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037667 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate::total 0.037665 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate::total 0.037667 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872496 # miss rate for SoftPFReq accesses
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872498 # miss rate for SoftPFReq accesses
|
||||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.872496 # miss rate for SoftPFReq accesses
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.872498 # miss rate for SoftPFReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.057277 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_miss_rate::total 0.057277 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074539 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.074540 # miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.074539 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::total 0.074540 # miss rate for overall accesses
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -179,49 +176,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks::writebacks 1536849 # number of writebacks
|
system.cpu.dcache.writebacks::writebacks 1536867 # number of writebacks
|
||||||
system.cpu.dcache.writebacks::total 1536849 # number of writebacks
|
system.cpu.dcache.writebacks::total 1536867 # number of writebacks
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements
|
system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements
|
||||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.013947 # Cycle average of tags in use
|
system.cpu.dtb_walker_cache.tags.tagsinuse 5.013943 # Cycle average of tags in use
|
||||||
system.cpu.dtb_walker_cache.tags.total_refs 12516 # Total number of references to valid blocks.
|
system.cpu.dtb_walker_cache.tags.total_refs 12520 # Total number of references to valid blocks.
|
||||||
system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks.
|
system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks.
|
||||||
system.cpu.dtb_walker_cache.tags.avg_refs 1.528578 # Average number of references to valid blocks.
|
system.cpu.dtb_walker_cache.tags.avg_refs 1.529067 # Average number of references to valid blocks.
|
||||||
system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500 # Cycle when the warmup percentage was hit.
|
system.cpu.dtb_walker_cache.tags.warmup_cycle 5101318572500 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013947 # Average occupied blocks per requestor
|
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013943 # Average occupied blocks per requestor
|
||||||
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy
|
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313371 # Average percentage of cache occupancy
|
||||||
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy
|
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313371 # Average percentage of cache occupancy
|
||||||
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
|
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
|
||||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
|
||||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
|
||||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
||||||
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
|
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
|
||||||
system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses
|
system.cpu.dtb_walker_cache.tags.tag_accesses 53161 # Number of tag accesses
|
||||||
system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses
|
system.cpu.dtb_walker_cache.tags.data_accesses 53161 # Number of data accesses
|
||||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12517 # number of ReadReq hits
|
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12521 # number of ReadReq hits
|
||||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12517 # number of ReadReq hits
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 12521 # number of ReadReq hits
|
||||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12517 # number of demand (read+write) hits
|
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12521 # number of demand (read+write) hits
|
||||||
system.cpu.dtb_walker_cache.demand_hits::total 12517 # number of demand (read+write) hits
|
system.cpu.dtb_walker_cache.demand_hits::total 12521 # number of demand (read+write) hits
|
||||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12517 # number of overall hits
|
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12521 # number of overall hits
|
||||||
system.cpu.dtb_walker_cache.overall_hits::total 12517 # number of overall hits
|
system.cpu.dtb_walker_cache.overall_hits::total 12521 # number of overall hits
|
||||||
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses
|
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses
|
||||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses
|
||||||
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses
|
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses
|
||||||
system.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses
|
system.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses
|
||||||
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses
|
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses
|
||||||
system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses
|
system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses
|
||||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21890 # number of ReadReq accesses(hits+misses)
|
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21894 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21890 # number of ReadReq accesses(hits+misses)
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21894 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21890 # number of demand (read+write) accesses
|
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21894 # number of demand (read+write) accesses
|
||||||
system.cpu.dtb_walker_cache.demand_accesses::total 21890 # number of demand (read+write) accesses
|
system.cpu.dtb_walker_cache.demand_accesses::total 21894 # number of demand (read+write) accesses
|
||||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21890 # number of overall (read+write) accesses
|
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21894 # number of overall (read+write) accesses
|
||||||
system.cpu.dtb_walker_cache.overall_accesses::total 21890 # number of overall (read+write) accesses
|
system.cpu.dtb_walker_cache.overall_accesses::total 21894 # number of overall (read+write) accesses
|
||||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428186 # miss rate for ReadReq accesses
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428108 # miss rate for ReadReq accesses
|
||||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428186 # miss rate for ReadReq accesses
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428108 # miss rate for ReadReq accesses
|
||||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428186 # miss rate for demand accesses
|
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428108 # miss rate for demand accesses
|
||||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428186 # miss rate for demand accesses
|
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428108 # miss rate for demand accesses
|
||||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428186 # miss rate for overall accesses
|
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428108 # miss rate for overall accesses
|
||||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428186 # miss rate for overall accesses
|
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428108 # miss rate for overall accesses
|
||||||
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -233,11 +230,11 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu
|
||||||
system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks
|
system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks
|
||||||
system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks
|
system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks
|
||||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.tags.replacements 791952 # number of replacements
|
system.cpu.icache.tags.replacements 791846 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 510.663108 # Cycle average of tags in use
|
system.cpu.icache.tags.tagsinuse 510.663108 # Cycle average of tags in use
|
||||||
system.cpu.icache.tags.total_refs 243645979 # Total number of references to valid blocks.
|
system.cpu.icache.tags.total_refs 243645674 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.tags.sampled_refs 792464 # Sample count of references to valid blocks.
|
system.cpu.icache.tags.sampled_refs 792358 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.tags.avg_refs 307.453687 # Average number of references to valid blocks.
|
system.cpu.icache.tags.avg_refs 307.494433 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.tags.warmup_cycle 148876575500 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.tags.warmup_cycle 148876575500 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.663108 # Average occupied blocks per requestor
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.663108 # Average occupied blocks per requestor
|
||||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy
|
||||||
|
|
@ -248,26 +245,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 134
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
||||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||||
system.cpu.icache.tags.tag_accesses 245230921 # Number of tag accesses
|
system.cpu.icache.tags.tag_accesses 245230404 # Number of tag accesses
|
||||||
system.cpu.icache.tags.data_accesses 245230921 # Number of data accesses
|
system.cpu.icache.tags.data_accesses 245230404 # Number of data accesses
|
||||||
system.cpu.icache.ReadReq_hits::cpu.inst 243645979 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits::cpu.inst 243645674 # number of ReadReq hits
|
||||||
system.cpu.icache.ReadReq_hits::total 243645979 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits::total 243645674 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits::cpu.inst 243645979 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits::cpu.inst 243645674 # number of demand (read+write) hits
|
||||||
system.cpu.icache.demand_hits::total 243645979 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits::total 243645674 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits::cpu.inst 243645979 # number of overall hits
|
system.cpu.icache.overall_hits::cpu.inst 243645674 # number of overall hits
|
||||||
system.cpu.icache.overall_hits::total 243645979 # number of overall hits
|
system.cpu.icache.overall_hits::total 243645674 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses::cpu.inst 792471 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses::cpu.inst 792365 # number of ReadReq misses
|
||||||
system.cpu.icache.ReadReq_misses::total 792471 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses::total 792365 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses::cpu.inst 792471 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses::cpu.inst 792365 # number of demand (read+write) misses
|
||||||
system.cpu.icache.demand_misses::total 792471 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses::total 792365 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses::cpu.inst 792471 # number of overall misses
|
system.cpu.icache.overall_misses::cpu.inst 792365 # number of overall misses
|
||||||
system.cpu.icache.overall_misses::total 792471 # number of overall misses
|
system.cpu.icache.overall_misses::total 792365 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244438450 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses::cpu.inst 244438039 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.ReadReq_accesses::total 244438450 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses::total 244438039 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses::cpu.inst 244438450 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses::cpu.inst 244438039 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.demand_accesses::total 244438450 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses::total 244438039 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses::cpu.inst 244438450 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses::cpu.inst 244438039 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses::total 244438450 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses::total 244438039 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003242 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003242 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate::total 0.003242 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate::total 0.003242 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.003242 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.003242 # miss rate for demand accesses
|
||||||
|
|
@ -284,12 +281,12 @@ system.cpu.icache.fast_writes 0 # nu
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements
|
system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements
|
||||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026453 # Cycle average of tags in use
|
system.cpu.itb_walker_cache.tags.tagsinuse 3.026443 # Cycle average of tags in use
|
||||||
system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks.
|
system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks.
|
||||||
system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks.
|
system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks.
|
||||||
system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks.
|
system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks.
|
||||||
system.cpu.itb_walker_cache.tags.warmup_cycle 5102140605000 # Cycle when the warmup percentage was hit.
|
system.cpu.itb_walker_cache.tags.warmup_cycle 5102148365500 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026453 # Average occupied blocks per requestor
|
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026443 # Average occupied blocks per requestor
|
||||||
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy
|
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy
|
||||||
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy
|
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy
|
||||||
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
|
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
|
||||||
|
|
@ -339,17 +336,17 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu
|
||||||
system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks
|
system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks
|
||||||
system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks
|
system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks
|
||||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.tags.replacements 106197 # number of replacements
|
system.cpu.l2cache.tags.replacements 106199 # number of replacements
|
||||||
system.cpu.l2cache.tags.tagsinuse 64825.457913 # Cycle average of tags in use
|
system.cpu.l2cache.tags.tagsinuse 64825.456332 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.tags.total_refs 3461872 # Total number of references to valid blocks.
|
system.cpu.l2cache.tags.total_refs 3461789 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.tags.sampled_refs 170308 # Sample count of references to valid blocks.
|
system.cpu.l2cache.tags.sampled_refs 170310 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.tags.avg_refs 20.327125 # Average number of references to valid blocks.
|
system.cpu.l2cache.tags.avg_refs 20.326399 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51911.004327 # Average occupied blocks per requestor
|
system.cpu.l2cache.tags.occ_blocks::writebacks 51911.006068 # Average occupied blocks per requestor
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132278 # Average occupied blocks per requestor
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132276 # Average occupied blocks per requestor
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.291417 # Average occupied blocks per requestor
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.288805 # Average occupied blocks per requestor
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.027412 # Average occupied blocks per requestor
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.026704 # Average occupied blocks per requestor
|
||||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.792099 # Average percentage of cache occupancy
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.792099 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||||
|
|
@ -360,32 +357,32 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024 64111
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498 # Occupied blocks per task id
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498 # Occupied blocks per task id
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20716 # Occupied blocks per task id
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20721 # Occupied blocks per task id
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39582 # Occupied blocks per task id
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39577 # Occupied blocks per task id
|
||||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id
|
||||||
system.cpu.l2cache.tags.tag_accesses 32246059 # Number of tag accesses
|
system.cpu.l2cache.tags.tag_accesses 32245523 # Number of tag accesses
|
||||||
system.cpu.l2cache.tags.data_accesses 32246059 # Number of data accesses
|
system.cpu.l2cache.tags.data_accesses 32245523 # Number of data accesses
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7331 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7331 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 779141 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 779035 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1276184 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1276188 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_hits::total 2065993 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::total 2065891 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits::writebacks 1540445 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits::writebacks 1540463 # number of Writeback hits
|
||||||
system.cpu.l2cache.Writeback_hits::total 1540445 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits::total 1540463 # number of Writeback hits
|
||||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits
|
||||||
system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits
|
system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 180006 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 180020 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits::total 180006 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits::total 180020 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7331 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7331 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 3337 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 3337 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_hits::cpu.inst 779141 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::cpu.inst 779035 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_hits::cpu.data 1456190 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::cpu.data 1456208 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_hits::total 2245999 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::total 2245911 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7331 # number of overall hits
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7331 # number of overall hits
|
||||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 3337 # number of overall hits
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 3337 # number of overall hits
|
||||||
system.cpu.l2cache.overall_hits::cpu.inst 779141 # number of overall hits
|
system.cpu.l2cache.overall_hits::cpu.inst 779035 # number of overall hits
|
||||||
system.cpu.l2cache.overall_hits::cpu.data 1456190 # number of overall hits
|
system.cpu.l2cache.overall_hits::cpu.data 1456208 # number of overall hits
|
||||||
system.cpu.l2cache.overall_hits::total 2245999 # number of overall hits
|
system.cpu.l2cache.overall_hits::total 2245911 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13317 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 13317 # number of ReadReq misses
|
||||||
|
|
@ -393,58 +390,58 @@ system.cpu.l2cache.ReadReq_misses::cpu.data 32232 #
|
||||||
system.cpu.l2cache.ReadReq_misses::total 45555 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::total 45555 # number of ReadReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1813 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1813 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_misses::total 1813 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses::total 1813 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 134898 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 134899 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses::total 134898 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses::total 134899 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.demand_misses::cpu.inst 13317 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses::cpu.inst 13317 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.demand_misses::cpu.data 167130 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses::cpu.data 167131 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.demand_misses::total 180453 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses::total 180454 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
|
||||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
|
||||||
system.cpu.l2cache.overall_misses::cpu.inst 13317 # number of overall misses
|
system.cpu.l2cache.overall_misses::cpu.inst 13317 # number of overall misses
|
||||||
system.cpu.l2cache.overall_misses::cpu.data 167130 # number of overall misses
|
system.cpu.l2cache.overall_misses::cpu.data 167131 # number of overall misses
|
||||||
system.cpu.l2cache.overall_misses::total 180453 # number of overall misses
|
system.cpu.l2cache.overall_misses::total 180454 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7332 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7332 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 792458 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 792352 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1308416 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1308420 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::total 2111548 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::total 2111446 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses::writebacks 1540445 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses::writebacks 1540463 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses::total 1540445 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses::total 1540463 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1835 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1835 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314904 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314919 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses::total 314904 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses::total 314919 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7332 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7332 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_accesses::cpu.inst 792458 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses::cpu.inst 792352 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_accesses::cpu.data 1623320 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses::cpu.data 1623339 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_accesses::total 2426452 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses::total 2426365 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7332 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7332 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses::cpu.inst 792458 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses::cpu.inst 792352 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses::cpu.data 1623320 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses::cpu.data 1623339 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses::total 2426452 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses::total 2426365 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016805 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024634 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024634 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.021574 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.021575 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988011 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988011 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988011 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988011 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428378 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428361 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428378 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428361 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016805 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102956 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102955 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::total 0.074369 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::total 0.074372 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016805 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102956 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102955 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::total 0.074369 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::total 0.074372 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -453,42 +450,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.writebacks::writebacks 98349 # number of writebacks
|
system.cpu.l2cache.writebacks::writebacks 98351 # number of writebacks
|
||||||
system.cpu.l2cache.writebacks::total 98349 # number of writebacks
|
system.cpu.l2cache.writebacks::total 98351 # number of writebacks
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 15972786 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 15972684 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 15972786 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 15972684 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::Writeback 1540445 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::Writeback 1540463 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 314909 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadExReq 314924 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 314909 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadExResp 314924 # Transaction distribution
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584942 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584730 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531741 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531797 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count::total 34148185 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count::total 34148029 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50718144 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50711360 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227716857 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227719225 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 279558137 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 279553721 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 48008 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 48008 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 4020727 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 4020658 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.108191 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.108192 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 3973099 98.82% 98.82% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::3 3973030 98.82% 98.82% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 4020727 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 4020658 # Request fanout histogram
|
||||||
system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution
|
system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution
|
||||||
system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution
|
system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution
|
||||||
system.iobus.trans_dist::WriteReq 57692 # Transaction distribution
|
system.iobus.trans_dist::WriteReq 57692 # Transaction distribution
|
||||||
|
|
@ -545,12 +542,12 @@ system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbrid
|
||||||
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes)
|
system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.iocache.tags.replacements 47573 # number of replacements
|
system.iocache.tags.replacements 47573 # number of replacements
|
||||||
system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use
|
system.iocache.tags.tagsinuse 0.042450 # Cycle average of tags in use
|
||||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||||
system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks.
|
system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks.
|
||||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||||
system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit.
|
system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit.
|
||||||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor
|
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042450 # Average occupied blocks per requestor
|
||||||
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
|
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
|
||||||
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
|
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
|
||||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||||
|
|
@ -558,10 +555,10 @@ system.iocache.tags.age_task_id_blocks_1023::2 16
|
||||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||||
system.iocache.tags.tag_accesses 428652 # Number of tag accesses
|
system.iocache.tags.tag_accesses 428652 # Number of tag accesses
|
||||||
system.iocache.tags.data_accesses 428652 # Number of data accesses
|
system.iocache.tags.data_accesses 428652 # Number of data accesses
|
||||||
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
|
|
||||||
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
|
|
||||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses
|
system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses
|
||||||
system.iocache.ReadReq_misses::total 908 # number of ReadReq misses
|
system.iocache.ReadReq_misses::total 908 # number of ReadReq misses
|
||||||
|
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
|
||||||
|
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
|
||||||
system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses
|
system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses
|
||||||
system.iocache.demand_misses::total 908 # number of demand (read+write) misses
|
system.iocache.demand_misses::total 908 # number of demand (read+write) misses
|
||||||
system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses
|
system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses
|
||||||
|
|
@ -576,6 +573,8 @@ system.iocache.overall_accesses::pc.south_bridge.ide 908
|
||||||
system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses
|
system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses
|
||||||
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
||||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||||
|
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
|
||||||
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
||||||
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
||||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||||
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
||||||
|
|
@ -586,52 +585,54 @@ system.iocache.blocked::no_mshrs 0 # nu
|
||||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
system.iocache.fast_writes 46720 # number of fast writes performed
|
system.iocache.fast_writes 0 # number of fast writes performed
|
||||||
system.iocache.cache_copies 0 # number of cache copies performed
|
system.iocache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
||||||
|
system.iocache.writebacks::total 46667 # number of writebacks
|
||||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.membus.trans_dist::ReadReq 13903768 # Transaction distribution
|
system.membus.trans_dist::ReadReq 13903768 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadResp 13903768 # Transaction distribution
|
system.membus.trans_dist::ReadResp 13903768 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteReq 13911 # Transaction distribution
|
system.membus.trans_dist::WriteReq 13911 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteResp 13911 # Transaction distribution
|
system.membus.trans_dist::WriteResp 13911 # Transaction distribution
|
||||||
system.membus.trans_dist::Writeback 98349 # Transaction distribution
|
system.membus.trans_dist::Writeback 145018 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
|
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
||||||
system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution
|
system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution
|
||||||
system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution
|
system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadExReq 134620 # Transaction distribution
|
system.membus.trans_dist::ReadExReq 134621 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadExResp 134615 # Transaction distribution
|
system.membus.trans_dist::ReadExResp 134616 # Transaction distribution
|
||||||
system.membus.trans_dist::MessageReq 1696 # Transaction distribution
|
system.membus.trans_dist::MessageReq 1696 # Transaction distribution
|
||||||
system.membus.trans_dist::MessageResp 1696 # Transaction distribution
|
system.membus.trans_dist::MessageResp 1696 # Transaction distribution
|
||||||
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463315 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463319 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205747 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205751 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141923 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::total 141923 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count::total 28304395 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count::total 28351066 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825216 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825408 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43249913 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43250105 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6034880 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 6034880 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 46304889 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 49291769 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 328677 # Request fanout histogram
|
system.membus.snoop_fanout::samples 375347 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 328677 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 375347 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 328677 # Request fanout histogram
|
system.membus.snoop_fanout::total 375347 # Request fanout histogram
|
||||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
||||||
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,13 +1,13 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.000035 # Number of seconds simulated
|
sim_seconds 0.000035 # Number of seconds simulated
|
||||||
sim_ticks 35024500 # Number of ticks simulated
|
sim_ticks 35022500 # Number of ticks simulated
|
||||||
final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 35022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 72507 # Simulator instruction rate (inst/s)
|
host_inst_rate 71946 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 72491 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 71929 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 396631772 # Simulator tick rate (ticks/s)
|
host_tick_rate 393524726 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 236200 # Number of bytes of host memory used
|
host_mem_usage 237176 # Number of bytes of host memory used
|
||||||
host_seconds 0.09 # Real time elapsed on the host
|
host_seconds 0.09 # Real time elapsed on the host
|
||||||
sim_insts 6400 # Number of instructions simulated
|
sim_insts 6400 # Number of instructions simulated
|
||||||
sim_ops 6400 # Number of ops (including micro ops) simulated
|
sim_ops 6400 # Number of ops (including micro ops) simulated
|
||||||
|
|
@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 23296 # Nu
|
||||||
system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory
|
||||||
system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
|
system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
|
||||||
system.physmem.bw_read::cpu.inst 973946809 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.inst 974002427 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::total 973946809 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::total 974002427 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu.inst 665134406 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu.inst 665172389 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::total 665134406 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::total 665172389 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.inst 973946809 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 974002427 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 973946809 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 974002427 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.readReqs 533 # Number of read requests accepted
|
system.physmem.readReqs 533 # Number of read requests accepted
|
||||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||||
system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
|
system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
|
||||||
|
|
@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
||||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||||
system.physmem.totGap 34926000 # Total gap between requests
|
system.physmem.totGap 34924000 # Total gap between requests
|
||||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||||
|
|
@ -196,15 +196,15 @@ system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # By
|
||||||
system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation
|
||||||
system.physmem.totQLat 3928000 # Total ticks spent queuing
|
system.physmem.totQLat 3887500 # Total ticks spent queuing
|
||||||
system.physmem.totMemAccLat 13921750 # Total ticks spent from burst creation until serviced by the DRAM
|
system.physmem.totMemAccLat 13881250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||||
system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers
|
system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers
|
||||||
system.physmem.avgQLat 7369.61 # Average queueing delay per DRAM burst
|
system.physmem.avgQLat 7293.62 # Average queueing delay per DRAM burst
|
||||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||||
system.physmem.avgMemAccLat 26119.61 # Average memory access latency per DRAM burst
|
system.physmem.avgMemAccLat 26043.62 # Average memory access latency per DRAM burst
|
||||||
system.physmem.avgRdBW 973.95 # Average DRAM read bandwidth in MiByte/s
|
system.physmem.avgRdBW 974.00 # Average DRAM read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||||
system.physmem.avgRdBWSys 973.95 # Average system read bandwidth in MiByte/s
|
system.physmem.avgRdBWSys 974.00 # Average system read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||||
system.physmem.busUtil 7.61 # Data bus utilization in percentage
|
system.physmem.busUtil 7.61 # Data bus utilization in percentage
|
||||||
|
|
@ -216,12 +216,12 @@ system.physmem.readRowHits 435 # Nu
|
||||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||||
system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads
|
system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads
|
||||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||||
system.physmem.avgGap 65527.20 # Average gap between requests
|
system.physmem.avgGap 65523.45 # Average gap between requests
|
||||||
system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined
|
system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined
|
||||||
system.physmem.memoryStateTime::IDLE 15500 # Time in different power states
|
system.physmem.memoryStateTime::IDLE 15500 # Time in different power states
|
||||||
system.physmem.memoryStateTime::REF 1040000 # Time in different power states
|
system.physmem.memoryStateTime::REF 1040000 # Time in different power states
|
||||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT 30394500 # Time in different power states
|
system.physmem.memoryStateTime::ACT 30393500 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||||
system.physmem.actEnergy::0 257040 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::0 257040 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem.actEnergy::1 385560 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::1 385560 # Energy for activate commands per rank (pJ)
|
||||||
|
|
@ -234,66 +234,43 @@ system.physmem.writeEnergy::1 0 # En
|
||||||
system.physmem.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.actBackEnergy::0 21425445 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::0 21425445 # Energy for active background per rank (pJ)
|
||||||
system.physmem.actBackEnergy::1 20168595 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::1 20164320 # Energy for active background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::0 67500 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::0 67500 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::1 1170000 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::1 1173750 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.totalEnergy::0 26007075 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::0 26007075 # Total energy per rank (pJ)
|
||||||
system.physmem.totalEnergy::1 25645770 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::1 25645245 # Total energy per rank (pJ)
|
||||||
system.physmem.averagePower::0 827.295718 # Core power per rank (mW)
|
system.physmem.averagePower::0 827.295718 # Core power per rank (mW)
|
||||||
system.physmem.averagePower::1 815.802457 # Core power per rank (mW)
|
system.physmem.averagePower::1 815.785757 # Core power per rank (mW)
|
||||||
system.membus.trans_dist::ReadReq 460 # Transaction distribution
|
system.cpu.branchPred.lookups 1972 # Number of BP lookups
|
||||||
system.membus.trans_dist::ReadResp 460 # Transaction distribution
|
system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted
|
||||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
|
||||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 533 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 533 # Request fanout histogram
|
|
||||||
system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks)
|
|
||||||
system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
|
|
||||||
system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks)
|
|
||||||
system.membus.respLayer1.utilization 14.2 # Layer utilization (%)
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
||||||
system.cpu.branchPred.lookups 1959 # Number of BP lookups
|
|
||||||
system.cpu.branchPred.condPredicted 1201 # Number of conditional branches predicted
|
|
||||||
system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect
|
system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect
|
||||||
system.cpu.branchPred.BTBLookups 1551 # Number of BTB lookups
|
system.cpu.branchPred.BTBLookups 1563 # Number of BTB lookups
|
||||||
system.cpu.branchPred.BTBHits 381 # Number of BTB hits
|
system.cpu.branchPred.BTBHits 385 # Number of BTB hits
|
||||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.branchPred.BTBHitPct 24.564797 # BTB Hit Percentage
|
system.cpu.branchPred.BTBHitPct 24.632118 # BTB Hit Percentage
|
||||||
system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
|
system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
|
system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
|
||||||
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 1368 # DTB read hits
|
system.cpu.dtb.read_hits 1370 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 11 # DTB read misses
|
system.cpu.dtb.read_misses 11 # DTB read misses
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.read_accesses 1379 # DTB read accesses
|
system.cpu.dtb.read_accesses 1381 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 884 # DTB write hits
|
system.cpu.dtb.write_hits 884 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.dtb.write_accesses 887 # DTB write accesses
|
system.cpu.dtb.write_accesses 887 # DTB write accesses
|
||||||
system.cpu.dtb.data_hits 2252 # DTB hits
|
system.cpu.dtb.data_hits 2254 # DTB hits
|
||||||
system.cpu.dtb.data_misses 14 # DTB misses
|
system.cpu.dtb.data_misses 14 # DTB misses
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.dtb.data_accesses 2266 # DTB accesses
|
system.cpu.dtb.data_accesses 2268 # DTB accesses
|
||||||
system.cpu.itb.fetch_hits 2630 # ITB hits
|
system.cpu.itb.fetch_hits 2642 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.fetch_accesses 2647 # ITB accesses
|
system.cpu.itb.fetch_accesses 2659 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
|
|
@ -307,68 +284,180 @@ system.cpu.itb.data_misses 0 # DT
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||||
system.cpu.numCycles 70049 # number of cpu cycles simulated
|
system.cpu.numCycles 70045 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.committedInsts 6400 # Number of instructions committed
|
system.cpu.committedInsts 6400 # Number of instructions committed
|
||||||
system.cpu.committedOps 6400 # Number of ops (including micro ops) committed
|
system.cpu.committedOps 6400 # Number of ops (including micro ops) committed
|
||||||
system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit
|
system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit
|
||||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||||
system.cpu.cpi 10.945156 # CPI: cycles per instruction
|
system.cpu.cpi 10.944531 # CPI: cycles per instruction
|
||||||
system.cpu.ipc 0.091365 # IPC: instructions per cycle
|
system.cpu.ipc 0.091370 # IPC: instructions per cycle
|
||||||
system.cpu.tickCycles 12515 # Number of cycles that the object actually ticked
|
system.cpu.tickCycles 12615 # Number of cycles that the object actually ticked
|
||||||
system.cpu.idleCycles 57534 # Total number of cycles that the object has spent stopped
|
system.cpu.idleCycles 57430 # Total number of cycles that the object has spent stopped
|
||||||
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||||
|
system.cpu.dcache.tags.tagsinuse 104.047628 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.tags.occ_blocks::cpu.inst 104.047628 # Average occupied blocks per requestor
|
||||||
|
system.cpu.dcache.tags.occ_percent::cpu.inst 0.025402 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.tags.occ_percent::total 0.025402 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
|
||||||
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
|
||||||
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
|
||||||
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.dcache.tags.tag_accesses 4569 # Number of tag accesses
|
||||||
|
system.cpu.dcache.tags.data_accesses 4569 # Number of data accesses
|
||||||
|
system.cpu.dcache.ReadReq_hits::cpu.inst 1233 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.ReadReq_hits::total 1233 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.demand_hits::cpu.inst 1973 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.demand_hits::total 1973 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits::cpu.inst 1973 # number of overall hits
|
||||||
|
system.cpu.dcache.overall_hits::total 1973 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses
|
||||||
|
system.cpu.dcache.overall_misses::total 227 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7703250 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8679250 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency::total 8679250 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency::cpu.inst 16382500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency::total 16382500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency::cpu.inst 16382500 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency::total 16382500 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses::cpu.inst 1335 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses::cpu.inst 2200 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.demand_accesses::total 2200 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses::cpu.inst 2200 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses::total 2200 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076404 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate::total 0.076404 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate::cpu.inst 0.103182 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate::total 0.103182 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate::cpu.inst 0.103182 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69434 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 69434 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency::total 72169.603524 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency::total 72169.603524 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits
|
||||||
|
system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7131000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5128000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5128000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12259000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency::total 12259000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12259000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency::total 12259000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.071910 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076818 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.076818 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076818 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74281.250000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70246.575342 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70246.575342 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 176.176418 # Cycle average of tags in use
|
system.cpu.icache.tags.tagsinuse 176.126032 # Cycle average of tags in use
|
||||||
system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks.
|
system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
|
system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks.
|
system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.tags.occ_blocks::cpu.inst 176.176418 # Average occupied blocks per requestor
|
system.cpu.icache.tags.occ_blocks::cpu.inst 176.126032 # Average occupied blocks per requestor
|
||||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.086024 # Average percentage of cache occupancy
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.085999 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.tags.occ_percent::total 0.086024 # Average percentage of cache occupancy
|
system.cpu.icache.tags.occ_percent::total 0.085999 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
|
system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id
|
||||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
|
||||||
system.cpu.icache.tags.tag_accesses 5625 # Number of tag accesses
|
system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses
|
||||||
system.cpu.icache.tags.data_accesses 5625 # Number of data accesses
|
system.cpu.icache.tags.data_accesses 5649 # Number of data accesses
|
||||||
system.cpu.icache.ReadReq_hits::cpu.inst 2265 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits::cpu.inst 2277 # number of ReadReq hits
|
||||||
system.cpu.icache.ReadReq_hits::total 2265 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits::total 2277 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits::cpu.inst 2265 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits::cpu.inst 2277 # number of demand (read+write) hits
|
||||||
system.cpu.icache.demand_hits::total 2265 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits::total 2277 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits::cpu.inst 2265 # number of overall hits
|
system.cpu.icache.overall_hits::cpu.inst 2277 # number of overall hits
|
||||||
system.cpu.icache.overall_hits::total 2265 # number of overall hits
|
system.cpu.icache.overall_hits::total 2277 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses
|
||||||
system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
|
||||||
system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
|
system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
|
||||||
system.cpu.icache.overall_misses::total 365 # number of overall misses
|
system.cpu.icache.overall_misses::total 365 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25941750 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25915750 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.ReadReq_miss_latency::total 25941750 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency::total 25915750 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency::cpu.inst 25941750 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency::cpu.inst 25915750 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.demand_miss_latency::total 25941750 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency::total 25915750 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency::cpu.inst 25941750 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency::cpu.inst 25915750 # number of overall miss cycles
|
||||||
system.cpu.icache.overall_miss_latency::total 25941750 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency::total 25915750 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.demand_accesses::total 2630 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses::total 2642 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses::cpu.inst 2630 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses::cpu.inst 2642 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses::total 2630 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses::total 2642 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138783 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138153 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate::total 0.138783 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate::total 0.138153 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 # miss rate for demand accesses
|
||||||
system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses
|
||||||
system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71073.287671 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71002.054795 # average ReadReq miss latency
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::total 71073.287671 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency::total 71002.054795 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency::total 71073.287671 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency::total 71002.054795 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency::total 71073.287671 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency::total 71002.054795 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -383,25 +472,127 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365
|
||||||
system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25054250 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25028250 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 25054250 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 25028250 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25054250 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25028250 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency::total 25054250 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency::total 25028250 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25054250 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25028250 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency::total 25054250 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency::total 25028250 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68641.780822 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68570.547945 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68641.780822 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68570.547945 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.tags.tagsinuse 233.857006 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.857006 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses
|
||||||
|
system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses
|
||||||
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 460 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_misses::total 460 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::cpu.inst 73 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses::cpu.inst 533 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_misses::total 533 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31686750 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::total 31686750 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5053000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5053000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 36739750 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::total 36739750 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 36739750 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::total 36739750 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses::cpu.inst 534 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::cpu.inst 534 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997831 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68884.239130 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68884.239130 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69219.178082 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69219.178082 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::total 68930.112570 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::total 68930.112570 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 460 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 73 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25921750 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25921750 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30069250 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::total 30069250 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30069250 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::total 30069250 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56351.630435 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56351.630435 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||||
|
|
@ -430,219 +621,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 626250 # La
|
||||||
system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
|
system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
system.membus.trans_dist::ReadReq 460 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.tagsinuse 233.917543 # Cycle average of tags in use
|
system.membus.trans_dist::ReadResp 460 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks.
|
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||||
system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks.
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.917543 # Average occupied blocks per requestor
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007139 # Average percentage of cache occupancy
|
system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.l2cache.tags.occ_percent::total 0.007139 # Average percentage of cache occupancy
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id
|
system.membus.snoop_fanout::samples 533 # Request fanout histogram
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses
|
system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||||
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
system.membus.snoop_fanout::total 533 # Request fanout histogram
|
||||||
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks)
|
||||||
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 460 # number of ReadReq misses
|
system.membus.respLayer1.occupancy 4967250 # Layer occupancy (ticks)
|
||||||
system.cpu.l2cache.ReadReq_misses::total 460 # number of ReadReq misses
|
system.membus.respLayer1.utilization 14.2 # Layer utilization (%)
|
||||||
system.cpu.l2cache.ReadExReq_misses::cpu.inst 73 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.demand_misses::cpu.inst 533 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_misses::total 533 # number of overall misses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31726750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::total 31726750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5065000 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5065000 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 36791750 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::total 36791750 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 36791750 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::total 36791750 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.demand_accesses::cpu.inst 534 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::cpu.inst 534 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997831 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69383.561644 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69383.561644 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::total 69027.673546 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::total 69027.673546 # average overall miss latency
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 460 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 73 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25964750 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25964750 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30112250 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::total 30112250 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30112250 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::total 30112250 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
||||||
system.cpu.dcache.tags.tagsinuse 104.075920 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 104.075920 # Average occupied blocks per requestor
|
|
||||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.025409 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.tags.occ_percent::total 0.025409 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
|
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
|
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
|
|
||||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.dcache.tags.tag_accesses 4559 # Number of tag accesses
|
|
||||||
system.cpu.dcache.tags.data_accesses 4559 # Number of data accesses
|
|
||||||
system.cpu.dcache.ReadReq_hits::cpu.inst 1228 # number of ReadReq hits
|
|
||||||
system.cpu.dcache.ReadReq_hits::total 1228 # number of ReadReq hits
|
|
||||||
system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.demand_hits::cpu.inst 1968 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_hits::total 1968 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.overall_hits::cpu.inst 1968 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_hits::total 1968 # number of overall hits
|
|
||||||
system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_misses::total 227 # number of overall misses
|
|
||||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7718250 # number of ReadReq miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_miss_latency::total 7718250 # number of ReadReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8705750 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency::total 8705750 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_latency::total 16424000 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 1330 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.ReadReq_accesses::total 1330 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_accesses::total 2195 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_accesses::total 2195 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076692 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_miss_rate::total 0.076692 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647 # average ReadReq miss latency
|
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647 # average ReadReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69646 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 69646 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency::total 72352.422907 # average overall miss latency
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits
|
|
||||||
system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7145500 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7145500 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5139500 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5139500 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::total 12285000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.072180 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.072180 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,13 +1,13 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.000019 # Number of seconds simulated
|
sim_seconds 0.000019 # Number of seconds simulated
|
||||||
sim_ticks 18662000 # Number of ticks simulated
|
sim_ticks 18733500 # Number of ticks simulated
|
||||||
final_tick 18662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 40123 # Simulator instruction rate (inst/s)
|
host_inst_rate 41421 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 40110 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 41407 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 289474844 # Simulator tick rate (ticks/s)
|
host_tick_rate 299977624 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 234892 # Number of bytes of host memory used
|
host_mem_usage 235900 # Number of bytes of host memory used
|
||||||
host_seconds 0.06 # Real time elapsed on the host
|
host_seconds 0.06 # Real time elapsed on the host
|
||||||
sim_insts 2585 # Number of instructions simulated
|
sim_insts 2585 # Number of instructions simulated
|
||||||
sim_ops 2585 # Number of ops (including micro ops) simulated
|
sim_ops 2585 # Number of ops (including micro ops) simulated
|
||||||
|
|
@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 14272 # Nu
|
||||||
system.physmem.bytes_inst_read::total 14272 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::total 14272 # Number of instructions bytes read from this memory
|
||||||
system.physmem.num_reads::cpu.inst 308 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.inst 308 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::total 308 # Number of read requests responded to by this memory
|
system.physmem.num_reads::total 308 # Number of read requests responded to by this memory
|
||||||
system.physmem.bw_read::cpu.inst 1056264066 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.inst 1052232631 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::total 1056264066 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::total 1052232631 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu.inst 764762619 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu.inst 761843756 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::total 764762619 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::total 761843756 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.inst 1056264066 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 1052232631 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 1056264066 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 1052232631 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.readReqs 308 # Number of read requests accepted
|
system.physmem.readReqs 308 # Number of read requests accepted
|
||||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||||
system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue
|
system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue
|
||||||
|
|
@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
||||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||||
system.physmem.totGap 18580000 # Total gap between requests
|
system.physmem.totGap 18651500 # Total gap between requests
|
||||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||||
|
|
@ -182,118 +182,95 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
||||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||||
system.physmem.bytesPerActivate::samples 44 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::samples 43 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::mean 411.636364 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::mean 421.209302 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::gmean 270.438338 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::gmean 281.192017 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::stdev 322.932860 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::stdev 321.893842 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::0-127 11 25.00% 25.00% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::0-127 10 23.26% 23.26% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::128-255 7 15.91% 40.91% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::128-255 8 18.60% 41.86% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::256-383 4 9.09% 50.00% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::256-383 3 6.98% 48.84% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::384-511 3 6.82% 56.82% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::384-511 3 6.98% 55.81% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::512-639 6 13.64% 70.45% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::512-639 6 13.95% 69.77% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::640-767 5 11.36% 81.82% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::640-767 4 9.30% 79.07% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::768-895 3 6.82% 88.64% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::768-895 4 9.30% 88.37% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::896-1023 1 2.27% 90.91% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::896-1023 2 4.65% 93.02% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::1024-1151 4 9.09% 100.00% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::1024-1151 3 6.98% 100.00% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::total 44 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::total 43 # Bytes accessed per row activation
|
||||||
system.physmem.totQLat 1719250 # Total ticks spent queuing
|
system.physmem.totQLat 1958750 # Total ticks spent queuing
|
||||||
system.physmem.totMemAccLat 7494250 # Total ticks spent from burst creation until serviced by the DRAM
|
system.physmem.totMemAccLat 7733750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||||
system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers
|
system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers
|
||||||
system.physmem.avgQLat 5581.98 # Average queueing delay per DRAM burst
|
system.physmem.avgQLat 6359.58 # Average queueing delay per DRAM burst
|
||||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||||
system.physmem.avgMemAccLat 24331.98 # Average memory access latency per DRAM burst
|
system.physmem.avgMemAccLat 25109.58 # Average memory access latency per DRAM burst
|
||||||
system.physmem.avgRdBW 1056.26 # Average DRAM read bandwidth in MiByte/s
|
system.physmem.avgRdBW 1052.23 # Average DRAM read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||||
system.physmem.avgRdBWSys 1056.26 # Average system read bandwidth in MiByte/s
|
system.physmem.avgRdBWSys 1052.23 # Average system read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||||
system.physmem.busUtil 8.25 # Data bus utilization in percentage
|
system.physmem.busUtil 8.22 # Data bus utilization in percentage
|
||||||
system.physmem.busUtilRead 8.25 # Data bus utilization in percentage for reads
|
system.physmem.busUtilRead 8.22 # Data bus utilization in percentage for reads
|
||||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||||
system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing
|
system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing
|
||||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||||
system.physmem.readRowHits 256 # Number of row buffer hits during reads
|
system.physmem.readRowHits 257 # Number of row buffer hits during reads
|
||||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||||
system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads
|
system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads
|
||||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||||
system.physmem.avgGap 60324.68 # Average gap between requests
|
system.physmem.avgGap 60556.82 # Average gap between requests
|
||||||
system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined
|
system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined
|
||||||
system.physmem.memoryStateTime::IDLE 15500 # Time in different power states
|
system.physmem.memoryStateTime::IDLE 15500 # Time in different power states
|
||||||
system.physmem.memoryStateTime::REF 520000 # Time in different power states
|
system.physmem.memoryStateTime::REF 520000 # Time in different power states
|
||||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT 15310750 # Time in different power states
|
system.physmem.memoryStateTime::ACT 15310750 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||||
system.physmem.actEnergy::0 90720 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::0 83160 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem.actEnergy::1 219240 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::1 219240 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem.preEnergy::0 49500 # Energy for precharge commands per rank (pJ)
|
system.physmem.preEnergy::0 45375 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem.preEnergy::1 119625 # Energy for precharge commands per rank (pJ)
|
system.physmem.preEnergy::1 119625 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem.readEnergy::0 795600 # Energy for read commands per rank (pJ)
|
system.physmem.readEnergy::0 795600 # Energy for read commands per rank (pJ)
|
||||||
system.physmem.readEnergy::1 1302600 # Energy for read commands per rank (pJ)
|
system.physmem.readEnergy::1 1294800 # Energy for read commands per rank (pJ)
|
||||||
system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
||||||
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
|
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
|
||||||
system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.actBackEnergy::0 10733670 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::0 10790100 # Energy for active background per rank (pJ)
|
||||||
system.physmem.actBackEnergy::1 10507095 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::1 10507095 # Energy for active background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::0 84000 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::0 34500 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::1 282750 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::1 282750 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.totalEnergy::0 12770610 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::0 12765855 # Total energy per rank (pJ)
|
||||||
system.physmem.totalEnergy::1 13448430 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::1 13440630 # Total energy per rank (pJ)
|
||||||
system.physmem.averagePower::0 806.607295 # Core power per rank (mW)
|
system.physmem.averagePower::0 806.306964 # Core power per rank (mW)
|
||||||
system.physmem.averagePower::1 849.419233 # Core power per rank (mW)
|
system.physmem.averagePower::1 848.926575 # Core power per rank (mW)
|
||||||
system.membus.trans_dist::ReadReq 281 # Transaction distribution
|
system.cpu.branchPred.lookups 793 # Number of BP lookups
|
||||||
system.membus.trans_dist::ReadResp 281 # Transaction distribution
|
system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted
|
||||||
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
|
|
||||||
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
|
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 308 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 308 # Request fanout histogram
|
|
||||||
system.membus.reqLayer0.occupancy 362000 # Layer occupancy (ticks)
|
|
||||||
system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
|
|
||||||
system.membus.respLayer1.occupancy 2870500 # Layer occupancy (ticks)
|
|
||||||
system.membus.respLayer1.utilization 15.4 # Layer utilization (%)
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
||||||
system.cpu.branchPred.lookups 786 # Number of BP lookups
|
|
||||||
system.cpu.branchPred.condPredicted 393 # Number of conditional branches predicted
|
|
||||||
system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect
|
system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect
|
||||||
system.cpu.branchPred.BTBLookups 558 # Number of BTB lookups
|
system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups
|
||||||
system.cpu.branchPred.BTBHits 58 # Number of BTB hits
|
system.cpu.branchPred.BTBHits 58 # Number of BTB hits
|
||||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.branchPred.BTBHitPct 10.394265 # BTB Hit Percentage
|
system.cpu.branchPred.BTBHitPct 10.320285 # BTB Hit Percentage
|
||||||
system.cpu.branchPred.usedRAS 139 # Number of times the RAS was used to get a target.
|
system.cpu.branchPred.usedRAS 139 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions.
|
system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions.
|
||||||
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 508 # DTB read hits
|
system.cpu.dtb.read_hits 509 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||||
system.cpu.dtb.read_acv 1 # DTB read access violations
|
system.cpu.dtb.read_acv 1 # DTB read access violations
|
||||||
system.cpu.dtb.read_accesses 515 # DTB read accesses
|
system.cpu.dtb.read_accesses 516 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 307 # DTB write hits
|
system.cpu.dtb.write_hits 307 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 6 # DTB write misses
|
system.cpu.dtb.write_misses 6 # DTB write misses
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.dtb.write_accesses 313 # DTB write accesses
|
system.cpu.dtb.write_accesses 313 # DTB write accesses
|
||||||
system.cpu.dtb.data_hits 815 # DTB hits
|
system.cpu.dtb.data_hits 816 # DTB hits
|
||||||
system.cpu.dtb.data_misses 13 # DTB misses
|
system.cpu.dtb.data_misses 13 # DTB misses
|
||||||
system.cpu.dtb.data_acv 1 # DTB access violations
|
system.cpu.dtb.data_acv 1 # DTB access violations
|
||||||
system.cpu.dtb.data_accesses 828 # DTB accesses
|
system.cpu.dtb.data_accesses 829 # DTB accesses
|
||||||
system.cpu.itb.fetch_hits 962 # ITB hits
|
system.cpu.itb.fetch_hits 974 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 13 # ITB misses
|
system.cpu.itb.fetch_misses 13 # ITB misses
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.fetch_accesses 975 # ITB accesses
|
system.cpu.itb.fetch_accesses 987 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
|
|
@ -307,248 +284,40 @@ system.cpu.itb.data_misses 0 # DT
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||||
system.cpu.numCycles 37324 # number of cpu cycles simulated
|
system.cpu.numCycles 37467 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.committedInsts 2585 # Number of instructions committed
|
system.cpu.committedInsts 2585 # Number of instructions committed
|
||||||
system.cpu.committedOps 2585 # Number of ops (including micro ops) committed
|
system.cpu.committedOps 2585 # Number of ops (including micro ops) committed
|
||||||
system.cpu.discardedOps 635 # Number of ops (including micro ops) which were discarded before commit
|
system.cpu.discardedOps 596 # Number of ops (including micro ops) which were discarded before commit
|
||||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||||
system.cpu.cpi 14.438685 # CPI: cycles per instruction
|
system.cpu.cpi 14.494004 # CPI: cycles per instruction
|
||||||
system.cpu.ipc 0.069258 # IPC: instructions per cycle
|
system.cpu.ipc 0.068994 # IPC: instructions per cycle
|
||||||
system.cpu.tickCycles 5337 # Number of cycles that the object actually ticked
|
system.cpu.tickCycles 5412 # Number of cycles that the object actually ticked
|
||||||
system.cpu.idleCycles 31987 # Total number of cycles that the object has spent stopped
|
system.cpu.idleCycles 32055 # Total number of cycles that the object has spent stopped
|
||||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
|
||||||
system.cpu.icache.tags.tagsinuse 118.813999 # Cycle average of tags in use
|
|
||||||
system.cpu.icache.tags.total_refs 739 # Total number of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.avg_refs 3.313901 # Average number of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.icache.tags.occ_blocks::cpu.inst 118.813999 # Average occupied blocks per requestor
|
|
||||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.058015 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.tags.occ_percent::total 0.058015 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.icache.tags.tag_accesses 2147 # Number of tag accesses
|
|
||||||
system.cpu.icache.tags.data_accesses 2147 # Number of data accesses
|
|
||||||
system.cpu.icache.ReadReq_hits::cpu.inst 739 # number of ReadReq hits
|
|
||||||
system.cpu.icache.ReadReq_hits::total 739 # number of ReadReq hits
|
|
||||||
system.cpu.icache.demand_hits::cpu.inst 739 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.demand_hits::total 739 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.overall_hits::cpu.inst 739 # number of overall hits
|
|
||||||
system.cpu.icache.overall_hits::total 739 # number of overall hits
|
|
||||||
system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses
|
|
||||||
system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses
|
|
||||||
system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses
|
|
||||||
system.cpu.icache.overall_misses::total 223 # number of overall misses
|
|
||||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15454750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.icache.ReadReq_miss_latency::total 15454750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.icache.demand_miss_latency::cpu.inst 15454750 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.demand_miss_latency::total 15454750 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.overall_miss_latency::cpu.inst 15454750 # number of overall miss cycles
|
|
||||||
system.cpu.icache.overall_miss_latency::total 15454750 # number of overall miss cycles
|
|
||||||
system.cpu.icache.ReadReq_accesses::cpu.inst 962 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.icache.ReadReq_accesses::total 962 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.icache.demand_accesses::cpu.inst 962 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.demand_accesses::total 962 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.overall_accesses::cpu.inst 962 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.overall_accesses::total 962 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.231809 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_miss_rate::total 0.231809 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.231809 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_miss_rate::total 0.231809 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.231809 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_miss_rate::total 0.231809 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69303.811659 # average ReadReq miss latency
|
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69303.811659 # average ReadReq miss latency
|
|
||||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69303.811659 # average overall miss latency
|
|
||||||
system.cpu.icache.demand_avg_miss_latency::total 69303.811659 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69303.811659 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_miss_latency::total 69303.811659 # average overall miss latency
|
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 223 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.demand_mshr_misses::cpu.inst 223 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14914250 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14914250 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14914250 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency::total 14914250 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14914250 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency::total 14914250 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231809 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231809 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231809 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate::total 0.231809 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231809 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate::total 0.231809 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66880.044843 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66880.044843 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66880.044843 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66880.044843 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66880.044843 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66880.044843 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer0.occupancy 381750 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer1.occupancy 136250 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
|
||||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
||||||
system.cpu.l2cache.tags.tagsinuse 146.987026 # Cycle average of tags in use
|
|
||||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.987026 # Average occupied blocks per requestor
|
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004486 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_percent::total 0.004486 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses
|
|
||||||
system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses
|
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses
|
|
||||||
system.cpu.l2cache.ReadReq_misses::total 281 # number of ReadReq misses
|
|
||||||
system.cpu.l2cache.ReadExReq_misses::cpu.inst 27 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.demand_misses::cpu.inst 308 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_misses::total 308 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.overall_misses::cpu.inst 308 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_misses::total 308 # number of overall misses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18929750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::total 18929750 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 1803250 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1803250 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20733000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::total 20733000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20733000 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::total 20733000 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 281 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 27 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.demand_accesses::cpu.inst 308 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_accesses::total 308 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::cpu.inst 308 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::total 308 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67365.658363 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67365.658363 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66787.037037 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66787.037037 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67314.935065 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::total 67314.935065 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67314.935065 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::total 67314.935065 # average overall miss latency
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 27 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 308 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::total 308 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 308 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15410750 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15410750 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1471750 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1471750 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16882500 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16882500 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16882500 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16882500 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54842.526690 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54842.526690 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54509.259259 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54509.259259 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54813.311688 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54813.311688 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54813.311688 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54813.311688 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||||
system.cpu.dcache.tags.tagsinuse 48.699994 # Cycle average of tags in use
|
system.cpu.dcache.tags.tagsinuse 48.468521 # Cycle average of tags in use
|
||||||
system.cpu.dcache.tags.total_refs 687 # Total number of references to valid blocks.
|
system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
|
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.tags.avg_refs 8.082353 # Average number of references to valid blocks.
|
system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 48.699994 # Average occupied blocks per requestor
|
system.cpu.dcache.tags.occ_blocks::cpu.inst 48.468521 # Average occupied blocks per requestor
|
||||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.011890 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::cpu.inst 0.011833 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.tags.occ_percent::total 0.011890 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::total 0.011833 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
|
||||||
system.cpu.dcache.tags.tag_accesses 1667 # Number of tag accesses
|
system.cpu.dcache.tags.tag_accesses 1677 # Number of tag accesses
|
||||||
system.cpu.dcache.tags.data_accesses 1667 # Number of data accesses
|
system.cpu.dcache.tags.data_accesses 1677 # Number of data accesses
|
||||||
system.cpu.dcache.ReadReq_hits::cpu.inst 436 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::cpu.inst 441 # number of ReadReq hits
|
||||||
system.cpu.dcache.ReadReq_hits::total 436 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::cpu.inst 251 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::cpu.inst 251 # number of WriteReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits
|
||||||
system.cpu.dcache.demand_hits::cpu.inst 687 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::cpu.inst 692 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.demand_hits::total 687 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::total 692 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits::cpu.inst 687 # number of overall hits
|
system.cpu.dcache.overall_hits::cpu.inst 692 # number of overall hits
|
||||||
system.cpu.dcache.overall_hits::total 687 # number of overall hits
|
system.cpu.dcache.overall_hits::total 692 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses::cpu.inst 61 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::cpu.inst 61 # number of ReadReq misses
|
||||||
system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses::cpu.inst 43 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses::cpu.inst 43 # number of WriteReq misses
|
||||||
|
|
@ -557,38 +326,38 @@ system.cpu.dcache.demand_misses::cpu.inst 104 # n
|
||||||
system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses::cpu.inst 104 # number of overall misses
|
system.cpu.dcache.overall_misses::cpu.inst 104 # number of overall misses
|
||||||
system.cpu.dcache.overall_misses::total 104 # number of overall misses
|
system.cpu.dcache.overall_misses::total 104 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4631500 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4636500 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_latency::total 4631500 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::total 4636500 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3005500 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3517500 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::total 3005500 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::total 3517500 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::cpu.inst 7637000 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::cpu.inst 8154000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::total 7637000 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::total 8154000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::cpu.inst 7637000 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::cpu.inst 8154000 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::total 7637000 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::total 8154000 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 497 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::cpu.inst 502 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_accesses::total 497 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 294 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::cpu.inst 294 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses::cpu.inst 791 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::cpu.inst 796 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.demand_accesses::total 791 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::total 796 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::cpu.inst 791 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::cpu.inst 796 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::total 791 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::total 796 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.122736 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.121514 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::total 0.122736 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::total 0.121514 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.146259 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.146259 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate::cpu.inst 0.131479 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate::cpu.inst 0.130653 # miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_miss_rate::total 0.131479 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.131479 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::cpu.inst 0.130653 # miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.131479 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75926.229508 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76008.196721 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75926.229508 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 76008.196721 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69895.348837 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81802.325581 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 69895.348837 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 81802.325581 # average WriteReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 73432.692308 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::total 73432.692308 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::total 78403.846154 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 73432.692308 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::total 73432.692308 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::total 78403.846154 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -613,30 +382,261 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 85
|
||||||
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 85 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.inst 85 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4297000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4302500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4297000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4302500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1830750 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2086500 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1830750 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2086500 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6127750 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6389000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::total 6127750 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::total 6389000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6127750 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6389000 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::total 6127750 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::total 6389000 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.116700 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.115538 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116700 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.091837 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.091837 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.107459 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.106784 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.107459 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.107459 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.106784 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.107459 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74086.206897 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74181.034483 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74086.206897 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74181.034483 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67805.555556 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77277.777778 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67805.555556 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77277.777778 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72091.176471 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72091.176471 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72091.176471 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72091.176471 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||||
|
system.cpu.icache.tags.tagsinuse 118.426247 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.tags.total_refs 751 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.avg_refs 3.367713 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.tags.occ_blocks::cpu.inst 118.426247 # Average occupied blocks per requestor
|
||||||
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.057825 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_percent::total 0.057825 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.icache.tags.tag_accesses 2171 # Number of tag accesses
|
||||||
|
system.cpu.icache.tags.data_accesses 2171 # Number of data accesses
|
||||||
|
system.cpu.icache.ReadReq_hits::cpu.inst 751 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_hits::total 751 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits::cpu.inst 751 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_hits::total 751 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits::cpu.inst 751 # number of overall hits
|
||||||
|
system.cpu.icache.overall_hits::total 751 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses
|
||||||
|
system.cpu.icache.overall_misses::total 223 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15431500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.ReadReq_miss_latency::total 15431500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency::cpu.inst 15431500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency::total 15431500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency::cpu.inst 15431500 # number of overall miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency::total 15431500 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses::cpu.inst 974 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_accesses::total 974 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses::cpu.inst 974 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_accesses::total 974 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::cpu.inst 974 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::total 974 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69199.551570 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency::total 69199.551570 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69199.551570 # average overall miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency::total 69199.551570 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69199.551570 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency::total 69199.551570 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 223 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses::cpu.inst 223 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14892500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 14892500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14892500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency::total 14892500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14892500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency::total 14892500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.228953 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate::total 0.228953 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate::total 0.228953 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66782.511211 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66782.511211 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66782.511211 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 66782.511211 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66782.511211 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 66782.511211 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.tags.tagsinuse 146.486275 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.486275 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004470 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::total 0.004470 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses
|
||||||
|
system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses
|
||||||
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_misses::total 281 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::cpu.inst 27 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses::cpu.inst 308 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_misses::total 308 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses::cpu.inst 308 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_misses::total 308 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18913000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::total 18913000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2059500 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2059500 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 20972500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::total 20972500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 20972500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::total 20972500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 281 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 27 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses::cpu.inst 308 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_accesses::total 308 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::cpu.inst 308 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::total 308 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67306.049822 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76277.777778 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76277.777778 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68092.532468 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::total 68092.532468 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68092.532468 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::total 68092.532468 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 27 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 308 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::total 308 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 308 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15398500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15398500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1725500 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1725500 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17124000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::total 17124000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17124000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::total 17124000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.932384 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63907.407407 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63907.407407 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55597.402597 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55597.402597 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55597.402597 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55597.402597 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||||
|
system.cpu.toL2Bus.respLayer0.occupancy 381000 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
|
||||||
|
system.cpu.toL2Bus.respLayer1.occupancy 137000 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||||
|
system.membus.trans_dist::ReadReq 281 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadResp 281 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||||
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
|
system.membus.snoop_fanout::samples 308 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::total 308 # Request fanout histogram
|
||||||
|
system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks)
|
||||||
|
system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
|
||||||
|
system.membus.respLayer1.occupancy 2868500 # Layer occupancy (ticks)
|
||||||
|
system.membus.respLayer1.utilization 15.3 # Layer utilization (%)
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,47 +1,47 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.000028 # Number of seconds simulated
|
sim_seconds 0.000028 # Number of seconds simulated
|
||||||
sim_ticks 27911000 # Number of ticks simulated
|
sim_ticks 27981000 # Number of ticks simulated
|
||||||
final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 3437 # Simulator instruction rate (inst/s)
|
host_inst_rate 65720 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 4023 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 76928 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 20833659 # Simulator tick rate (ticks/s)
|
host_tick_rate 399296424 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 251612 # Number of bytes of host memory used
|
host_mem_usage 250660 # Number of bytes of host memory used
|
||||||
host_seconds 1.34 # Real time elapsed on the host
|
host_seconds 0.07 # Real time elapsed on the host
|
||||||
sim_insts 4604 # Number of instructions simulated
|
sim_insts 4604 # Number of instructions simulated
|
||||||
sim_ops 5390 # Number of ops (including micro ops) simulated
|
sim_ops 5390 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
system.clk_domain.clock 1000 # Clock period in ticks
|
system.clk_domain.clock 1000 # Clock period in ticks
|
||||||
system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.inst 26944 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::total 26880 # Number of bytes read from this memory
|
system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
|
||||||
system.physmem.num_reads::cpu.inst 420 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.inst 421 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::total 420 # Number of read requests responded to by this memory
|
system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
|
||||||
system.physmem.bw_read::cpu.inst 963061159 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.inst 962939137 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::total 963061159 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu.inst 697072839 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::total 697072839 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.inst 963061159 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 962939137 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 963061159 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.readReqs 420 # Number of read requests accepted
|
system.physmem.readReqs 421 # Number of read requests accepted
|
||||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||||
system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue
|
system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
|
||||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||||
system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM
|
system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM
|
||||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||||
system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side
|
system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side
|
||||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||||
system.physmem.perBankRdBursts::0 91 # Per bank write bursts
|
system.physmem.perBankRdBursts::0 91 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::1 51 # Per bank write bursts
|
system.physmem.perBankRdBursts::1 52 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::2 20 # Per bank write bursts
|
system.physmem.perBankRdBursts::2 20 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::3 42 # Per bank write bursts
|
system.physmem.perBankRdBursts::3 43 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::4 23 # Per bank write bursts
|
system.physmem.perBankRdBursts::4 22 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::5 41 # Per bank write bursts
|
system.physmem.perBankRdBursts::5 41 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::6 36 # Per bank write bursts
|
system.physmem.perBankRdBursts::6 36 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::7 12 # Per bank write bursts
|
system.physmem.perBankRdBursts::7 12 # Per bank write bursts
|
||||||
|
|
@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
||||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||||
system.physmem.totGap 27825500 # Total gap between requests
|
system.physmem.totGap 27895500 # Total gap between requests
|
||||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::6 420 # Read request sizes (log2)
|
system.physmem.readPktSize::6 421 # Read request sizes (log2)
|
||||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||||
|
|
@ -87,7 +87,7 @@ system.physmem.writePktSize::4 0 # Wr
|
||||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||||
system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||||
|
|
@ -182,28 +182,28 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
||||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||||
system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::mean 396 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::mean 403.301587 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::gmean 274.035894 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::gmean 282.308639 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::stdev 327.902425 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::stdev 327.677686 # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::0-127 10 15.62% 15.62% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::0-127 9 14.29% 14.29% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::128-255 17 26.56% 42.19% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::128-255 16 25.40% 39.68% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::256-383 12 18.75% 60.94% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::256-383 13 20.63% 60.32% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::384-511 7 10.94% 71.88% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::512-639 3 4.69% 76.56% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::640-767 2 3.12% 79.69% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation
|
||||||
system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation
|
system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
|
||||||
system.physmem.totQLat 2575500 # Total ticks spent queuing
|
system.physmem.totQLat 2478000 # Total ticks spent queuing
|
||||||
system.physmem.totMemAccLat 10450500 # Total ticks spent from burst creation until serviced by the DRAM
|
system.physmem.totMemAccLat 10371750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||||
system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers
|
system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
|
||||||
system.physmem.avgQLat 6132.14 # Average queueing delay per DRAM burst
|
system.physmem.avgQLat 5885.99 # Average queueing delay per DRAM burst
|
||||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||||
system.physmem.avgMemAccLat 24882.14 # Average memory access latency per DRAM burst
|
system.physmem.avgMemAccLat 24635.99 # Average memory access latency per DRAM burst
|
||||||
system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s
|
system.physmem.avgRdBW 962.94 # Average DRAM read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||||
system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s
|
system.physmem.avgRdBWSys 962.94 # Average system read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||||
system.physmem.busUtil 7.52 # Data bus utilization in percentage
|
system.physmem.busUtil 7.52 # Data bus utilization in percentage
|
||||||
|
|
@ -211,20 +211,20 @@ system.physmem.busUtilRead 7.52 # Da
|
||||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||||
system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
|
system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
|
||||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||||
system.physmem.readRowHits 348 # Number of row buffer hits during reads
|
system.physmem.readRowHits 350 # Number of row buffer hits during reads
|
||||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||||
system.physmem.readRowHitRate 82.86 # Row buffer hit rate for reads
|
system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
|
||||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||||
system.physmem.avgGap 66251.19 # Average gap between requests
|
system.physmem.avgGap 66260.10 # Average gap between requests
|
||||||
system.physmem.pageHitRate 82.86 # Row buffer hit rate, read and write combined
|
system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
|
||||||
system.physmem.memoryStateTime::IDLE 12000 # Time in different power states
|
system.physmem.memoryStateTime::IDLE 12000 # Time in different power states
|
||||||
system.physmem.memoryStateTime::REF 780000 # Time in different power states
|
system.physmem.memoryStateTime::REF 780000 # Time in different power states
|
||||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT 22840500 # Time in different power states
|
system.physmem.memoryStateTime::ACT 22840500 # Time in different power states
|
||||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||||
system.physmem.actEnergy::0 302400 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem.actEnergy::1 136080 # Energy for activate commands per rank (pJ)
|
system.physmem.actEnergy::1 136080 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem.preEnergy::0 165000 # Energy for precharge commands per rank (pJ)
|
system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem.preEnergy::1 74250 # Energy for precharge commands per rank (pJ)
|
system.physmem.preEnergy::1 74250 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem.readEnergy::0 2090400 # Energy for read commands per rank (pJ)
|
system.physmem.readEnergy::0 2090400 # Energy for read commands per rank (pJ)
|
||||||
system.physmem.readEnergy::1 702000 # Energy for read commands per rank (pJ)
|
system.physmem.readEnergy::1 702000 # Energy for read commands per rank (pJ)
|
||||||
|
|
@ -232,47 +232,24 @@ system.physmem.writeEnergy::0 0 # En
|
||||||
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
|
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
|
||||||
system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ)
|
system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem.actBackEnergy::0 16015860 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::0 16099650 # Energy for active background per rank (pJ)
|
||||||
system.physmem.actBackEnergy::1 16042365 # Energy for active background per rank (pJ)
|
system.physmem.actBackEnergy::1 15972255 # Energy for active background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::0 122250 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::0 48750 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.preBackEnergy::1 99000 # Energy for precharge background per rank (pJ)
|
system.physmem.preBackEnergy::1 160500 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem.totalEnergy::0 20221590 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::0 20220195 # Total energy per rank (pJ)
|
||||||
system.physmem.totalEnergy::1 18579375 # Total energy per rank (pJ)
|
system.physmem.totalEnergy::1 18570765 # Total energy per rank (pJ)
|
||||||
system.physmem.averagePower::0 856.166817 # Core power per rank (mW)
|
system.physmem.averagePower::0 856.107753 # Core power per rank (mW)
|
||||||
system.physmem.averagePower::1 786.636676 # Core power per rank (mW)
|
system.physmem.averagePower::1 786.272135 # Core power per rank (mW)
|
||||||
system.membus.trans_dist::ReadReq 377 # Transaction distribution
|
system.cpu.branchPred.lookups 1926 # Number of BP lookups
|
||||||
system.membus.trans_dist::ReadResp 377 # Transaction distribution
|
system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted
|
||||||
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
|
|
||||||
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
|
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 420 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 420 # Request fanout histogram
|
|
||||||
system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
|
|
||||||
system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
|
|
||||||
system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks)
|
|
||||||
system.membus.respLayer1.utilization 14.1 # Layer utilization (%)
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
||||||
system.cpu.branchPred.lookups 1903 # Number of BP lookups
|
|
||||||
system.cpu.branchPred.condPredicted 1138 # Number of conditional branches predicted
|
|
||||||
system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect
|
system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect
|
||||||
system.cpu.branchPred.BTBLookups 1573 # Number of BTB lookups
|
system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups
|
||||||
system.cpu.branchPred.BTBHits 325 # Number of BTB hits
|
system.cpu.branchPred.BTBHits 326 # Number of BTB hits
|
||||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.branchPred.BTBHitPct 20.661157 # BTB Hit Percentage
|
system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage
|
||||||
system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
|
system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
|
system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
|
||||||
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||||
|
|
@ -358,268 +335,44 @@ system.cpu.itb.hits 0 # DT
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||||
system.cpu.numCycles 55822 # number of cpu cycles simulated
|
system.cpu.numCycles 55962 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.committedInsts 4604 # Number of instructions committed
|
system.cpu.committedInsts 4604 # Number of instructions committed
|
||||||
system.cpu.committedOps 5390 # Number of ops (including micro ops) committed
|
system.cpu.committedOps 5390 # Number of ops (including micro ops) committed
|
||||||
system.cpu.discardedOps 1208 # Number of ops (including micro ops) which were discarded before commit
|
system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit
|
||||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||||
system.cpu.cpi 12.124674 # CPI: cycles per instruction
|
system.cpu.cpi 12.155083 # CPI: cycles per instruction
|
||||||
system.cpu.ipc 0.082476 # IPC: instructions per cycle
|
system.cpu.ipc 0.082270 # IPC: instructions per cycle
|
||||||
system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked
|
system.cpu.tickCycles 10640 # Number of cycles that the object actually ticked
|
||||||
system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped
|
system.cpu.idleCycles 45322 # Total number of cycles that the object has spent stopped
|
||||||
system.cpu.icache.tags.replacements 3 # number of replacements
|
|
||||||
system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use
|
|
||||||
system.cpu.icache.tags.total_refs 1918 # Total number of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.avg_refs 5.975078 # Average number of references to valid blocks.
|
|
||||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor
|
|
||||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id
|
|
||||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.icache.tags.tag_accesses 4799 # Number of tag accesses
|
|
||||||
system.cpu.icache.tags.data_accesses 4799 # Number of data accesses
|
|
||||||
system.cpu.icache.ReadReq_hits::cpu.inst 1918 # number of ReadReq hits
|
|
||||||
system.cpu.icache.ReadReq_hits::total 1918 # number of ReadReq hits
|
|
||||||
system.cpu.icache.demand_hits::cpu.inst 1918 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.demand_hits::total 1918 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.overall_hits::cpu.inst 1918 # number of overall hits
|
|
||||||
system.cpu.icache.overall_hits::total 1918 # number of overall hits
|
|
||||||
system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses
|
|
||||||
system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses
|
|
||||||
system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses
|
|
||||||
system.cpu.icache.overall_misses::total 321 # number of overall misses
|
|
||||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles
|
|
||||||
system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles
|
|
||||||
system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles
|
|
||||||
system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles
|
|
||||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2239 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.icache.ReadReq_accesses::total 2239 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.icache.demand_accesses::cpu.inst 2239 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.demand_accesses::total 2239 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.overall_accesses::cpu.inst 2239 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.overall_accesses::total 2239 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143368 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_miss_rate::total 0.143368 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.143368 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_miss_rate::total 0.143368 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.143368 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_miss_rate::total 0.143368 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency
|
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency
|
|
||||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
|
|
||||||
system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency
|
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143368 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate::total 0.143368 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate::total 0.143368 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::5 467 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 233500 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer0.occupancy 546750 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
|
|
||||||
system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
|
|
||||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
|
||||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
||||||
system.cpu.l2cache.tags.tagsinuse 195.957604 # Cycle average of tags in use
|
|
||||||
system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.avg_refs 0.103448 # Average number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.957604 # Average occupied blocks per requestor
|
|
||||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005980 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_percent::total 0.005980 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
|
|
||||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id
|
|
||||||
system.cpu.l2cache.tags.tag_accesses 4156 # Number of tag accesses
|
|
||||||
system.cpu.l2cache.tags.data_accesses 4156 # Number of data accesses
|
|
||||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits
|
|
||||||
system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
|
|
||||||
system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits
|
|
||||||
system.cpu.l2cache.overall_hits::total 39 # number of overall hits
|
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses
|
|
||||||
system.cpu.l2cache.ReadReq_misses::total 385 # number of ReadReq misses
|
|
||||||
system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
|
|
||||||
system.cpu.l2cache.demand_misses::cpu.inst 428 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.overall_misses::cpu.inst 428 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_misses::total 428 # number of overall misses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26169000 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::total 26169000 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2824000 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2824000 # number of ReadExReq miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 28993000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_latency::total 28993000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 28993000 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_latency::total 28993000 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 424 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.demand_accesses::cpu.inst 467 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::cpu.inst 467 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908019 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.908019 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916488 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916488 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605 # average ReadExReq miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206 # average overall miss latency
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20974000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20974000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23258000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::total 23258000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23258000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::total 23258000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889151 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889151 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070 # average ReadExReq mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||||
system.cpu.dcache.tags.tagsinuse 86.665340 # Cycle average of tags in use
|
system.cpu.dcache.tags.tagsinuse 86.669090 # Cycle average of tags in use
|
||||||
system.cpu.dcache.tags.total_refs 1919 # Total number of references to valid blocks.
|
system.cpu.dcache.tags.total_refs 1922 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks.
|
system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 86.665340 # Average occupied blocks per requestor
|
system.cpu.dcache.tags.occ_blocks::cpu.inst 86.669090 # Average occupied blocks per requestor
|
||||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy
|
system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
|
||||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
|
||||||
system.cpu.dcache.tags.tag_accesses 4348 # Number of tag accesses
|
system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses
|
||||||
system.cpu.dcache.tags.data_accesses 4348 # Number of data accesses
|
system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses
|
||||||
system.cpu.dcache.ReadReq_hits::cpu.inst 1051 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::cpu.inst 1054 # number of ReadReq hits
|
||||||
system.cpu.dcache.ReadReq_hits::total 1051 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits
|
||||||
system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.demand_hits::cpu.inst 1897 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::cpu.inst 1900 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.demand_hits::total 1897 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits::cpu.inst 1897 # number of overall hits
|
system.cpu.dcache.overall_hits::cpu.inst 1900 # number of overall hits
|
||||||
system.cpu.dcache.overall_hits::total 1897 # number of overall hits
|
system.cpu.dcache.overall_hits::total 1900 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses
|
||||||
system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses
|
||||||
|
|
@ -628,42 +381,42 @@ system.cpu.dcache.demand_misses::cpu.inst 182 # n
|
||||||
system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses
|
system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses
|
||||||
system.cpu.dcache.overall_misses::total 182 # number of overall misses
|
system.cpu.dcache.overall_misses::total 182 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6950741 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6708741 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_latency::total 6950741 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4586500 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4576500 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::total 4586500 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::cpu.inst 11537241 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::cpu.inst 11285241 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::total 11537241 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::cpu.inst 11537241 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::cpu.inst 11285241 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::total 11537241 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 1166 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::cpu.inst 1169 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_accesses::total 1166 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses::cpu.inst 2079 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::cpu.inst 2082 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.demand_accesses::total 2079 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::cpu.inst 2079 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::cpu.inst 2082 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses::total 2079 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098628 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098375 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate::total 0.098628 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate::cpu.inst 0.087542 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate::cpu.inst 0.087416 # miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::cpu.inst 0.087416 # miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 58336.878261 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68305.970149 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::total 63391.434066 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::total 63391.434066 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -688,30 +441,277 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 146
|
||||||
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6257258 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6015258 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6257258 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2857500 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9124258 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 8872758 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::total 9124258 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9124258 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 8872758 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::total 9124258 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088109 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070125 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070125 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 58400.563107 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66453.488372 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60772.315068 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60772.315068 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.tags.replacements 3 # number of replacements
|
||||||
|
system.cpu.icache.tags.tagsinuse 162.236148 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.avg_refs 5.959627 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.tags.occ_blocks::cpu.inst 162.236148 # Average occupied blocks per requestor
|
||||||
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.079217 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_percent::total 0.079217 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
|
||||||
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.icache.tags.tag_accesses 4804 # Number of tag accesses
|
||||||
|
system.cpu.icache.tags.data_accesses 4804 # Number of data accesses
|
||||||
|
system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits
|
||||||
|
system.cpu.icache.overall_hits::total 1919 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
|
||||||
|
system.cpu.icache.overall_misses::total 322 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 21729250 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.ReadReq_miss_latency::total 21729250 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency::cpu.inst 21729250 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency::total 21729250 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency::cpu.inst 21729250 # number of overall miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency::total 21729250 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses::cpu.inst 2241 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_accesses::total 2241 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses::cpu.inst 2241 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_accesses::total 2241 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::cpu.inst 2241 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses::total 2241 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143686 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate::total 0.143686 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.143686 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_miss_rate::total 0.143686 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.143686 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_miss_rate::total 0.143686 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency::total 67482.142857 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency::total 67482.142857 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20954750 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 20954750 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20954750 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency::total 20954750 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20954750 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency::total 20954750 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143686 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate::total 0.143686 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate::total 0.143686 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.tags.tagsinuse 195.981905 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.981905 # Average occupied blocks per requestor
|
||||||
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005981 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id
|
||||||
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
|
||||||
|
system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses
|
||||||
|
system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses
|
||||||
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_hits::total 39 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_misses::total 386 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses::cpu.inst 429 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses::cpu.inst 429 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_misses::total 429 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26149000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency::total 26149000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2814500 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2814500 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 28963500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency::total 28963500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 28963500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency::total 28963500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 425 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses::cpu.inst 468 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::cpu.inst 468 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908235 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.908235 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916667 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916667 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67743.523316 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65453.488372 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67513.986014 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67513.986014 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 378 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses::total 378 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 421 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 421 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20940500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2273500 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23214000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23214000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889412 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899573 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899573 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55398.148148 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52872.093023 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55140.142518 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55140.142518 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 644 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_count::total 936 # Packet count per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::5 468 100.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
|
||||||
|
system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||||
|
system.cpu.toL2Bus.respLayer0.occupancy 548250 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
|
||||||
|
system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
|
||||||
|
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||||
|
system.membus.trans_dist::ReadReq 378 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadResp 378 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||||
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
|
system.membus.snoop_fanout::samples 421 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::total 421 # Request fanout histogram
|
||||||
|
system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks)
|
||||||
|
system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
|
||||||
|
system.membus.respLayer1.occupancy 3936000 # Layer occupancy (ticks)
|
||||||
|
system.membus.respLayer1.utilization 14.1 # Layer utilization (%)
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue