2254 lines
258 KiB
Plaintext
2254 lines
258 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.818075 # Number of seconds simulated
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sim_ticks 2818074786500 # Number of ticks simulated
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final_tick 2818074786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 252135 # Simulator instruction rate (inst/s)
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host_op_rate 306151 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 5631568448 # Simulator tick rate (ticks/s)
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host_mem_usage 564964 # Number of bytes of host memory used
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host_seconds 500.41 # Real time elapsed on the host
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sim_insts 126169808 # Number of instructions simulated
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sim_ops 153199842 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 666212 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 4384416 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 128384 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1037892 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.dtb.walker 6016 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 504320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 4231744 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 10960328 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 666212 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 128384 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 504320 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1298916 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 8261760 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
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system.physmem.bytes_written::total 8279284 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 18863 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 69025 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 2006 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 16218 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.dtb.walker 94 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 7880 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 66121 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 180228 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 129090 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 133471 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 236407 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 1555820 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 45557 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 368298 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.dtb.walker 2135 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 178959 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 1501644 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3889296 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 236407 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 45557 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 178959 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 460923 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2931704 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2937922 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2931704 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 236407 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 1562035 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 45557 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 368301 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.dtb.walker 2135 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 178959 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 1501644 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6827218 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 92321 # Number of read requests accepted
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system.physmem.writeReqs 90302 # Number of write requests accepted
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system.physmem.readBursts 92321 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 90302 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 5904000 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 4544 # Total number of bytes read from write queue
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system.physmem.bytesWritten 5704128 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 5908484 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 5779208 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 71 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 1152 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 2483 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 6041 # Per bank write bursts
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system.physmem.perBankRdBursts::1 5798 # Per bank write bursts
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system.physmem.perBankRdBursts::2 5558 # Per bank write bursts
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system.physmem.perBankRdBursts::3 6021 # Per bank write bursts
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system.physmem.perBankRdBursts::4 5562 # Per bank write bursts
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system.physmem.perBankRdBursts::5 5457 # Per bank write bursts
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system.physmem.perBankRdBursts::6 6123 # Per bank write bursts
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system.physmem.perBankRdBursts::7 6801 # Per bank write bursts
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system.physmem.perBankRdBursts::8 6403 # Per bank write bursts
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system.physmem.perBankRdBursts::9 6349 # Per bank write bursts
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system.physmem.perBankRdBursts::10 5693 # Per bank write bursts
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system.physmem.perBankRdBursts::11 5092 # Per bank write bursts
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system.physmem.perBankRdBursts::12 5281 # Per bank write bursts
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system.physmem.perBankRdBursts::13 5450 # Per bank write bursts
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system.physmem.perBankRdBursts::14 5307 # Per bank write bursts
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system.physmem.perBankRdBursts::15 5314 # Per bank write bursts
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system.physmem.perBankWrBursts::0 5390 # Per bank write bursts
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system.physmem.perBankWrBursts::1 4962 # Per bank write bursts
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system.physmem.perBankWrBursts::2 5472 # Per bank write bursts
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system.physmem.perBankWrBursts::3 5886 # Per bank write bursts
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system.physmem.perBankWrBursts::4 5376 # Per bank write bursts
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system.physmem.perBankWrBursts::5 5734 # Per bank write bursts
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system.physmem.perBankWrBursts::6 5792 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6324 # Per bank write bursts
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system.physmem.perBankWrBursts::8 6132 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6057 # Per bank write bursts
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system.physmem.perBankWrBursts::10 5626 # Per bank write bursts
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system.physmem.perBankWrBursts::11 4872 # Per bank write bursts
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system.physmem.perBankWrBursts::12 5573 # Per bank write bursts
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system.physmem.perBankWrBursts::13 5712 # Per bank write bursts
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system.physmem.perBankWrBursts::14 5197 # Per bank write bursts
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system.physmem.perBankWrBursts::15 5022 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 2816508644000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 1 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 92320 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 2 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 90300 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 60706 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 28069 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 2967 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 505 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 57 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 53 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 53 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 53 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 51 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 50 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 50 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 49 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 48 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 49 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 49 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 1254 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2369 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 3788 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4880 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5164 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5960 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 6412 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 6179 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 6520 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5954 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5683 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 5086 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 5011 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4003 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 3895 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 3940 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 3737 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 316 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 264 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 222 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 195 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 200 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 178 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 155 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 152 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 130 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 124 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 97 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 78 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 69 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 68 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 62 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 43 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 39 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 27 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 33954 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 341.872416 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 193.139988 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 360.706061 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 12607 37.13% 37.13% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 7646 22.52% 59.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 2942 8.66% 68.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 1742 5.13% 73.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 1359 4.00% 77.45% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 780 2.30% 79.74% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 533 1.57% 81.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 565 1.66% 82.98% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 5780 17.02% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 33954 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 3432 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 26.875583 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 525.946384 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 3431 99.97% 99.97% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 3432 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 3432 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 25.969406 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 20.900383 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 25.459060 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::0-3 4 0.12% 0.12% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::4-7 2 0.06% 0.17% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::8-11 3 0.09% 0.26% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::12-15 2 0.06% 0.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 2696 78.55% 78.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 29 0.84% 79.72% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 30 0.87% 80.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 138 4.02% 84.62% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 83 2.42% 87.03% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 30 0.87% 87.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 20 0.58% 88.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 23 0.67% 89.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 73 2.13% 91.29% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 7 0.20% 91.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 5 0.15% 91.64% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 8 0.23% 91.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 20 0.58% 92.45% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 8 0.23% 92.69% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 8 0.23% 92.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 21 0.61% 93.53% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 41 1.19% 94.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 8 0.23% 94.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 3 0.09% 95.05% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 9 0.26% 95.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 65 1.89% 97.20% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 4 0.12% 97.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-107 7 0.20% 97.52% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 5 0.15% 97.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 7 0.20% 97.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::116-119 3 0.09% 97.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-123 8 0.23% 98.19% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::124-127 3 0.09% 98.28% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 22 0.64% 98.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 7 0.20% 99.13% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-139 2 0.06% 99.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 2 0.06% 99.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-147 2 0.06% 99.30% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::148-151 3 0.09% 99.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-155 1 0.03% 99.42% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 3 0.09% 99.50% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-163 5 0.15% 99.65% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::168-171 1 0.03% 99.68% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-179 3 0.09% 99.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::180-183 2 0.06% 99.83% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::188-191 1 0.03% 99.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::196-199 1 0.03% 99.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::200-203 1 0.03% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-227 1 0.03% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::228-231 1 0.03% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::244-247 1 0.03% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 3432 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 1184332750 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 2914020250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 461250000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 12838.30 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 31588.30 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 2.10 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.02 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 2.10 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.05 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 8.03 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 76434 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 70988 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 82.86 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 79.63 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 15422529.71 # Average gap between requests
|
|
system.physmem.pageHitRate 81.27 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 2704815148250 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 94101540000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 19154581250 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem.actEnergy::0 134477280 # Energy for activate commands per rank (pJ)
|
|
system.physmem.actEnergy::1 122214960 # Energy for activate commands per rank (pJ)
|
|
system.physmem.preEnergy::0 73375500 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.preEnergy::1 66684750 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.readEnergy::0 369415800 # Energy for read commands per rank (pJ)
|
|
system.physmem.readEnergy::1 350110800 # Energy for read commands per rank (pJ)
|
|
system.physmem.writeEnergy::0 291185280 # Energy for write commands per rank (pJ)
|
|
system.physmem.writeEnergy::1 286357680 # Energy for write commands per rank (pJ)
|
|
system.physmem.refreshEnergy::0 184062612240 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.refreshEnergy::1 184062612240 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.actBackEnergy::0 70840900170 # Energy for active background per rank (pJ)
|
|
system.physmem.actBackEnergy::1 70013903985 # Energy for active background per rank (pJ)
|
|
system.physmem.preBackEnergy::0 1628700821250 # Energy for precharge background per rank (pJ)
|
|
system.physmem.preBackEnergy::1 1629426256500 # Energy for precharge background per rank (pJ)
|
|
system.physmem.totalEnergy::0 1884472787520 # Total energy per rank (pJ)
|
|
system.physmem.totalEnergy::1 1884328140915 # Total energy per rank (pJ)
|
|
system.physmem.averagePower::0 668.710440 # Core power per rank (mW)
|
|
system.physmem.averagePower::1 668.659112 # Core power per rank (mW)
|
|
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 14476474 # DTB read hits
|
|
system.cpu0.dtb.read_misses 4869 # DTB read misses
|
|
system.cpu0.dtb.write_hits 11056177 # DTB write hits
|
|
system.cpu0.dtb.write_misses 893 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 188 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 3212 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 944 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 196 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 14481343 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 11057070 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 25532651 # DTB hits
|
|
system.cpu0.dtb.misses 5762 # DTB misses
|
|
system.cpu0.dtb.accesses 25538413 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.inst_hits 67995752 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 2758 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 188 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 1969 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 67998510 # ITB inst accesses
|
|
system.cpu0.itb.hits 67995752 # DTB hits
|
|
system.cpu0.itb.misses 2758 # DTB misses
|
|
system.cpu0.itb.accesses 67998510 # DTB accesses
|
|
system.cpu0.numCycles 82558276 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 66186941 # Number of instructions committed
|
|
system.cpu0.committedOps 80639436 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 70858992 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 5470 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 7266542 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 8791397 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 70858992 # number of integer instructions
|
|
system.cpu0.num_fp_insts 5470 # number of float instructions
|
|
system.cpu0.num_int_register_reads 131380013 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 49295072 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 4246 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written
|
|
system.cpu0.num_cc_register_reads 245776790 # number of times the CC registers were read
|
|
system.cpu0.num_cc_register_writes 29457750 # number of times the CC registers were written
|
|
system.cpu0.num_mem_refs 26204570 # number of memory refs
|
|
system.cpu0.num_load_insts 14653679 # Number of load instructions
|
|
system.cpu0.num_store_insts 11550891 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 77949108.406676 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 4609167.593324 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.055829 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.944171 # Percentage of idle cycles
|
|
system.cpu0.Branches 16455876 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 2193 0.00% 0.00% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 55779692 67.98% 67.99% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 58849 0.07% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 4532 0.01% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.06% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 14653679 17.86% 85.92% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 11550891 14.08% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 82049836 # Class of executed instruction
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 3055 # number of quiesce instructions executed
|
|
system.cpu0.dcache.tags.replacements 833965 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.996800 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 46972085 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 834477 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 56.289251 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.818118 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.670897 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.507786 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948864 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032560 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018570 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 198452344 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 198452344 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 13787811 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 4397354 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu2.data 8501200 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 26686365 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 10663716 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 3166111 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu2.data 5160414 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 18990241 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190628 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 60624 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 130481 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 381733 # number of SoftPFReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235896 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80331 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 134984 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 451211 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 237277 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 82832 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 139583 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 459692 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 24451527 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 7563465 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu2.data 13661614 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 45676606 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 24642155 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 7624089 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu2.data 13792095 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 46058339 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 191712 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 58922 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu2.data 315531 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 566165 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 143864 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 35394 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu2.data 1531641 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1710899 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54000 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 21214 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 65487 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 140701 # number of SoftPFReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4460 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3296 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9679 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 17435 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 15 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 335576 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 94316 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu2.data 1847172 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 2277064 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 389576 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 115530 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu2.data 1912659 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 2417765 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 899565500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 5307857354 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 6207422854 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1328486412 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 70638951119 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 71967437531 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 46576250 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 132400246 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 178976496 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 207001 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 207001 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 2228051912 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu2.data 75946808473 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 78174860385 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 2228051912 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu2.data 75946808473 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 78174860385 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 13979523 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 4456276 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu2.data 8816731 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 27252530 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 10807580 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 3201505 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu2.data 6692055 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 20701140 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 244628 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 81838 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 195968 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 522434 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 240356 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 83627 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 144663 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 468646 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 237279 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 82832 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 139598 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 459709 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 24787103 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 7657781 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu2.data 15508786 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 47953670 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 25031731 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 7739619 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu2.data 15704754 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 48476104 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013714 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013222 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035788 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.020775 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013311 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011055 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.228875 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.082648 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.220743 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.259219 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.334172 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269318 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018556 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.039413 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.066907 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037203 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000107 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000037 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013538 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012316 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.119105 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.047485 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015563 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014927 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.121789 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.049875 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15267.056448 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16821.983748 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10963.981973 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37534.226479 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46119.783369 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42064.106374 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14131.143811 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13679.124496 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10265.356811 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13800.066667 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12176.529412 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23623.265533 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41115.179568 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 34331.428710 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19285.483528 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39707.448360 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 32333.523062 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 374153 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 25938 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 24753 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 535 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.115461 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 48.482243 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 692650 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 692650 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 119 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 155404 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 155523 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1411618 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 1411618 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1952 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6678 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8630 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu1.data 119 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu2.data 1567022 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 1567141 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu1.data 119 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu2.data 1567022 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 1567141 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 58803 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 160127 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 218930 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 35394 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 120023 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 155417 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 20830 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 43721 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::total 64551 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1344 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3001 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4345 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 15 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 94197 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu2.data 280150 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 374347 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 115027 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 323871 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 438898 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779470500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2130747955 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2910218455 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1251702570 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5436442471 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6688145041 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 266097500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 651596008 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 917693508 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 21534500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 37307002 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58841502 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 176999 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 176999 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2031173070 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7567190426 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 9598363496 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2297270570 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8218786434 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 10516057004 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1018847500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1696409500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2715257000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 779636500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1318509000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2098145500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1798484000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3014918500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4813402500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013196 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018162 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008033 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011055 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017935 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007508 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.254527 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.223103 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123558 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016071 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.020745 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.009271 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000107 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000033 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012301 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018064 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.007806 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014862 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020622 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.009054 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13255.624713 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13306.612595 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13292.917622 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35364.823699 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45295.005716 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43033.548717 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12774.723956 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14903.501933 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14216.565320 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16022.693452 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12431.523492 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13542.347986 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11799.933333 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11799.933333 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21563.033536 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27011.209802 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25640.284271 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19971.576847 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25376.728494 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23960.138811 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 1798241 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.545331 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 100915026 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 1798752 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 56.102801 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 10926866250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.669310 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.516745 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.359276 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.932948 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.042025 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.024139 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999112 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 104562639 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 104562639 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 67129206 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 21624080 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu2.inst 12161740 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 100915026 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 67129206 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 21624080 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu2.inst 12161740 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 100915026 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 67129206 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 21624080 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu2.inst 12161740 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 100915026 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 868572 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 248802 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu2.inst 731453 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 1848827 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 868572 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 248802 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu2.inst 731453 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 1848827 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 868572 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 248802 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu2.inst 731453 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 1848827 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3368077000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10037357964 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 13405434964 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 3368077000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu2.inst 10037357964 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 13405434964 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 3368077000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu2.inst 10037357964 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 13405434964 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 67997778 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 21872882 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu2.inst 12893193 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 102763853 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 67997778 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 21872882 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu2.inst 12893193 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 102763853 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 67997778 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 21872882 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu2.inst 12893193 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 102763853 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012774 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011375 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.056732 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.017991 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012774 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011375 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.056732 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.017991 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012774 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011375 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.056732 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.017991 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13537.178158 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13722.492032 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 7250.778447 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13537.178158 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13722.492032 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 7250.778447 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13537.178158 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13722.492032 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 7250.778447 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 5131 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 344 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.915698 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 50040 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 50040 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu2.inst 50040 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 50040 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu2.inst 50040 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 50040 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 248802 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 681413 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 930215 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 248802 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu2.inst 681413 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 930215 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 248802 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu2.inst 681413 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 930215 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2869743000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8188546795 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11058289795 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2869743000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8188546795 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 11058289795 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2869743000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8188546795 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 11058289795 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011375 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.052851 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009052 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011375 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.052851 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.009052 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011375 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.052851 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.009052 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11534.244098 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12017.009941 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11887.885913 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11534.244098 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12017.009941 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11887.885913 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11534.244098 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12017.009941 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11887.885913 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 4627532 # DTB read hits
|
|
system.cpu1.dtb.read_misses 1596 # DTB read misses
|
|
system.cpu1.dtb.write_hits 3288935 # DTB write hits
|
|
system.cpu1.dtb.write_misses 256 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 148 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 1270 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 69 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 4629128 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 3289191 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 7916467 # DTB hits
|
|
system.cpu1.dtb.misses 1852 # DTB misses
|
|
system.cpu1.dtb.accesses 7918319 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.inst_hits 21872882 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 825 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 148 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 668 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 21873707 # ITB inst accesses
|
|
system.cpu1.itb.hits 21872882 # DTB hits
|
|
system.cpu1.itb.misses 825 # DTB misses
|
|
system.cpu1.itb.accesses 21873707 # DTB accesses
|
|
system.cpu1.numCycles 158012156 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 21172070 # Number of instructions committed
|
|
system.cpu1.committedOps 25390672 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 22586857 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 1738 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 2402647 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 2689176 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 22586857 # number of integer instructions
|
|
system.cpu1.num_fp_insts 1738 # number of float instructions
|
|
system.cpu1.num_int_register_reads 41666783 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 15854927 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 1290 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 92283936 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 9328431 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 8130215 # number of memory refs
|
|
system.cpu1.num_load_insts 4674464 # Number of load instructions
|
|
system.cpu1.num_store_insts 3455751 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 151523865.450182 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 6488290.549818 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.041062 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.958938 # Percentage of idle cycles
|
|
system.cpu1.Branches 5242761 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 34 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 17956106 68.78% 68.78% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 18827 0.07% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.85% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 1169 0.00% 68.86% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 68.86% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.86% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.86% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 4674464 17.91% 86.76% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 3455751 13.24% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 26106351 # Class of executed instruction
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu2.branchPred.lookups 17443399 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 9460519 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 398611 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 10920300 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 8161771 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 74.739439 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 4093630 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 21092 # Number of incorrect RAS predictions.
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu2.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.dtb.read_hits 9671030 # DTB read hits
|
|
system.cpu2.dtb.read_misses 37752 # DTB read misses
|
|
system.cpu2.dtb.write_hits 7157940 # DTB write hits
|
|
system.cpu2.dtb.write_misses 5738 # DTB write misses
|
|
system.cpu2.dtb.flush_tlb 182 # Number of times complete TLB was flushed
|
|
system.cpu2.dtb.flush_tlb_mva 368 # Number of times TLB was flushed by MVA
|
|
system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.dtb.flush_entries 2464 # Number of entries that have been flushed from TLB
|
|
system.cpu2.dtb.align_faults 439 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.dtb.prefetch_faults 949 # Number of TLB faults due to prefetch
|
|
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.dtb.perms_faults 419 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.dtb.read_accesses 9708782 # DTB read accesses
|
|
system.cpu2.dtb.write_accesses 7163678 # DTB write accesses
|
|
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.dtb.hits 16828970 # DTB hits
|
|
system.cpu2.dtb.misses 43490 # DTB misses
|
|
system.cpu2.dtb.accesses 16872460 # DTB accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu2.itb.inst_hits 12894617 # ITB inst hits
|
|
system.cpu2.itb.inst_misses 6298 # ITB inst misses
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
|
system.cpu2.itb.flush_tlb 182 # Number of times complete TLB was flushed
|
|
system.cpu2.itb.flush_tlb_mva 368 # Number of times TLB was flushed by MVA
|
|
system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.itb.flush_entries 1799 # Number of entries that have been flushed from TLB
|
|
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.itb.perms_faults 1027 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.itb.inst_accesses 12900915 # ITB inst accesses
|
|
system.cpu2.itb.hits 12894617 # DTB hits
|
|
system.cpu2.itb.misses 6298 # DTB misses
|
|
system.cpu2.itb.accesses 12900915 # DTB accesses
|
|
system.cpu2.numCycles 69897742 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.fetch.icacheStallCycles 26768356 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 69154350 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 17443399 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 12255401 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 39728052 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 2075674 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.TlbCycles 91833 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu2.fetch.MiscStallCycles 964 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.PendingDrainCycles 303 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu2.fetch.PendingTrapStallCycles 279943 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.PendingQuiesceStallCycles 102540 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu2.fetch.IcacheWaitRetryStallCycles 510 # Number of stall cycles due to full MSHR
|
|
system.cpu2.fetch.CacheLines 12893196 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 269600 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.ItlbSquashes 2749 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 68010313 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.222372 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 2.345734 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 49396667 72.63% 72.63% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 2406815 3.54% 76.17% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 1558633 2.29% 78.46% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 4908408 7.22% 85.68% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 1099721 1.62% 87.30% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 702073 1.03% 88.33% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 3889062 5.72% 94.05% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 750470 1.10% 95.15% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 3298464 4.85% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 68010313 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.249556 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 0.989365 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 18657683 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 36955851 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 10391299 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 1075131 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 930120 # Number of cycles decode is squashing
|
|
system.cpu2.decode.BranchResolved 1306172 # Number of times decode resolved a branch
|
|
system.cpu2.decode.BranchMispred 109269 # Number of times decode detected a branch misprediction
|
|
system.cpu2.decode.DecodedInsts 59268734 # Number of instructions handled by decode
|
|
system.cpu2.decode.SquashedInsts 353681 # Number of squashed instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 930120 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 19279637 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 4349454 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 27177493 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 10831041 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 5442328 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 56795330 # Number of instructions processed by rename
|
|
system.cpu2.rename.ROBFullEvents 2300 # Number of times rename has blocked due to ROB full
|
|
system.cpu2.rename.IQFullEvents 936981 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LQFullEvents 152434 # Number of times rename has blocked due to LQ full
|
|
system.cpu2.rename.SQFullEvents 3851730 # Number of times rename has blocked due to SQ full
|
|
system.cpu2.rename.RenamedOperands 58689966 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 260889069 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 63678439 # Number of integer rename lookups
|
|
system.cpu2.rename.fp_rename_lookups 4318 # Number of floating rename lookups
|
|
system.cpu2.rename.CommittedMaps 48634410 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 10055540 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 957404 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 893614 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 6253924 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 10259989 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 7928891 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 1377694 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 1916931 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 54575287 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 669934 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 51950842 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 68646 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 7267604 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 18361034 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 68925 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 68010313 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 0.763867 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.465859 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 47556715 69.93% 69.93% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 6835010 10.05% 79.98% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 5099948 7.50% 87.47% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 4195226 6.17% 93.64% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 1610331 2.37% 96.01% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 1069065 1.57% 97.58% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 1123688 1.65% 99.23% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 361159 0.53% 99.77% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 159171 0.23% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 68010313 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 78624 9.78% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 1 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.78% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 373360 46.42% 56.20% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 352326 43.80% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 110 0.00% 0.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 34419657 66.25% 66.25% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 39271 0.08% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 2 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 2864 0.01% 66.34% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.34% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.34% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.34% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 9952470 19.16% 85.49% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 7536463 14.51% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 51950842 # Type of FU issued
|
|
system.cpu2.iq.rate 0.743241 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 804311 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.015482 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 172775366 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 62545429 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 50354259 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 9588 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 5092 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 4209 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 52749857 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 5186 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 265342 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 1601303 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 1888 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 38444 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 793651 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 130825 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 118759 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 930120 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 3238109 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 943841 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 55348166 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 92957 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 10259989 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 7928891 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 358502 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 33985 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 900757 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 38444 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 183146 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 162363 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 345509 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 51516440 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 9776464 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 391010 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 102945 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 17239257 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 9485344 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 7462793 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 0.737026 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 51063802 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 50358468 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 26440569 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 45930116 # num instructions consuming a value
|
|
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu2.iew.wb_rate 0.720459 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.575670 # average fanout of values written-back
|
|
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu2.commit.commitSquashedInsts 8108589 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 601009 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 290869 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 66287251 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 0.712520 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 1.616760 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 48204047 72.72% 72.72% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 8094433 12.21% 84.93% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 3998554 6.03% 90.96% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 1723968 2.60% 93.56% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 875669 1.32% 94.89% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 615346 0.93% 95.81% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 1257319 1.90% 97.71% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 299111 0.45% 98.16% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 1218804 1.84% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 66287251 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 38872037 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 47230974 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 15793926 # Number of memory references committed
|
|
system.cpu2.commit.loads 8658686 # Number of loads committed
|
|
system.cpu2.commit.membars 225734 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 8913791 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 41344274 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 1642310 # Number of function calls committed.
|
|
system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntAlu 31396236 66.47% 66.47% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntMult 37948 0.08% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.55% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMisc 2864 0.01% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemRead 8658686 18.33% 84.89% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemWrite 7135240 15.11% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::total 47230974 # Class of committed instruction
|
|
system.cpu2.commit.bw_lim_events 1218804 # number cycles where commit BW limit reached
|
|
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu2.rob.rob_reads 112988408 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 112405622 # The number of ROB writes
|
|
system.cpu2.timesIdled 280375 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 1887429 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 5250225403 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 38810797 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 47169734 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.cpi 1.800987 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 1.800987 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 0.555251 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 0.555251 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 56393520 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 31926452 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_reads 15872 # number of floating regfile reads
|
|
system.cpu2.fp_regfile_writes 13692 # number of floating regfile writes
|
|
system.cpu2.cc_regfile_reads 182232541 # number of cc regfile reads
|
|
system.cpu2.cc_regfile_writes 19215539 # number of cc regfile writes
|
|
system.cpu2.misc_regfile_reads 124355307 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 481535 # number of misc regfile writes
|
|
system.iobus.trans_dist::ReadReq 30188 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 30188 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59019 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 22795 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 159119 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 18213000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 2807000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 15730000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 217719639 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 39873000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 22974011 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 36442 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.993341 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 245004243009 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 0.993341 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.062084 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.062084 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328284 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 252 # number of overall misses
|
|
system.iocache.overall_misses::total 252 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ide 14419928 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 14419928 # number of ReadReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6029712700 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::total 6029712700 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 14419928 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 14419928 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 14419928 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 14419928 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 57221.936508 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 57221.936508 # average ReadReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 166456.291409 # average WriteInvalidateReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::total 166456.291409 # average WriteInvalidateReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 57221.936508 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 57221.936508 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 34890 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 4513 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 7.730999 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
|
system.iocache.writebacks::total 36190 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 127 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 127 # number of ReadReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 22720 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::total 22720 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 127 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 127 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 127 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 127 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 7815928 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 7815928 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4848250722 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4848250722 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 7815928 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 7815928 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 7815928 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 7815928 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 0.503968 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.627208 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.627208 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 0.503968 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 0.503968 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61542.740157 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 61542.740157 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213391.316989 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213391.316989 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 61542.740157 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 61542.740157 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 61542.740157 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 61542.740157 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 100831 # number of replacements
|
|
system.l2c.tags.tagsinuse 65118.744874 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 2894730 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 166072 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 17.430572 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 49795.493403 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939326 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 5292.397633 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 2853.974292 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969197 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 1121.420686 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 949.232304 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.dtb.walker 58.100226 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 3505.367496 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 1539.850216 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.759819 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.080756 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.043548 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.017112 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.014484 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000887 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.053488 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.023496 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.993633 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 65196 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 45 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 3290 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 7951 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 53614 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000687 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.994812 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 27445059 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 27445059 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 5016 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 2571 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 858721 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 243218 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 1379 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 679 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 246795 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 78418 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.dtb.walker 27414 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.itb.walker 6412 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 673438 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 202274 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 2346335 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 692650 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 692650 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 9 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 5 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu2.data 41 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 55 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu2.data 14 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 14 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 80155 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 20967 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu2.data 56516 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 157638 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 5016 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 2571 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 858721 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 323373 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 1379 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 679 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 246795 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 99385 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.dtb.walker 27414 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.itb.walker 6412 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 673438 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 258790 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2503973 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 5016 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 2571 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 858721 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 323373 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 1379 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 679 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 246795 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 99385 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.dtb.walker 27414 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.itb.walker 6412 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 673438 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 258790 # number of overall hits
|
|
system.l2c.overall_hits::total 2503973 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 9846 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 6954 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 2006 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 2559 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.dtb.walker 94 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.inst 7888 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.data 4558 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 33911 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 1225 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 431 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 1060 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 2716 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 62475 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 13991 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 62423 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 138889 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 9846 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 69429 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 2006 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 16550 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.dtb.walker 94 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 7888 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 66981 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 172800 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 9846 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 69429 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 2006 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 16550 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.dtb.walker 94 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 7888 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 66981 # number of overall misses
|
|
system.l2c.overall_misses::total 172800 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 144626500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 192907250 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 7248000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.inst 607430500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.data 371890495 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 1324177245 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 22999 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu2.data 301987 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 324986 # number of UpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 987166510 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 4660643249 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 5647809759 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 144626500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 1180073760 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.dtb.walker 7248000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 607430500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 5032533744 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 6971987004 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 144626500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 1180073760 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.dtb.walker 7248000 # number of overall miss cycles
|
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|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 1961647000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1668818000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2819608000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 4488426000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000725 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008063 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.031602 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003417 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011570 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021829 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.007166 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988532 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.962761 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.538073 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.066667 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.058824 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.400223 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.524832 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.257697 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000725 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008063 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.142752 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003417 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011570 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.205476 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.034920 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000725 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008063 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.142752 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003417 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011570 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.205476 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.034920 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59455.882353 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62886.186010 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64755.319149 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 64427.787644 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 69219.046512 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 64881.697444 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10002.886792 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.341382 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57766.563505 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62320.767201 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 61486.916547 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59455.882353 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58558.171601 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64755.319149 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 64427.787644 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62786.059428 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 62106.440817 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59455.882353 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58558.171601 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64755.319149 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 64427.787644 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62786.059428 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 62106.440817 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 74228 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 74227 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 27571 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 27571 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 129090 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4545 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4548 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 137060 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 137060 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471586 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 579048 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109015 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 109015 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 688063 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16930172 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 17093291 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642496 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 4642496 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 21735787 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 288 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 341037 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 341037 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 341037 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 40803000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 460500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 937458500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 904148767 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 23873989 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.toL2Bus.trans_dist::ReadReq 2443122 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2443118 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 692650 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteInvalidateReq 22720 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 2771 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 2788 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 296527 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 296527 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3615529 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484690 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28930 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88144 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 6217293 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115152760 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97928947 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48448 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 155392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 213285547 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 51952 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 3431323 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 5.010630 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.102554 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::5 3394847 98.94% 98.94% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::6 36476 1.06% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 3431323 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 2376326693 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 558000 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 4188826435 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 2020844355 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 11830425 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 39636892 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|