X86: Start implementing the interrupt command register in the local APIC.
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3 changed files with 52 additions and 14 deletions
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@ -31,6 +31,8 @@
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#ifndef __ARCH_X86_APICREGS_HH__
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#define __ARCH_X86_APICREGS_HH__
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#include "base/bitunion.hh"
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namespace X86ISA
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{
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enum ApicRegIndex
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@ -86,6 +88,20 @@ namespace X86ISA
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{
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return (ApicRegIndex)(APIC_INTERRUPT_REQUEST_BASE + index);
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}
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BitUnion32(InterruptCommandRegLow)
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Bitfield<7, 0> vector;
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Bitfield<10, 8> deliveryMode;
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Bitfield<11> destMode;
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Bitfield<12> deliveryStatus;
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Bitfield<14> level;
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Bitfield<15> trigger;
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Bitfield<19, 18> destShorthand;
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EndBitUnion(InterruptCommandRegLow)
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BitUnion32(InterruptCommandRegHigh)
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Bitfield<31, 24> destination;
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EndBitUnion(InterruptCommandRegHigh)
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}
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#endif
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@ -60,6 +60,7 @@
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#include "arch/x86/intmessage.hh"
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#include "cpu/base.hh"
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#include "mem/packet_access.hh"
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#include "sim/system.hh"
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int
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divideFromConf(uint32_t conf)
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@ -366,14 +367,6 @@ X86ISA::Interrupts::readReg(ApicRegIndex reg)
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case APIC_ERROR_STATUS:
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regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
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break;
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case APIC_INTERRUPT_COMMAND_LOW:
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panic("Local APIC Interrupt Command low"
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" register unimplemented.\n");
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break;
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case APIC_INTERRUPT_COMMAND_HIGH:
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panic("Local APIC Interrupt Command high"
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" register unimplemented.\n");
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break;
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case APIC_CURRENT_COUNT:
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{
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if (apicTimerEvent.scheduled()) {
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@ -459,12 +452,40 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
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}
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break;
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case APIC_INTERRUPT_COMMAND_LOW:
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panic("Local APIC Interrupt Command low"
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" register unimplemented.\n");
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{
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InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
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// Check if we're already sending an IPI.
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if (low.deliveryStatus) {
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newVal = low;
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break;
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case APIC_INTERRUPT_COMMAND_HIGH:
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panic("Local APIC Interrupt Command high"
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" register unimplemented.\n");
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}
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low = val;
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InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
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// Record that an IPI is being sent.
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low.deliveryStatus = 1;
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TriggerIntMessage message;
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message.destination = high.destination;
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message.vector = low.vector;
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message.deliveryMode = low.deliveryMode;
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message.destMode = low.destMode;
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message.level = low.level;
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message.trigger = low.trigger;
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bool timing = sys->getMemoryMode() == Enums::timing;
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switch (low.destShorthand) {
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case 0:
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intPort->sendMessage(message, timing);
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break;
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case 1:
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panic("Self IPIs aren't implemented.\n");
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break;
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case 2:
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panic("Broadcast including self IPIs aren't implemented.\n");
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break;
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case 3:
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panic("Broadcast excluding self IPIs aren't implemented.\n");
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break;
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}
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}
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break;
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case APIC_LVT_TIMER:
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case APIC_LVT_THERMAL_SENSOR:
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@ -34,6 +34,7 @@
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#include "arch/x86/x86_traits.hh"
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#include "base/bitunion.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "mem/request.hh"
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#include "sim/host.hh"
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