Changed MIPS and Alpha to pass the syscall number to the syscall function
arch/alpha/isa/decoder.isa: Fixed up Alpha to pass the syscall number directly to the syscall function. arch/mips/isa/decoder.isa: Fixed up MIPS to pass the syscall number directly to the syscall function. arch/mips/isa/operands.isa: Added an R2 operand which is passed to the syscall function as the syscall number to use. --HG-- extra : convert_revision : 066d486cd6a2761b29e413c6d526c268788975f3
This commit is contained in:
parent
3d99b4a544
commit
609c4ecea6
3 changed files with 3 additions and 2 deletions
|
@ -693,7 +693,7 @@ decode OPCODE default Unknown::unknown() {
|
||||||
SimExit(curTick, "halt instruction encountered");
|
SimExit(curTick, "halt instruction encountered");
|
||||||
}}, IsNonSpeculative);
|
}}, IsNonSpeculative);
|
||||||
0x83: callsys({{
|
0x83: callsys({{
|
||||||
xc->syscall();
|
xc->syscall(R0);
|
||||||
}}, IsNonSpeculative);
|
}}, IsNonSpeculative);
|
||||||
// Read uniq reg into ABI return value register (r0)
|
// Read uniq reg into ABI return value register (r0)
|
||||||
0x9e: rduniq({{ R0 = Runiq; }});
|
0x9e: rduniq({{ R0 = Runiq; }});
|
||||||
|
|
|
@ -89,7 +89,7 @@ decode OPCODE_HI default Unknown::unknown() {
|
||||||
}
|
}
|
||||||
|
|
||||||
format BasicOp {
|
format BasicOp {
|
||||||
0x4: syscall({{ xc->syscall(); }},IsNonSpeculative);
|
0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative);
|
||||||
0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative);
|
0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative);
|
||||||
0x7: sync({{ panic("Not implemented sync yet"); }},IsNonSpeculative);
|
0x7: sync({{ panic("Not implemented sync yet"); }},IsNonSpeculative);
|
||||||
}
|
}
|
||||||
|
|
|
@ -18,6 +18,7 @@ def operands {{
|
||||||
'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
|
'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
|
||||||
'r31': ('IntReg', 'uw','R31','IsInteger', 4),
|
'r31': ('IntReg', 'uw','R31','IsInteger', 4),
|
||||||
'R0': ('IntReg', 'uw','R0', 'IsInteger', 5),
|
'R0': ('IntReg', 'uw','R0', 'IsInteger', 5),
|
||||||
|
'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
|
||||||
|
|
||||||
'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
|
'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue