diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index e09673269..3d38e91f9 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -693,7 +693,7 @@ decode OPCODE default Unknown::unknown() {
                 SimExit(curTick, "halt instruction encountered");
             }}, IsNonSpeculative);
             0x83: callsys({{
-                xc->syscall();
+                xc->syscall(R0);
             }}, IsNonSpeculative);
             // Read uniq reg into ABI return value register (r0)
             0x9e: rduniq({{ R0 = Runiq; }});
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index f5dd3d911..2df2b0403 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -89,7 +89,7 @@ decode OPCODE_HI default Unknown::unknown() {
                 }
 
                 format BasicOp {
-                    0x4: syscall({{ xc->syscall(); }},IsNonSpeculative);
+                    0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative);
                     0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative);
                     0x7: sync({{  panic("Not implemented sync yet"); }},IsNonSpeculative);
                 }
diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
index 13870337b..c01496dc9 100644
--- a/arch/mips/isa/operands.isa
+++ b/arch/mips/isa/operands.isa
@@ -18,6 +18,7 @@ def operands {{
     'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
     'r31': ('IntReg', 'uw','R31','IsInteger', 4),
     'R0':  ('IntReg', 'uw','R0', 'IsInteger', 5),
+    'R2':  ('IntReg', 'uw','2', 'IsInteger', 5),
 
     'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),