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Changed MIPS and Alpha to pass the syscall number to the syscall function

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arch/alpha/isa/decoder.isa:
    Fixed up Alpha to pass the syscall number directly to the syscall function.
arch/mips/isa/decoder.isa:
    Fixed up MIPS to pass the syscall number directly to the syscall function.
arch/mips/isa/operands.isa:
    Added an R2 operand which is passed to the syscall function as the syscall number to use.

--HG--
extra : convert_revision : 066d486cd6a2761b29e413c6d526c268788975f3
This commit is contained in:
Gabe Black 2006-04-18 09:44:24 -04:00
parent 3d99b4a544
commit 609c4ecea6
3 changed files with 3 additions and 2 deletions
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2
arch/alpha/isa/decoder.isa
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@ -693,7 +693,7 @@ decode OPCODE default Unknown::unknown() {
SimExit(curTick, "halt instruction encountered");
}}, IsNonSpeculative);
0x83: callsys({{
xc->syscall();
xc->syscall(R0);
}}, IsNonSpeculative);
// Read uniq reg into ABI return value register (r0)
0x9e: rduniq({{ R0 = Runiq; }});

2
arch/mips/isa/decoder.isa
View file

@ -89,7 +89,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
format BasicOp {
0x4: syscall({{ xc->syscall(); }},IsNonSpeculative);
0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative);
0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative);
0x7: sync({{ panic("Not implemented sync yet"); }},IsNonSpeculative);
}

1
arch/mips/isa/operands.isa
View file

@ -18,6 +18,7 @@ def operands {{
'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
'r31': ('IntReg', 'uw','R31','IsInteger', 4),
'R0': ('IntReg', 'uw','R0', 'IsInteger', 5),
'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),