tests: Add CPU switching tests

This changeset adds a set of tests that stress the CPU switching
code. It adds the following test configurations:

 * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3)
 * realview-switcheroo-atomic -- ARM system (atomic<->atomic)
 * realview-switcheroo-timing -- ARM system (timing<->timing)
 * realview-switcheroo-o3 -- ARM system (O3<->O3)
 * realview-switcheroo-full -- ARM system (atomic, timing, O3)

Reference data is provided for the 10.linux-boot test case. All of the
tests trigger a CPU switch once per millisecond during the boot
process.

The in-order CPU model was not included in any of the tests as it does
not support CPU handover.

tests/SConscript

@@ -301,7 +301,8 @@ if env['TARGET_ISA'] == 'alpha':
                 'tsunami-simple-timing-dual',
                 'twosys-tsunami-simple-atomic',
                 'tsunami-o3', 'tsunami-o3-dual',
-                'tsunami-inorder']
+                'tsunami-inorder',
+                'tsunami-switcheroo-full']
 if env['TARGET_ISA'] == 'sparc':
     configs += ['t1000-simple-atomic',
                 't1000-simple-timing']
@@ -314,7 +315,11 @@ if env['TARGET_ISA'] == 'arm':
                 'realview-simple-timing-dual',
                 'realview-o3',
                 'realview-o3-checker',
-                'realview-o3-dual']
+                'realview-o3-dual',
+                'realview-switcheroo-atomic',
+                'realview-switcheroo-timing',
+                'realview-switcheroo-o3',
+                'realview-switcheroo-full']
 if env['TARGET_ISA'] == 'x86':
     configs += ['pc-simple-atomic',
                 'pc-simple-timing',

tests/configs/alpha_generic.py

@@ -91,3 +91,10 @@ class LinuxAlphaFSSystemUniprocessor(LinuxAlphaSystemBuilder,
     def __init__(self, **kwargs):
         BaseFSSystemUniprocessor.__init__(self, **kwargs)
         LinuxAlphaSystemBuilder.__init__(self)
+
+class LinuxAlphaFSSwitcheroo(LinuxAlphaSystemBuilder, BaseFSSwitcheroo):
+    """Uniprocessor Alpha system prepared for CPU switching"""
+
+    def __init__(self, **kwargs):
+        BaseFSSwitcheroo.__init__(self, **kwargs)
+        LinuxAlphaSystemBuilder.__init__(self)

tests/configs/arm_generic.py

@@ -93,3 +93,11 @@ class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder,
     def __init__(self, machine_type='RealView_PBX', **kwargs):
         BaseFSSystemUniprocessor.__init__(self, **kwargs)
         LinuxArmSystemBuilder.__init__(self, machine_type)
+
+
+class LinuxArmFSSwitcheroo(LinuxArmSystemBuilder, BaseFSSwitcheroo):
+    """Uniprocessor ARM system prepared for CPU switching"""
+
+    def __init__(self, machine_type='RealView_PBX', **kwargs):
+        BaseFSSwitcheroo.__init__(self, **kwargs)
+        LinuxArmSystemBuilder.__init__(self, machine_type)

tests/configs/base_config.py

@@ -121,10 +121,13 @@ class BaseSystem(object):
 
         sha_bus = self.create_caches_shared(system)
         for cpu in system.cpu:
-            self.create_caches_private(cpu)
+            if not cpu.switched_out:
-            self.init_cpu(system, cpu)
+                self.create_caches_private(cpu)
-            cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
+                self.init_cpu(system, cpu)
-                                system.membus)
+                cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
+                                    system.membus)
+            else:
+                self.init_cpu(system, cpu)
 
     @abstractmethod
     def create_system(self):
@@ -173,3 +176,16 @@ class BaseFSSystemUniprocessor(BaseFSSystem):
 
     def create_caches_shared(self, system):
         return None
+
+class BaseFSSwitcheroo(BaseFSSystem):
+    """Uniprocessor system prepared for CPU switching"""
+
+    def __init__(self, cpu_classes, **kwargs):
+        BaseFSSystem.__init__(self, **kwargs)
+        self.cpu_classes = tuple(cpu_classes)
+
+    def create_cpus(self):
+        cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True)
+                 for cclass in self.cpu_classes ]
+        cpus[0].switched_out = False
+        return cpus

tests/configs/realview-switcheroo-atomic.py

@@ -0,0 +1,48 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.objects import *
+from arm_generic import *
+import switcheroo
+
+root = LinuxArmFSSwitcheroo(
+    cpu_classes=(AtomicSimpleCPU, AtomicSimpleCPU)
+    ).create_root()
+
+# Setup a custom test method that uses the switcheroo tester that
+# switches between CPU models.
+run_test = switcheroo.run_test

tests/configs/realview-switcheroo-full.py

@@ -0,0 +1,48 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.objects import *
+from arm_generic import *
+import switcheroo
+
+root = LinuxArmFSSwitcheroo(
+    cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
+    ).create_root()
+
+# Setup a custom test method that uses the switcheroo tester that
+# switches between CPU models.
+run_test = switcheroo.run_test

tests/configs/realview-switcheroo-o3.py

@@ -0,0 +1,48 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.objects import *
+from arm_generic import *
+import switcheroo
+
+root = LinuxArmFSSwitcheroo(
+    cpu_classes=(DerivO3CPU, DerivO3CPU)
+    ).create_root()
+
+# Setup a custom test method that uses the switcheroo tester that
+# switches between CPU models.
+run_test = switcheroo.run_test

tests/configs/realview-switcheroo-timing.py

@@ -0,0 +1,48 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.objects import *
+from arm_generic import *
+import switcheroo
+
+root = LinuxArmFSSwitcheroo(
+    cpu_classes=(TimingSimpleCPU, TimingSimpleCPU)
+    ).create_root()
+
+# Setup a custom test method that uses the switcheroo tester that
+# switches between CPU models.
+run_test = switcheroo.run_test

tests/configs/switcheroo.py

@@ -0,0 +1,138 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+from Caches import *
+
+def _memMode(cclass):
+    if cclass == AtomicSimpleCPU:
+        return "atomic", m5.objects.params.atomic
+    else:
+        return "timing", m5.objects.params.timing
+
+class Sequential:
+    """Sequential CPU switcher.
+
+    The sequential CPU switches between all CPUs in a system in
+    order. The CPUs in the system must have been prepared for
+    switching, which in practice means that only one CPU is switched
+    in. base_config.BaseFSSwitcheroo can be used to create such a
+    system.
+    """
+    def __init__(self, cpus):
+        self.first_cpu = None
+        for (cpuno, cpu) in enumerate(cpus):
+            if not cpu.switched_out:
+                if self.first_cpu != None:
+                    fatal("More than one CPU is switched in");
+                self.first_cpu = cpuno
+
+        if self.first_cpu == None:
+            fatal("The system contains no switched in CPUs")
+
+        self.cur_cpu = self.first_cpu
+        self.cpus = cpus
+
+    def next(self):
+        self.cur_cpu = (self.cur_cpu + 1) % len(self.cpus)
+        return self.cpus[self.cur_cpu]
+
+    def first(self):
+        return self.cpus[self.first_cpu]
+
+def run_test(root, switcher=None, freq=1000):
+    """Test runner for CPU switcheroo tests.
+
+    The switcheroo test runner is used to switch CPUs in a system that
+    has been prepared for CPU switching. Such systems should have
+    multiple CPUs when they are instantiated, but only one should be
+    switched in. Such configurations can be created using the
+    base_config.BaseFSSwitcheroo class.
+
+    A CPU switcher object is used to control switching. The default
+    switcher sequentially switches between all CPUs in a system,
+    starting with the CPU that is currently switched in.
+
+    Unlike most other test runners, this one automatically configures
+    the memory mode of the system based on the first CPU the switcher
+    reports.
+
+    Keyword Arguments:
+      switcher -- CPU switcher implementation. See Sequential for
+                  an example implementation.
+      period -- Switching frequency in Hz.
+    """
+
+    if switcher == None:
+        switcher = Sequential(root.system.cpu)
+
+    current_cpu = switcher.first()
+    system = root.system
+    system.mem_mode = _memMode(type(current_cpu))[0]
+
+    # instantiate configuration
+    m5.instantiate()
+
+    # Determine the switching period, this has to be done after
+    # instantiating the system since the time base must be fixed.
+    period = m5.ticks.fromSeconds(1.0 / freq)
+    while True:
+        exit_event = m5.simulate(period)
+        exit_cause = exit_event.getCause()
+
+        if exit_cause == "simulate() limit reached":
+            next_cpu = switcher.next()
+
+            print "Switching CPUs..."
+            print "Next CPU: %s" % type(next_cpu)
+            m5.drain(system)
+            system.setMemoryMode(_memMode(type(next_cpu))[1])
+            if current_cpu != next_cpu:
+                m5.switchCpus([ (current_cpu, next_cpu) ])
+            else:
+                print "Source CPU and destination CPU are the same, skipping..."
+            m5.resume(system)
+            current_cpu = next_cpu
+        elif exit_cause == "target called exit()" or \
+                exit_cause == "m5_exit instruction encountered":
+
+            sys.exit(0)
+        else:
+            print "Test failed: Unknown exit cause: %s" % exit_cause
+            sys.exit(1)

tests/configs/tsunami-switcheroo-full.py

@@ -0,0 +1,48 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.objects import *
+from alpha_generic import *
+import switcheroo
+
+root = LinuxAlphaFSSwitcheroo(
+    cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
+    ).create_root()
+
+# Setup a custom test method that uses the switcheroo tester that
+# switches between CPU models.
+run_test = switcheroo.run_test

tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr

@@ -0,0 +1,9 @@
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything

tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal

@@ -0,0 +1,108 @@
+M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
+
Got Configuration 623
+
memsize 8000000 pages 4000 
+
First free page after ROM 0xFFFFFC0000018000
+
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
+
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
+
CPU Clock at 2000 MHz IntrClockFrequency=1024 
+
Booting with 1 processor(s) 
+
KSP: 0x20043FE8 PTBR 0x20
+
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
+
Memory cluster 0 [0 - 392]
+
Memory cluster 1 [392 - 15992]
+
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 
+
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
+
unix_boot_mem ends at FFFFFC0000076000 
+
k_argc = 0 
+
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
+
CallbackFixup 0 18000, t7=FFFFFC000070C000
+
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
+
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
+
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
+
Command line: root=/dev/hda1 console=ttyS0
+
memcluster 0, usage 1, start        0, end      392
+
memcluster 1, usage 0, start      392, end    16384
+
freeing pages 1069:16384
+
reserving pages 1069:1070
+
4096K Bcache detected; load hit latency 6 cycles, load miss latency 32 cycles
+
SMP: 1 CPUs probed -- cpu_present_mask = 1
+
Built 1 zonelists
+
Kernel command line: root=/dev/hda1 console=ttyS0
+
PID hash table entries: 1024 (order: 10, 32768 bytes)
+
Using epoch = 1900
+
Console: colour dummy device 80x25
+
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
+
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
+
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
+
Mount-cache hash table entries: 512
+
SMP mode deactivated.
+
Brought up 1 CPUs
+
SMP: Total of 1 processors activated (4002.20 BogoMIPS).
+
NET: Registered protocol family 16
+
EISA bus registered
+
pci: enabling save/restore of SRM state
+
SCSI subsystem initialized
+
srm_env: version 0.0.5 loaded successfully
+
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+
Initializing Cryptographic API
+
rtc: Standard PC (1900) epoch (1900) detected
+
Real Time Clock Driver v1.12
+
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
+
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+
io scheduler noop registered
+
io scheduler anticipatory registered
+
io scheduler deadline registered
+
io scheduler cfq registered
+
loop: loaded (max 8 devices)
+
nbd: registered device at major 43
+
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+
PCI: Setting latency timer of device 0000:00:01.0 to 64
+
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
+
eth0: enabling optical transceiver
+
eth0: using 64 bit addressing.
+
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
+
tun: Universal TUN/TAP device driver, 1.6
+
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
+
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
+
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+
PIIX4: IDE controller at PCI slot 0000:00:00.0
+
PIIX4: chipset revision 0
+
PIIX4: 100% native mode on irq 31
+
PCI: Setting latency timer of device 0000:00:00.0 to 64
+
    ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
+
    ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
+
hda: M5 IDE Disk, ATA DISK drive
+
hdb: M5 IDE Disk, ATA DISK drive
+
ide0 at 0x8410-0x8417,0x8422 on irq 31
+
hda: max request size: 128KiB
+
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
+
hda: cache flushes not supported
+
 hda: hda1
+
hdb: max request size: 128KiB
+
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+
hdb: cache flushes not supported
+
 hdb: unknown partition table
+
mice: PS/2 mouse device common for all mice
+
NET: Registered protocol family 2
+
IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
+
TCP established hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP: Hash tables configured (established 16384 bind 16384)
+
TCP reno registered
+
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
+
ip_tables: (C) 2000-2002 Netfilter core team
+
arp_tables: (C) 2002 David S. Miller
+
TCP bic registered
+
Initializing IPsec netlink socket
+
NET: Registered protocol family 1
+
NET: Registered protocol family 17
+
NET: Registered protocol family 15
+
Bridge firewalling registered
+
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
+
All bugs added by David S. Miller <davem@redhat.com>
+
VFS: Mounted root (ext2 filesystem) readonly.
+
Freeing unused kernel memory: 224k freed
+

init started:  BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
+mounting filesystems...
+EXT2-fs warning: checktime reached, running e2fsck is recommended
+
loading script...

tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr

@@ -0,0 +1,28 @@
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: 	instruction 'mcr icialluis' unimplemented
+hack: be nice to actually delete the event here
+warn: 	instruction 'mcr dccimvac' unimplemented
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
+warn: LCD dual screen mode not supported
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR

tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr

@@ -0,0 +1,18 @@
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: 	instruction 'mcr icialluis' unimplemented
+hack: be nice to actually delete the event here
+warn: 	instruction 'mcr dccimvac' unimplemented
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
+warn: LCD dual screen mode not supported
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR

tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini

@@ -0,0 +1,795 @@
+[root]
+type=Root
+children=system
+full_system=true
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+atags_addr=256
+boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+clock=1000
+dtb_filename=
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+flags_addr=268435504
+gic_cpu_addr=520093952
+init_param=0
+kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+load_addr_mask=268435455
+machine_type=RealView_PBX
+mem_mode=timing
+mem_ranges=0:134217727
+memories=system.physmem system.realview.nvmem
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+readfile=tests/halt.sh
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.bridge]
+type=Bridge
+clock=1000
+delay=50000
+ranges=268435456:520093695 1073741824:1610612735
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img
+read_only=true
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts isa itb tracer
+checker=Null
+clock=500
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=1
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+
+[system.cpu0.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[2]
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dtb interrupts isa itb tracer
+checker=Null
+clock=500
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+switched_out=true
+system=system
+tracer=system.cpu1.tracer
+workload=
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.interrupts]
+type=ArmInterrupts
+
+[system.cpu1.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=NoncoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=8
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+
+[system.iocache]
+type=BaseCache
+addr_ranges=0:134217727
+assoc=8
+block_size=64
+clock=1000
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+size=1024
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[25]
+mem_side=system.membus.slave[2]
+
+[system.l2c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.membus]
+type=CoherentBus
+children=badaddr_responder
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
+conf_table_reported=true
+in_addr_map=true
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
+null=false
+page_policy=open
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
+zero=false
+port=system.membus.master[2]
+
+[system.realview]
+type=RealView
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+intrctrl=system.intrctrl
+max_mem_size=268435456
+mem_start_addr=0
+pci_cfg_base=0
+system=system
+
+[system.realview.a9scu]
+type=A9SCU
+clock=1000
+pio_addr=520093696
+pio_latency=100000
+system=system
+pio=system.membus.master[5]
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268451840
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=402653184
+BAR0LegacyIO=true
+BAR0Size=16
+BAR1=402653440
+BAR1LegacyIO=true
+BAR1Size=1
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clock=1000
+config_latency=20000
+ctrl_offset=2
+disks=system.cf0
+io_shift=1
+pci_bus=2
+pci_dev=7
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[8]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[7]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clock=1000
+gic=system.realview.gic
+int_num=55
+pio_addr=268566528
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.dmac_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268632064
+pio_latency=100000
+system=system
+pio=system.iobus.master[9]
+
+[system.realview.flash_fake]
+type=IsaFake
+clock=1000
+fake_mem=true
+pio_addr=1073741824
+pio_latency=100000
+pio_size=536870912
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[24]
+
+[system.realview.gic]
+type=Gic
+clock=1000
+cpu_addr=520093952
+cpu_pio_delay=10000
+dist_addr=520097792
+dist_pio_delay=10000
+int_latency=10000
+it_lines=128
+platform=system.realview
+system=system
+pio=system.membus.master[3]
+
+[system.realview.gpio0_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268513280
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.gpio1_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268517376
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.realview.gpio2_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268521472
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clock=1000
+gic=system.realview.gic
+int_delay=1000000
+int_num=52
+is_mouse=false
+pio_addr=268460032
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[5]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clock=1000
+gic=system.realview.gic
+int_delay=1000000
+int_num=53
+is_mouse=true
+pio_addr=268464128
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=520101888
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.master[4]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=100000
+system=system
+pio=system.membus.master[6]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268455936
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clock=1000
+conf_table_reported=false
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.master[1]
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clock=1000
+idreg=0
+pio_addr=268435456
+pio_latency=100000
+proc_id0=201326592
+proc_id1=201327138
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clock=1000
+gic=system.realview.gic
+int_delay=100000
+int_num=42
+pio_addr=268529664
+pio_latency=100000
+system=system
+time=Thu Jan  1 00:00:00 2009
+pio=system.iobus.master[23]
+
+[system.realview.sci_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268492800
+pio_latency=100000
+system=system
+pio=system.iobus.master[20]
+
+[system.realview.smc_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=269357056
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=true
+pio_addr=268439552
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.ssp_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268488704
+pio_latency=100000
+system=system
+pio=system.iobus.master[19]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clock=1000
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=36
+int_num1=36
+pio_addr=268505088
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clock=1000
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=37
+int_num1=37
+pio_addr=268509184
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clock=1000
+end_on_eot=false
+gic=system.realview.gic
+int_delay=100000
+int_num=44
+pio_addr=268472320
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268476416
+pio_latency=100000
+system=system
+pio=system.iobus.master[10]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268480512
+pio_latency=100000
+system=system
+pio=system.iobus.master[11]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268484608
+pio_latency=100000
+system=system
+pio=system.iobus.master[12]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268500992
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+
+[system.vncserver]
+type=VncServer
+frame_capture=false
+number=0
+port=5900
+

tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr

@@ -0,0 +1,40 @@
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+hack: be nice to actually delete the event here
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr dccimvac' unimplemented
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
+warn: LCD dual screen mode not supported
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR

tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini

@@ -0,0 +1,803 @@
+[root]
+type=Root
+children=system
+full_system=true
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+atags_addr=256
+boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+clock=1000
+dtb_filename=
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+flags_addr=268435504
+gic_cpu_addr=520093952
+init_param=0
+kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+load_addr_mask=268435455
+machine_type=RealView_PBX
+mem_mode=atomic
+mem_ranges=0:134217727
+memories=system.physmem system.realview.nvmem
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+readfile=tests/halt.sh
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.bridge]
+type=Bridge
+clock=1000
+delay=50000
+ranges=268435456:520093695 1073741824:1610612735
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img
+read_only=true
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dtb icache interrupts isa itb tracer
+checker=Null
+clock=500
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=1
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+
+[system.cpu0.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[2]
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu1]
+type=AtomicSimpleCPU
+children=dtb interrupts isa itb tracer
+checker=Null
+clock=500
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+switched_out=true
+system=system
+tracer=system.cpu1.tracer
+width=1
+workload=
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.interrupts]
+type=ArmInterrupts
+
+[system.cpu1.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=NoncoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=8
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+
+[system.iocache]
+type=BaseCache
+addr_ranges=0:134217727
+assoc=8
+block_size=64
+clock=1000
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+size=1024
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[25]
+mem_side=system.membus.slave[2]
+
+[system.l2c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.membus]
+type=CoherentBus
+children=badaddr_responder
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
+conf_table_reported=true
+in_addr_map=true
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
+null=false
+page_policy=open
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
+zero=false
+port=system.membus.master[2]
+
+[system.realview]
+type=RealView
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+intrctrl=system.intrctrl
+max_mem_size=268435456
+mem_start_addr=0
+pci_cfg_base=0
+system=system
+
+[system.realview.a9scu]
+type=A9SCU
+clock=1000
+pio_addr=520093696
+pio_latency=100000
+system=system
+pio=system.membus.master[5]
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268451840
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=402653184
+BAR0LegacyIO=true
+BAR0Size=16
+BAR1=402653440
+BAR1LegacyIO=true
+BAR1Size=1
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clock=1000
+config_latency=20000
+ctrl_offset=2
+disks=system.cf0
+io_shift=1
+pci_bus=2
+pci_dev=7
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[8]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[7]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clock=1000
+gic=system.realview.gic
+int_num=55
+pio_addr=268566528
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.dmac_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268632064
+pio_latency=100000
+system=system
+pio=system.iobus.master[9]
+
+[system.realview.flash_fake]
+type=IsaFake
+clock=1000
+fake_mem=true
+pio_addr=1073741824
+pio_latency=100000
+pio_size=536870912
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[24]
+
+[system.realview.gic]
+type=Gic
+clock=1000
+cpu_addr=520093952
+cpu_pio_delay=10000
+dist_addr=520097792
+dist_pio_delay=10000
+int_latency=10000
+it_lines=128
+platform=system.realview
+system=system
+pio=system.membus.master[3]
+
+[system.realview.gpio0_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268513280
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.gpio1_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268517376
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.realview.gpio2_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268521472
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clock=1000
+gic=system.realview.gic
+int_delay=1000000
+int_num=52
+is_mouse=false
+pio_addr=268460032
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[5]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clock=1000
+gic=system.realview.gic
+int_delay=1000000
+int_num=53
+is_mouse=true
+pio_addr=268464128
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=520101888
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.master[4]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=100000
+system=system
+pio=system.membus.master[6]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268455936
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clock=1000
+conf_table_reported=false
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.master[1]
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clock=1000
+idreg=0
+pio_addr=268435456
+pio_latency=100000
+proc_id0=201326592
+proc_id1=201327138
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clock=1000
+gic=system.realview.gic
+int_delay=100000
+int_num=42
+pio_addr=268529664
+pio_latency=100000
+system=system
+time=Thu Jan  1 00:00:00 2009
+pio=system.iobus.master[23]
+
+[system.realview.sci_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268492800
+pio_latency=100000
+system=system
+pio=system.iobus.master[20]
+
+[system.realview.smc_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=269357056
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=true
+pio_addr=268439552
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.ssp_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268488704
+pio_latency=100000
+system=system
+pio=system.iobus.master[19]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clock=1000
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=36
+int_num1=36
+pio_addr=268505088
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clock=1000
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=37
+int_num1=37
+pio_addr=268509184
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clock=1000
+end_on_eot=false
+gic=system.realview.gic
+int_delay=100000
+int_num=44
+pio_addr=268472320
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268476416
+pio_latency=100000
+system=system
+pio=system.iobus.master[10]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268480512
+pio_latency=100000
+system=system
+pio=system.iobus.master[11]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268484608
+pio_latency=100000
+system=system
+pio=system.iobus.master[12]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268500992
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+
+[system.vncserver]
+type=VncServer
+frame_capture=false
+number=0
+port=5900
+

tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr

@@ -0,0 +1,22 @@
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr dccimvac' unimplemented
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
+hack: be nice to actually delete the event here
+warn: LCD dual screen mode not supported
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR

tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt

@@ -0,0 +1,689 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  2.332810                       # Number of seconds simulated
+sim_ticks                                2332810256000                       # Number of ticks simulated
+final_tick                               2332810256000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 669803                       # Simulator instruction rate (inst/s)
+host_op_rate                                   861325                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            25865872844                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 384756                       # Number of bytes of host memory used
+host_seconds                                    90.19                       # Real time elapsed on the host
+sim_insts                                    60408639                       # Number of instructions simulated
+sim_ops                                      77681819                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           492704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          6494800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           212416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2577132                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            121450716                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       492704                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       212416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          705120                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3703040                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1405784                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       1610060                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6718884                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      13959168                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             13901                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            101515                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              3319                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             40278                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              14118186                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57860                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           351446                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           402515                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               811821                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47870736                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker            55                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            82                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              211206                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             2784110                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               91056                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1104733                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                52061978                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         211206                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          91056                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             302262                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1587373                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             602614                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data             690180                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2880167                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1587373                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47870736                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker           55                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           82                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             211206                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3386724                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              91056                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1794913                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54942145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                             0                       # Total number of read requests seen
+system.physmem.writeReqs                            0                       # Total number of write requests seen
+system.physmem.cpureqs                              0                       # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead                            0                       # Total number of bytes read from memory
+system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
+system.physmem.bytesConsumedRd                      0                       # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
+system.physmem.perBankRdReqs::0                     0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1                     0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2                     0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3                     0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4                     0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5                     0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6                     0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7                     0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8                     0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9                     0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10                    0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11                    0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12                    0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13                    0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14                    0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15                    0                       # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
+system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
+system.physmem.totGap                               0                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::6                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
+system.physmem.writePktSize::0                      0                       # categorize write packet sizes
+system.physmem.writePktSize::1                      0                       # categorize write packet sizes
+system.physmem.writePktSize::2                      0                       # categorize write packet sizes
+system.physmem.writePktSize::3                      0                       # categorize write packet sizes
+system.physmem.writePktSize::4                      0                       # categorize write packet sizes
+system.physmem.writePktSize::5                      0                       # categorize write packet sizes
+system.physmem.writePktSize::6                      0                       # categorize write packet sizes
+system.physmem.writePktSize::7                      0                       # categorize write packet sizes
+system.physmem.writePktSize::8                      0                       # categorize write packet sizes
+system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::6                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
+system.physmem.rdQLenPdf::0                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.totQLat                              0                       # Total cycles spent in queuing delays
+system.physmem.totMemAccLat                         0                       # Sum of mem lat for all requests
+system.physmem.totBusLat                            0                       # Total cycles spent in databus access
+system.physmem.totBankLat                           0                       # Total cycles spent in bank access
+system.physmem.avgQLat                            nan                       # Average queueing delay per request
+system.physmem.avgBankLat                         nan                       # Average bank access latency per request
+system.physmem.avgBusLat                          nan                       # Average bus latency per request
+system.physmem.avgMemAccLat                       nan                       # Average memory access latency
+system.physmem.avgRdBW                           0.00                       # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW                   0.00                       # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
+system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil                           0.00                       # Data bus utilization in percentage
+system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
+system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
+system.physmem.readRowHits                          0                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                     nan                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.avgGap                             nan                       # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst            9                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                9                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst            9                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst            9                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         62242                       # number of replacements
+system.l2c.tagsinuse                     50006.300216                       # Cycle average of tags in use
+system.l2c.total_refs                         1678484                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        127627                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         13.151480                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                  2316901485000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        36900.571426                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker       0.993823                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker       0.993931                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          4917.298425                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          3152.525316                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          2097.421528                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          2936.495766                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.563058                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker      0.000015                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.itb.walker      0.000015                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.075032                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.048104                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.032004                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.044807                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.763036                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker         9005                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         3277                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             473131                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             196969                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         4875                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         2050                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             365740                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             169794                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1224841                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          592682                       # number of Writeback hits
+system.l2c.Writeback_hits::total               592682                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data              12                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              14                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            63335                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            50403                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               113738                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          9005                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          3277                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              473131                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              260304                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          4875                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          2050                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              365740                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              220197                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1338579                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         9005                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         3277                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             473131                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             260304                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         4875                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         2050                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             365740                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             220197                       # number of overall hits
+system.l2c.overall_hits::total                1338579                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker            2                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker            3                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             7285                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             5807                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             3319                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             4065                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                20481                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          1520                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1399                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2919                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          96488                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          36984                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133472                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker            2                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              7285                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            102295                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              3319                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             41049                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                153953                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker            2                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             7285                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           102295                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             3319                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            41049                       # number of overall misses
+system.l2c.overall_misses::total               153953                       # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         9007                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         3280                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         480416                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         202776                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         4875                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         2050                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         369059                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         173859                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1245322                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       592682                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           592682                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         1532                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         1413                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2945                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       159823                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        87387                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247210                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         9007                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         3280                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          480416                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          362599                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         4875                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         2050                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          369059                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          261246                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1492532                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         9007                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         3280                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         480416                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         362599                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         4875                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         2050                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         369059                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         261246                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1492532                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000222                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000915                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.015164                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.028638                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.008993                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.023381                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016446                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.992167                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.990092                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.991171                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.603718                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.423221                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.539913                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000222                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000915                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.015164                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.282116                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.008993                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.157128                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.103149                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000222                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000915                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.015164                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.282116                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.008993                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.157128                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.103149                       # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks::writebacks               57860                       # number of writebacks
+system.l2c.writebacks::total                    57860                       # number of writebacks
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
+system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
+system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
+system.cpu0.dtb.read_hits                     7929195                       # DTB read hits
+system.cpu0.dtb.read_misses                      6442                       # DTB read misses
+system.cpu0.dtb.write_hits                    6437090                       # DTB write hits
+system.cpu0.dtb.write_misses                     1931                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1168                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid                752                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    5576                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   136                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults                      240                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 7935637                       # DTB read accesses
+system.cpu0.dtb.write_accesses                6439021                       # DTB write accesses
+system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
+system.cpu0.dtb.hits                         14366285                       # DTB hits
+system.cpu0.dtb.misses                           8373                       # DTB misses
+system.cpu0.dtb.accesses                     14374658                       # DTB accesses
+system.cpu0.itb.inst_hits                    32543252                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3703                       # ITB inst misses
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
+system.cpu0.itb.flush_tlb                        1168                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid                752                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    2636                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.inst_accesses                32546955                       # ITB inst accesses
+system.cpu0.itb.hits                         32543252                       # DTB hits
+system.cpu0.itb.misses                           3703                       # DTB misses
+system.cpu0.itb.accesses                     32546955                       # DTB accesses
+system.cpu0.numCycles                      4633589645                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.committedInsts                   31998088                       # Number of instructions committed
+system.cpu0.committedOps                     41901559                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             37065460                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5364                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1207172                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4285544                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    37065460                       # number of integer instructions
+system.cpu0.num_fp_insts                         5364                       # number of float instructions
+system.cpu0.num_int_register_reads          188704130                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          39536951                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3938                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1428                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     15013039                       # number of memory refs
+system.cpu0.num_load_insts                    8304652                       # Number of load instructions
+system.cpu0.num_store_insts                   6708387                       # Number of store instructions
+system.cpu0.num_idle_cycles              186586242.606667                       # Number of idle cycles
+system.cpu0.num_busy_cycles              4447003402.393333                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.959732                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.040268                       # Percentage of idle cycles
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.quiesce                   82795                       # number of quiesce instructions executed
+system.cpu0.icache.replacements                850590                       # number of replacements
+system.cpu0.icache.tagsinuse               511.678593                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                60583498                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                851102                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 71.182418                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle            5709380500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   444.509138                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu1.inst    67.169455                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.868182                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu1.inst     0.131190                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.999372                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     32064737                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     28518761                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       60583498                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     32064737                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     28518761                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        60583498                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     32064737                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     28518761                       # number of overall hits
+system.cpu0.icache.overall_hits::total       60583498                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       481294                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       369808                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       851102                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       481294                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       369808                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        851102                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       481294                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       369808                       # number of overall misses
+system.cpu0.icache.overall_misses::total       851102                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     32546031                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     28888569                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     61434600                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     32546031                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     28888569                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     61434600                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     32546031                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     28888569                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     61434600                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014788                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.012801                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.013854                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014788                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.012801                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.013854                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014788                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.012801                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.013854                       # miss rate for overall accesses
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.replacements                623333                       # number of replacements
+system.cpu0.dcache.tagsinuse               511.997031                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                23628287                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                623845                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 37.875253                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle              21763000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   451.298859                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu1.data    60.698172                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.881443                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu1.data     0.118551                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.999994                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6995578                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      6184445                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       13180023                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5776851                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      4185214                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       9962065                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139290                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        96746                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       236036                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       145936                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       101282                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       247218                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     12772429                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     10369659                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        23142088                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     12772429                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     10369659                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       23142088                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       196129                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       169323                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       365452                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       161355                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        88800                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       250155                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6647                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         4536                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        11183                       # number of LoadLockedReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       357484                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       258123                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        615607                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       357484                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       258123                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       615607                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7191707                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      6353768                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     13545475                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5938206                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      4274014                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10212220                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       145937                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       101282                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       247219                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       145936                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       101282                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       247218                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     13129913                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     10627782                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     23757695                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     13129913                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     10627782                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     23757695                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.027272                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.026649                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.026980                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027172                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.020777                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.024496                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.045547                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044786                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.045235                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027227                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024288                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.025912                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027227                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.024288                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.025912                       # miss rate for overall accesses
+system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks       592682                       # number of writebacks
+system.cpu0.dcache.writebacks::total           592682                       # number of writebacks
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
+system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
+system.cpu1.dtb.read_hits                     7038607                       # DTB read hits
+system.cpu1.dtb.read_misses                      4222                       # DTB read misses
+system.cpu1.dtb.write_hits                    4778914                       # DTB write hits
+system.cpu1.dtb.write_misses                     1250                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1166                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid                687                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    2949                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                    80                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults                      212                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 7042829                       # DTB read accesses
+system.cpu1.dtb.write_accesses                4780164                       # DTB write accesses
+system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
+system.cpu1.dtb.hits                         11817521                       # DTB hits
+system.cpu1.dtb.misses                           5472                       # DTB misses
+system.cpu1.dtb.accesses                     11822993                       # DTB accesses
+system.cpu1.itb.inst_hits                    28886893                       # ITB inst hits
+system.cpu1.itb.inst_misses                      2463                       # ITB inst misses
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
+system.cpu1.itb.flush_tlb                        1166                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid                687                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                    1597                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.inst_accesses                28889356                       # ITB inst accesses
+system.cpu1.itb.hits                         28886893                       # DTB hits
+system.cpu1.itb.misses                           2463                       # DTB misses
+system.cpu1.itb.accesses                     28889356                       # DTB accesses
+system.cpu1.numCycles                      4279954910                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.committedInsts                   28410551                       # Number of instructions committed
+system.cpu1.committedOps                     35780260                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             31730145                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  4905                       # Number of float alu accesses
+system.cpu1.num_func_calls                     928836                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      3656569                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    31730145                       # number of integer instructions
+system.cpu1.num_fp_insts                         4905                       # number of float instructions
+system.cpu1.num_int_register_reads          160620144                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          34566657                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                3555                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1352                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                     12348598                       # number of memory refs
+system.cpu1.num_load_insts                    7334875                       # Number of load instructions
+system.cpu1.num_store_insts                   5013723                       # Number of store instructions
+system.cpu1.num_idle_cycles              8315278953.102118                       # Number of idle cycles
+system.cpu1.num_busy_cycles              -4035324043.102118                       # Number of busy cycles
+system.cpu1.not_idle_fraction               -0.942843                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    1.942843                       # Percentage of idle cycles
+system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+system.iocache.replacements                         0                       # number of replacements
+system.iocache.tagsinuse                            0                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
+system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
+system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------

tests/run.py

@@ -93,6 +93,16 @@ def require_sim_object(name, fatal=False):
         else:
             skip_test(msg)
 
+def run_test(root):
+    """Default run_test implementations. Scripts can override it."""
+
+    # instantiate configuration
+    m5.instantiate()
+
+    # simulate until program terminates
+    exit_event = m5.simulate(maxtick)
+    print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
+
 # Since we're in batch mode, dont allow tcp socket connections
 m5.disableAllListeners()
 
@@ -160,10 +170,4 @@ for sysattr in [ "system", "testsys", "drivesys" ]:
     if hasattr(root, sysattr):
         initCPUs(getattr(root, sysattr))
 
-# instantiate configuration
+run_test(root)
-m5.instantiate()
-
-# simulate until program terminates
-exit_event = m5.simulate(maxtick)
-
-print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()