arm: Merge ISA files with pseudo instructions
This changeset moves the pseudo instructions used to signal unknown instructions and unimplemented instructions to the same source files as the decoder fault.
This commit is contained in:
Andreas Sandberg
parent
4eff4fa12e
commit
5bfa7e3d59
6 changed files with 205 additions and 267 deletions
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@ -11,6 +11,9 @@
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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@ -35,6 +38,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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* Stephen Hines
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*/
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#include "arch/arm/insts/pseudo.hh"
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@ -99,3 +103,100 @@ DecoderFaultInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("gem5fault %s", faultName());
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}
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FailUnimplemented::FailUnimplemented(const char *_mnemonic,
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ExtMachInst _machInst)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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FailUnimplemented::FailUnimplemented(const char *_mnemonic,
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ExtMachInst _machInst,
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const std::string& _fullMnemonic)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass),
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fullMnemonic(_fullMnemonic)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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Fault
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FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
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{
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return std::make_shared<UndefinedInstruction>(machInst, false, mnemonic);
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}
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std::string
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FailUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s (unimplemented)",
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fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
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}
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WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
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ExtMachInst _machInst)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
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ExtMachInst _machInst,
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const std::string& _fullMnemonic)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false),
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fullMnemonic(_fullMnemonic)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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Fault
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WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
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{
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if (!warned) {
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warn("\tinstruction '%s' unimplemented\n",
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fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
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warned = true;
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}
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return NoFault;
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}
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std::string
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WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s (unimplemented)",
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fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
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}
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FlushPipeInst::FlushPipeInst(const char *_mnemonic, ExtMachInst _machInst)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass)
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{
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flags[IsNonSpeculative] = true;
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}
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Fault
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FlushPipeInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
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{
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Fault fault = std::make_shared<FlushPipe>();
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return fault;
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}
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std::string
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FlushPipeInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s (pipe flush)", mnemonic);
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}
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@ -11,6 +11,9 @@
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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@ -35,6 +38,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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* Stephen Hines
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*/
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#ifndef __ARCH_ARM_INSTS_PSEUDO_HH__
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@ -57,5 +61,71 @@ class DecoderFaultInst : public ArmStaticInst
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Static instruction class for unimplemented instructions that
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* cause simulator termination. Note that these are recognized
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* (legal) instructions that the simulator does not support; the
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* 'Unknown' class is used for unrecognized/illegal instructions.
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* This is a leaf class.
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*/
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class FailUnimplemented : public ArmStaticInst
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{
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private:
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/// Full mnemonic for MRC and MCR instructions including the
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/// coproc. register name
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std::string fullMnemonic;
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public:
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FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
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FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
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const std::string& _fullMnemonic);
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Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for unimplemented instructions that cause a warning
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* to be printed (but do not terminate simulation). This
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* implementation is a little screwy in that it will print a
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* warning for each instance of a particular unimplemented machine
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* instruction, not just for each unimplemented opcode. Should
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* probably make the 'warned' flag a static member of the derived
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* class.
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*/
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class WarnUnimplemented : public ArmStaticInst
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{
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private:
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/// Have we warned on this instruction yet?
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mutable bool warned;
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/// Full mnemonic for MRC and MCR instructions including the
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/// coproc. register name
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std::string fullMnemonic;
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public:
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WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
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WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
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const std::string& _fullMnemonic);
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Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class FlushPipeInst : public ArmStaticInst
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{
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public:
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FlushPipeInst(const char *_mnemonic, ExtMachInst _machInst);
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Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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#endif
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@ -68,12 +68,6 @@
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//Miscellaneous instructions that don't fit elsewhere
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##include "misc.isa"
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//Include the unimplemented format
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##include "unimp.isa"
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//Include the unknown format
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##include "unknown.isa"
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//Include the breakpoint format
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##include "breakpoint.isa"
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@ -12,6 +12,9 @@
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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@ -36,9 +39,40 @@
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Andreas Sandberg
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// Stephen Hines
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////////////////////////////////////////////////////////////////////
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//
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// Internal fault handling
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//
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def format DecoderFault() {{
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decode_block = '''
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return new DecoderFaultInst(machInst);
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'''
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Unknown instruction handling
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//
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def format Unknown() {{
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decode_block = 'return new Unknown(machInst);\n'
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Unimplemented instructions
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//
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def format FailUnimpl() {{
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iop = InstObjParams(name, 'FailUnimplemented')
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decode_block = BasicDecodeWithMnemonic.subst(iop)
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}};
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def format WarnUnimpl() {{
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iop = InstObjParams(name, 'WarnUnimplemented')
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decode_block = BasicDecodeWithMnemonic.subst(iop)
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}};
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@ -1,215 +0,0 @@
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// -*- mode:c++ -*-
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// Copyright (c) 2010, 2012 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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////////////////////////////////////////////////////////////////////
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//
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// Unimplemented instructions
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//
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output header {{
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/**
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* Static instruction class for unimplemented instructions that
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* cause simulator termination. Note that these are recognized
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* (legal) instructions that the simulator does not support; the
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* 'Unknown' class is used for unrecognized/illegal instructions.
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* This is a leaf class.
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*/
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class FailUnimplemented : public ArmStaticInst
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{
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public:
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/// Full mnemonic for MRC and MCR instructions including the
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/// coproc. register name
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std::string fullMnemonic;
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/// Constructor
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FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
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const std::string& _fullMnemonic)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass),
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fullMnemonic(_fullMnemonic)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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%(BasicExecDeclare)s
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for unimplemented instructions that cause a warning
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* to be printed (but do not terminate simulation). This
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* implementation is a little screwy in that it will print a
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* warning for each instance of a particular unimplemented machine
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* instruction, not just for each unimplemented opcode. Should
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* probably make the 'warned' flag a static member of the derived
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* class.
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*/
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class WarnUnimplemented : public ArmStaticInst
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{
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private:
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/// Have we warned on this instruction yet?
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mutable bool warned;
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/// Full mnemonic for MRC and MCR instructions including the
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/// coproc. register name
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std::string fullMnemonic;
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public:
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/// Constructor
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WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
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const std::string& _fullMnemonic)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false),
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fullMnemonic(_fullMnemonic)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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%(BasicExecDeclare)s
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class FlushPipeInst : public ArmStaticInst
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{
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public:
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FlushPipeInst(const char *_mnemonic, ExtMachInst _machInst)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass)
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{
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flags[IsNonSpeculative] = true;
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}
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%(BasicExecDeclare)s
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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FailUnimplemented::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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return csprintf("%-10s (unimplemented)",
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fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
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}
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std::string
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WarnUnimplemented::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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return csprintf("%-10s (unimplemented)",
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fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
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}
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std::string
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FlushPipeInst::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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return csprintf("%-10s (pipe flush)", mnemonic);
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}
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}};
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output exec {{
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Fault
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FailUnimplemented::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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return std::make_shared<UndefinedInstruction>(machInst, false,
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mnemonic);
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}
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Fault
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WarnUnimplemented::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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if (!warned) {
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warn("\tinstruction '%s' unimplemented\n",
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fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
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warned = true;
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}
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return NoFault;
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}
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Fault
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FlushPipeInst::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = std::make_shared<FlushPipe>();
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return fault;
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}
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}};
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def format FailUnimpl() {{
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iop = InstObjParams(name, 'FailUnimplemented')
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decode_block = BasicDecodeWithMnemonic.subst(iop)
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}};
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def format WarnUnimpl() {{
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iop = InstObjParams(name, 'WarnUnimplemented')
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decode_block = BasicDecodeWithMnemonic.subst(iop)
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}};
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@ -1,46 +0,0 @@
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// -*- mode:c++ -*-
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|
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
|
||||
//
|
||||
// The license below extends only to copyright in the software and shall
|
||||
// not be construed as granting a license to any other intellectual
|
||||
// property including but not limited to intellectual property relating
|
||||
// to a hardware implementation of the functionality of the software
|
||||
// licensed hereunder. You may use the software subject to the license
|
||||
// terms below provided that you ensure that this notice is replicated
|
||||
// unmodified and in its entirety in all distributions of the software,
|
||||
// modified or unmodified, in source code or in binary form.
|
||||
//
|
||||
// Copyright (c) 2007-2008 The Florida State University
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Stephen Hines
|
||||
|
||||
def format Unknown() {{
|
||||
decode_block = 'return new Unknown(machInst);\n'
|
||||
}};
|
||||
|
||||
Loading…
Reference in a new issue