stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
This commit is contained in:
Steve Reinhardt
parent
b085db84af
commit
5b08e211ab
118 changed files with 31777 additions and 31361 deletions
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@ -15,17 +15,18 @@ boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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cache_line_size=64
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clk_domain=system.clk_domain
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console=/dist/binaries/console
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console=/home/stever/m5/m5_system_2.0b3/binaries/console
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eventq_index=0
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init_param=0
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kernel=/dist/binaries/vmlinux
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kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
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load_addr_mask=1099511627775
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load_offset=0
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mem_mode=timing
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mem_ranges=0:134217727
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memories=system.physmem
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num_work_ids=16
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pal=/dist/binaries/ts_osfpal
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readfile=tests/halt.sh
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pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
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readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
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symbolfile=
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system_rev=1024
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system_type=34
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@ -131,6 +132,7 @@ smtLSQThreshold=100
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smtNumFetchingThreads=1
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smtROBPolicy=Partitioned
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smtROBThreshold=100
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socket_id=0
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squashWidth=8
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store_set_clear_period=250000
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switched_out=false
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@ -636,6 +638,7 @@ smtLSQThreshold=100
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smtNumFetchingThreads=1
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smtROBPolicy=Partitioned
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smtROBThreshold=100
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socket_id=0
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squashWidth=8
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store_set_clear_period=250000
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switched_out=false
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@ -1091,7 +1094,7 @@ table_size=65536
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[system.disk0.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/dist/disks/linux-latest.img
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image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
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read_only=true
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[system.disk2]
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@ -1114,7 +1117,7 @@ table_size=65536
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[system.disk2.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/dist/disks/linux-bigswap2.img
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image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
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read_only=true
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[system.intrctrl]
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@ -1235,9 +1238,9 @@ warn_access=
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pio=system.membus.default
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[system.physmem]
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type=SimpleDRAM
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type=DRAMCtrl
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activation_limit=4
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addr_mapping=RaBaChCo
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addr_mapping=RoRaBaChCo
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banks_per_rank=8
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burst_length=8
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channels=1
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@ -1248,27 +1251,33 @@ device_rowbuffer_size=1024
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devices_per_rank=8
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eventq_index=0
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in_addr_map=true
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max_accesses_per_row=16
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mem_sched_policy=frfcfs
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min_writes_per_switch=16
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null=false
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page_policy=open
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page_policy=open_adaptive
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range=0:134217727
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ranks_per_channel=2
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read_buffer_size=32
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static_backend_latency=10000
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static_frontend_latency=10000
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tBURST=5000
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tCK=1250
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tCL=13750
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tRAS=35000
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tRCD=13750
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tREFI=7800000
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tRFC=300000
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tRFC=260000
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tRP=13750
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tRRD=6250
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tRRD=6000
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tRTP=7500
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tRTW=2500
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tWR=15000
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tWTR=7500
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tXAW=40000
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write_buffer_size=32
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write_high_thresh_perc=70
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write_low_thresh_perc=0
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tXAW=30000
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write_buffer_size=64
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write_high_thresh_perc=85
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write_low_thresh_perc=50
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port=system.membus.master[1]
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[system.simple_disk]
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@ -1281,7 +1290,7 @@ system=system
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[system.simple_disk.disk]
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type=RawDiskImage
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eventq_index=0
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image_file=/dist/disks/linux-latest.img
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image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
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read_only=true
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[system.terminal]
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@ -2,3 +2,4 @@ warn: Sockets disabled, not accepting terminal connections
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warn: Sockets disabled, not accepting gdb connections
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warn: Prefetch instructions in Alpha do not do anything
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warn: Prefetch instructions in Alpha do not do anything
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warn: Obsolete M5 ivlb instruction encountered.
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@ -1,13 +1,15 @@
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Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
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Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jan 22 2014 16:27:55
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gem5 started Jan 22 2014 19:30:57
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gem5 executing on u200540-lin
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
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gem5 compiled Jun 21 2014 10:36:29
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gem5 started Jun 21 2014 13:05:58
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gem5 executing on phenom
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/binaries/vmlinux
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info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
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0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
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info: Entering event queue @ 0. Starting simulation...
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info: Launching CPU 1 @ 126320000
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Exiting @ tick 1903338216000 because m5_exit instruction encountered
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info: Launching CPU 1 @ 121062000
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Exiting @ tick 1906207240000 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
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memcluster 1, usage 0, start 392, end 16384
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freeing pages 1069:16384
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reserving pages 1069:1070
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4096K Bcache detected; load hit latency 30 cycles, load miss latency 134 cycles
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4096K Bcache detected; load hit latency 30 cycles, load miss latency 140 cycles
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SMP: 2 CPUs probed -- cpu_present_mask = 3
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Built 1 zonelists
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Kernel command line: root=/dev/hda1 console=ttyS0
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@ -15,17 +15,18 @@ boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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cache_line_size=64
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clk_domain=system.clk_domain
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console=/dist/binaries/console
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console=/home/stever/m5/m5_system_2.0b3/binaries/console
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eventq_index=0
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init_param=0
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kernel=/dist/binaries/vmlinux
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kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
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load_addr_mask=1099511627775
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load_offset=0
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mem_mode=timing
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mem_ranges=0:134217727
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memories=system.physmem
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num_work_ids=16
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pal=/dist/binaries/ts_osfpal
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readfile=tests/halt.sh
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pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
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readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
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symbolfile=
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system_rev=1024
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system_type=34
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@ -131,6 +132,7 @@ smtLSQThreshold=100
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smtNumFetchingThreads=1
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smtROBPolicy=Partitioned
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smtROBThreshold=100
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socket_id=0
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squashWidth=8
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store_set_clear_period=250000
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switched_out=false
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@ -632,7 +634,7 @@ table_size=65536
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[system.disk0.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/dist/disks/linux-latest.img
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image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
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read_only=true
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[system.disk2]
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@ -655,7 +657,7 @@ table_size=65536
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[system.disk2.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/dist/disks/linux-bigswap2.img
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image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
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read_only=true
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[system.intrctrl]
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@ -741,9 +743,9 @@ warn_access=
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pio=system.membus.default
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[system.physmem]
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type=SimpleDRAM
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type=DRAMCtrl
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activation_limit=4
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addr_mapping=RaBaChCo
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addr_mapping=RoRaBaChCo
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banks_per_rank=8
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burst_length=8
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channels=1
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@ -754,27 +756,33 @@ device_rowbuffer_size=1024
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devices_per_rank=8
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eventq_index=0
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in_addr_map=true
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max_accesses_per_row=16
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mem_sched_policy=frfcfs
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min_writes_per_switch=16
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null=false
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page_policy=open
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page_policy=open_adaptive
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range=0:134217727
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ranks_per_channel=2
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read_buffer_size=32
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static_backend_latency=10000
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static_frontend_latency=10000
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tBURST=5000
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tCK=1250
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tCL=13750
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tRAS=35000
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tRCD=13750
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tREFI=7800000
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tRFC=300000
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tRFC=260000
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tRP=13750
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tRRD=6250
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tRRD=6000
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tRTP=7500
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tRTW=2500
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tWR=15000
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tWTR=7500
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tXAW=40000
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write_buffer_size=32
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write_high_thresh_perc=70
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write_low_thresh_perc=0
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tXAW=30000
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write_buffer_size=64
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write_high_thresh_perc=85
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write_low_thresh_perc=50
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port=system.membus.master[1]
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[system.simple_disk]
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@ -787,7 +795,7 @@ system=system
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[system.simple_disk.disk]
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type=RawDiskImage
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eventq_index=0
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image_file=/dist/disks/linux-latest.img
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image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
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read_only=true
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[system.terminal]
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@ -1,12 +1,14 @@
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Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
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Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jan 22 2014 16:27:55
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gem5 started Jan 22 2014 19:25:00
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gem5 executing on u200540-lin
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
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gem5 compiled Jun 21 2014 10:36:29
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gem5 started Jun 21 2014 13:05:52
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gem5 executing on phenom
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/binaries/vmlinux
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info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
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0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 1860197780500 because m5_exit instruction encountered
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Exiting @ tick 1860172195000 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
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memcluster 1, usage 0, start 392, end 16384
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freeing pages 1069:16384
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reserving pages 1069:1070
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4096K Bcache detected; load hit latency 30 cycles, load miss latency 134 cycles
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4096K Bcache detected; load hit latency 30 cycles, load miss latency 140 cycles
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SMP: 1 CPUs probed -- cpu_present_mask = 1
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Built 1 zonelists
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Kernel command line: root=/dev/hda1 console=ttyS0
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@ -15,17 +15,18 @@ boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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cache_line_size=64
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clk_domain=system.clk_domain
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console=/dist/binaries/console
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console=/home/stever/m5/m5_system_2.0b3/binaries/console
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eventq_index=0
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init_param=0
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kernel=/dist/binaries/vmlinux
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kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
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load_addr_mask=1099511627775
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load_offset=0
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mem_mode=atomic
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mem_ranges=0:134217727
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memories=system.physmem
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num_work_ids=16
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pal=/dist/binaries/ts_osfpal
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readfile=tests/halt.sh
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pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
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readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
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symbolfile=
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system_rev=1024
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system_type=34
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@ -58,6 +59,7 @@ voltage_domain=system.voltage_domain
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[system.cpu0]
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type=AtomicSimpleCPU
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children=dcache dtb icache interrupts isa itb tracer
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branchPred=Null
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checker=Null
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clk_domain=system.cpu_clk_domain
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cpu_id=0
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@ -85,6 +87,7 @@ simpoint_profile_file=simpoint.bb.gz
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simpoint_start_insts=
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simulate_data_stalls=false
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simulate_inst_stalls=false
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socket_id=0
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switched_out=false
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system=system
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tracer=system.cpu0.tracer
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@ -189,6 +192,7 @@ eventq_index=0
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[system.cpu1]
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type=TimingSimpleCPU
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children=dtb isa itb tracer
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branchPred=Null
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checker=Null
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clk_domain=system.cpu_clk_domain
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cpu_id=0
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@ -210,6 +214,7 @@ numThreads=1
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profile=0
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progress_interval=0
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simpoint_start_insts=
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socket_id=0
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switched_out=true
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system=system
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tracer=system.cpu1.tracer
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@ -310,6 +315,7 @@ smtLSQThreshold=100
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smtNumFetchingThreads=1
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smtROBPolicy=Partitioned
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smtROBThreshold=100
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socket_id=0
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squashWidth=8
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store_set_clear_period=250000
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switched_out=true
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@ -689,7 +695,7 @@ table_size=65536
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[system.disk0.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/dist/disks/linux-latest.img
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image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
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read_only=true
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[system.disk2]
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@ -712,7 +718,7 @@ table_size=65536
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[system.disk2.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/dist/disks/linux-bigswap2.img
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image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
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read_only=true
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[system.intrctrl]
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@ -833,9 +839,9 @@ warn_access=
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pio=system.membus.default
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[system.physmem]
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type=SimpleDRAM
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type=DRAMCtrl
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activation_limit=4
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addr_mapping=RaBaChCo
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addr_mapping=RoRaBaChCo
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banks_per_rank=8
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burst_length=8
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channels=1
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@ -846,27 +852,33 @@ device_rowbuffer_size=1024
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devices_per_rank=8
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eventq_index=0
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in_addr_map=true
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max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
|
|
@ -879,7 +891,7 @@ system=system
|
|||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/dist/disks/linux-latest.img
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
|
|||
|
|
@ -1,9 +1,11 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:27:55
|
||||
gem5 started Jan 22 2014 19:37:21
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
|
||||
gem5 compiled Jun 21 2014 10:36:29
|
||||
gem5 started Jun 21 2014 13:11:51
|
||||
gem5 executing on phenom
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
boot_release_addr=65528
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -30,19 +30,19 @@ have_security=false
|
|||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
load_offset=0
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem system.realview.nvmem
|
||||
memories=system.realview.nvmem system.physmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=tests/halt.sh
|
||||
readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -85,7 +85,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/dist/disks/linux-arm-ael.img
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -172,6 +172,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -228,6 +229,7 @@ numThreads=1
|
|||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.checker.tracer
|
||||
|
|
@ -980,9 +982,9 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -993,27 +995,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
|
|
|
|||
|
|
@ -10,20 +10,21 @@ warn: instruction 'mcr icialluis' unimplemented
|
|||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: 6176053500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
|
||||
warn: 6184767500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
|
||||
warn: 6220839500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
|
||||
warn: 6236327500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
|
||||
warn: 6779610500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
|
||||
warn: 6127336500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
|
||||
warn: 6135886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
|
||||
warn: 6171724500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
|
||||
warn: 6187045500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
|
||||
warn: 6729690500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: 51874115000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
|
||||
warn: 2476169247000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
|
||||
warn: 2490093200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2491309014500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
|
||||
warn: 2512521404000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2513043156000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2517323856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10
|
||||
warn: 2518814467000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
|
||||
warn: 2519896624000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
|
||||
warn: 2519897721500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
|
||||
warn: 2520452967000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
|
||||
warn: 51815926000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
|
||||
warn: 2464496392000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
|
||||
warn: 2490035144500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2491240940500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
|
||||
warn: 2491596722500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
|
||||
warn: 2505538162500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
|
||||
warn: 2507237495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
|
||||
warn: 2512436106000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2512950831500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2518637805000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
|
||||
warn: 2519704735000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
|
||||
warn: 2519705958000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
|
||||
|
|
|
|||
|
|
@ -1,15 +1,15 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 18:47:40
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 21:27:42
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
0: system.cpu.checker.isa: ISA system set to: 0x645a800 0x645a800
|
||||
0: system.cpu.isa: ISA system set to: 0x645a800 0x645a800
|
||||
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
0: system.cpu.checker.isa: ISA system set to: 0x639d990 0x639d990
|
||||
0: system.cpu.isa: ISA system set to: 0x639d990 0x639d990
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Using kernel entry physical address at 0x8000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2526146947500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2525888859000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
boot_release_addr=65528
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -30,7 +30,7 @@ have_security=false
|
|||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
load_offset=0
|
||||
machine_type=RealView_PBX
|
||||
|
|
@ -42,7 +42,7 @@ num_work_ids=16
|
|||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=tests/halt.sh
|
||||
readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -85,7 +85,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/dist/disks/linux-arm-ael.img
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -172,6 +172,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -775,6 +776,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -1423,9 +1425,9 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -1436,27 +1438,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
|
|
|
|||
|
|
@ -1,15 +1,15 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 18:56:34
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 21:27:42
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
0: system.cpu0.isa: ISA system set to: 0x6856800 0x6856800
|
||||
0: system.cpu1.isa: ISA system set to: 0x6856800 0x6856800
|
||||
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
0: system.cpu0.isa: ISA system set to: 0x628e100 0x628e100
|
||||
0: system.cpu1.isa: ISA system set to: 0x628e100 0x628e100
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Using kernel entry physical address at 0x8000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2605645191500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2605245500000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Binary file not shown.
|
|
@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
boot_release_addr=65528
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -30,7 +30,7 @@ have_security=false
|
|||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
load_offset=0
|
||||
machine_type=RealView_PBX
|
||||
|
|
@ -42,7 +42,7 @@ num_work_ids=16
|
|||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=tests/halt.sh
|
||||
readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -85,7 +85,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/dist/disks/linux-arm-ael.img
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -172,6 +172,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -831,9 +832,9 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -844,27 +845,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 18:42:01
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 21:27:42
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
0: system.cpu.isa: ISA system set to: 0x6dd8800 0x6dd8800
|
||||
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
0: system.cpu.isa: ISA system set to: 0x4e2f380 0x4e2f380
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Using kernel entry physical address at 0x8000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2526146947500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2525888859000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Binary file not shown.
|
|
@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
boot_release_addr=65528
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -30,7 +30,7 @@ have_security=false
|
|||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
load_offset=0
|
||||
machine_type=RealView_PBX
|
||||
|
|
@ -42,7 +42,7 @@ num_work_ids=16
|
|||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=tests/halt.sh
|
||||
readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -85,7 +85,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/dist/disks/linux-arm-ael.img
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -97,6 +97,7 @@ voltage_domain=system.voltage_domain
|
|||
[system.cpu0]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
|
|
@ -126,6 +127,7 @@ simpoint_profile_file=simpoint.bb.gz
|
|||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
|
|
@ -326,6 +328,7 @@ eventq_index=0
|
|||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
children=dstage2_mmu dtb isa istage2_mmu itb tracer
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
|
|
@ -349,6 +352,7 @@ numThreads=1
|
|||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=true
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
|
|
@ -543,6 +547,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=true
|
||||
|
|
@ -1111,9 +1116,9 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -1124,27 +1129,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 19:05:28
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 21:27:42
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu0.isa: ISA system set to: 0x5606400 0x5606400
|
||||
0: system.cpu1.isa: ISA system set to: 0x5606400 0x5606400
|
||||
0: system.cpu2.isa: ISA system set to: 0x5606400 0x5606400
|
||||
0: system.cpu0.isa: ISA system set to: 0x61c8fe0 0x61c8fe0
|
||||
0: system.cpu1.isa: ISA system set to: 0x61c8fe0 0x61c8fe0
|
||||
0: system.cpu2.isa: ISA system set to: 0x61c8fe0 0x61c8fe0
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Binary file not shown.
|
|
@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
boot_release_addr=65528
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -30,7 +30,7 @@ have_security=false
|
|||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
load_offset=0
|
||||
machine_type=RealView_PBX
|
||||
|
|
@ -42,7 +42,7 @@ num_work_ids=16
|
|||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=tests/halt.sh
|
||||
readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -85,7 +85,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/dist/disks/linux-arm-ael.img
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -172,6 +172,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -775,6 +776,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=true
|
||||
|
|
@ -1343,9 +1345,9 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -1356,27 +1358,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 19:10:32
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 21:27:42
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu0.isa: ISA system set to: 0x6aaf400 0x6aaf400
|
||||
0: system.cpu1.isa: ISA system set to: 0x6aaf400 0x6aaf400
|
||||
0: system.cpu0.isa: ISA system set to: 0x60c5390 0x60c5390
|
||||
0: system.cpu1.isa: ISA system set to: 0x60c5390 0x60c5390
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Binary file not shown.
|
|
@ -20,13 +20,14 @@ eventq_index=0
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
|
||||
smbios_table=system.smbios_table
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -161,6 +162,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -1535,7 +1537,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/dist/disks/linux-x86.img
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -1558,7 +1560,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/dist/disks/linux-bigswap2.img
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
@ -1747,9 +1749,9 @@ system=system
|
|||
pio=system.iobus.master[9]
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -1760,27 +1762,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[3]
|
||||
|
||||
[system.smbios_table]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 17:10:34
|
||||
gem5 started Jan 22 2014 22:15:55
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
|
||||
gem5 compiled Jun 21 2014 11:13:07
|
||||
gem5 started Jun 21 2014 22:16:40
|
||||
gem5 executing on phenom
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9
|
||||
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5133933067000 because m5_exit instruction encountered
|
||||
Exiting @ tick 5137926173000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -28,7 +28,7 @@ Built 1 zonelists. Total pages: 30612
|
|||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
time.c: Detected 2000.008 MHz processor.
|
||||
time.c: Detected 1999.999 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
|
|
@ -44,7 +44,7 @@ ACPI: Core revision 20070126
|
|||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812560
|
||||
result 7812524
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
|
|
|
|||
|
|
@ -20,14 +20,14 @@ eventq_index=0
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=/z/stever/hg/gem5/tests/halt.sh
|
||||
readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
|
||||
smbios_table=system.smbios_table
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -1597,7 +1597,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/dist/m5/system/disks/linux-x86.img
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -1620,7 +1620,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ warn: Reading current count from inactive timer.
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: x86 cpuid: unknown family 0xbacc
|
||||
warn: x86 cpuid: unknown family 0xbacc
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
warn: x86 cpuid: unimplemented function 8
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled May 12 2014 12:50:47
|
||||
gem5 started May 12 2014 15:35:34
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /z/stever/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
|
||||
gem5 compiled Jun 21 2014 11:13:07
|
||||
gem5 started Jun 21 2014 22:18:32
|
||||
gem5 executing on phenom
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -44,7 +44,7 @@ ACPI: Core revision 20070126
|
|||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812444
|
||||
result 7812464
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
|
|
|
|||
|
|
@ -118,6 +118,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -698,9 +699,9 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/arm/linux/mcf
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -727,9 +728,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -740,27 +741,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 17:10:45
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 21:33:12
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu.isa: ISA system set to: 0 0x50d0380
|
||||
0: system.cpu.isa: ISA system set to: 0 0x666d940
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
MCF SPEC version 1.6.I
|
||||
|
|
@ -24,4 +24,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 26911921000 because target called exit()
|
||||
Exiting @ tick 26894328500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -18,6 +18,7 @@ eventq_index=0
|
|||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
|
|
@ -115,6 +116,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -632,9 +634,9 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -661,9 +663,9 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s
|
|||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -674,27 +676,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 17:10:34
|
||||
gem5 started Jan 22 2014 19:53:01
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||
gem5 compiled Jun 21 2014 11:13:07
|
||||
gem5 started Jun 21 2014 16:50:55
|
||||
gem5 executing on phenom
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -24,4 +26,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 65613727000 because target called exit()
|
||||
Exiting @ tick 64361067000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -118,6 +118,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -698,9 +699,9 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/arm/linux/parser
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -727,9 +728,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -740,27 +741,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 17:14:04
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 21:42:28
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu.isa: ISA system set to: 0 0x4cfd380
|
||||
0: system.cpu.isa: ISA system set to: 0 0x6824800
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
Reading the dictionary files: *************************************************
|
||||
|
|
@ -68,4 +68,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 202696649500 because target called exit()
|
||||
Exiting @ tick 201639641000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -18,6 +18,7 @@ eventq_index=0
|
|||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
|
|
@ -115,6 +116,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -632,9 +634,9 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/x86/linux/parser
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -661,9 +663,9 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s
|
|||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -674,27 +676,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,17 +1,28 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 15 2014 16:30:59
|
||||
gem5 started Feb 16 2014 01:49:09
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
gem5 compiled Jun 21 2014 11:13:07
|
||||
gem5 started Jun 21 2014 22:34:22
|
||||
gem5 executing on phenom
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
Reading the dictionary files: *********info: Increasing stack size by one page.
|
||||
****************************************
|
||||
info: Increasing stack size by one page.
|
||||
******************************info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
**********
|
||||
58924 words stored in 3784810 bytes
|
||||
|
||||
|
||||
|
|
@ -23,8 +34,6 @@ Processing sentences in batch mode
|
|||
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -74,11 +83,9 @@ info: Increasing stack size by one page.
|
|||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 459118646000 because target called exit()
|
||||
Exiting @ tick 456433328000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -18,6 +18,7 @@ eventq_index=0
|
|||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
|
|
@ -115,6 +116,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -599,7 +601,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/alpha/tru64/eon
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -628,9 +630,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -641,27 +643,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,14 +1,16 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:27:55
|
||||
gem5 started Jan 22 2014 17:48:27
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
|
||||
gem5 compiled Jun 21 2014 10:36:29
|
||||
gem5 started Jun 21 2014 11:54:16
|
||||
gem5 executing on phenom
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Eon, Version 1.1
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.066667
|
||||
Exiting @ tick 77516381000 because target called exit()
|
||||
Exiting @ tick 72880000500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -118,6 +118,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -698,7 +699,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/arm/linux/eon
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -727,9 +728,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -740,27 +741,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,5 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: CP14 unimplemented crn[15], opc1[7], crm[4], opc2[6]
|
||||
getting pixel output filename pixels_out.cook
|
||||
opening control file chair.control.cook
|
||||
opening camera file chair.camera
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 17:23:42
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 21:42:59
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu.isa: ISA system set to: 0 0x4718040
|
||||
0: system.cpu.isa: ISA system set to: 0 0x6560400
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Eon, Version 1.1
|
||||
|
|
@ -14,4 +14,4 @@ info: Increasing stack size by one page.
|
|||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.060000
|
||||
Exiting @ tick 68503867000 because target called exit()
|
||||
Exiting @ tick 64766858000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -18,6 +18,7 @@ eventq_index=0
|
|||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
|
|
@ -115,6 +116,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -599,7 +601,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -628,9 +630,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -641,27 +643,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:27:55
|
||||
gem5 started Jan 22 2014 17:50:38
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
|
||||
gem5 compiled Jun 21 2014 10:36:29
|
||||
gem5 started Jun 21 2014 21:27:33
|
||||
gem5 executing on phenom
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 631518097500 because target called exit()
|
||||
Exiting @ tick 635929494500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -118,6 +118,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -698,7 +699,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/arm/linux/perlbmk
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -727,9 +728,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -740,27 +741,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 17:31:04
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 21:43:02
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu.isa: ISA system set to: 0 0x4c3a340
|
||||
0: system.cpu.isa: ISA system set to: 0 0x5c9e4b0
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -1386,4 +1386,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 629535413500 because target called exit()
|
||||
Exiting @ tick 634728078000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -18,6 +18,7 @@ eventq_index=0
|
|||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
|
|
@ -115,6 +116,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -599,7 +601,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -628,9 +630,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -641,27 +643,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,11 +1,13 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:27:55
|
||||
gem5 started Jan 22 2014 18:24:06
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
|
||||
gem5 compiled Jun 21 2014 10:36:29
|
||||
gem5 started Jun 21 2014 12:22:04
|
||||
gem5 executing on phenom
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 24876941500 because target called exit()
|
||||
Exiting @ tick 24220559500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -118,6 +118,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -698,7 +699,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/arm/linux/vortex
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -727,9 +728,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -740,27 +741,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,2 +1 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: CP14 unimplemented crn[15], opc1[7], crm[8], opc2[4]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 17:54:40
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 21:43:42
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu.isa: ISA system set to: 0 0x5a6c340
|
||||
0: system.cpu.isa: ISA system set to: 0 0x62769a0
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 26790388000 because target called exit()
|
||||
Exiting @ tick 25431292500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -18,6 +18,7 @@ eventq_index=0
|
|||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
|
|
@ -115,6 +116,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -599,7 +601,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/alpha/tru64/bzip2
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -628,9 +630,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -641,27 +643,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:27:55
|
||||
gem5 started Jan 22 2014 18:30:51
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
|
||||
gem5 compiled Jun 21 2014 10:36:29
|
||||
gem5 started Jun 21 2014 16:50:46
|
||||
gem5 executing on phenom
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -23,4 +25,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 685386545000 because target called exit()
|
||||
Exiting @ tick 679349778000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -118,6 +118,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -698,7 +699,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/arm/linux/bzip2
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -727,9 +728,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -740,27 +741,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 18:05:55
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 21:45:58
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu.isa: ISA system set to: 0 0x5017340
|
||||
0: system.cpu.isa: ISA system set to: 0 0x5287000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
Loading Input Data
|
||||
|
|
@ -25,4 +25,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 533761922000 because target called exit()
|
||||
Exiting @ tick 523063504500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -18,6 +18,7 @@ eventq_index=0
|
|||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
|
|
@ -115,6 +116,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -599,7 +601,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/alpha/tru64/twolf
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -628,9 +630,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -641,27 +643,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:27:55
|
||||
gem5 started Jan 22 2014 19:15:16
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
|
||||
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
|
||||
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
|
||||
gem5 compiled Jun 21 2014 10:36:29
|
||||
gem5 started Jun 21 2014 12:55:52
|
||||
gem5 executing on phenom
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 23461709500 because target called exit()
|
||||
122 123 124 Exiting @ tick 23058360500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -118,6 +118,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -698,7 +699,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/arm/linux/twolf
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -727,9 +728,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -740,27 +741,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 18:25:13
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 21:53:28
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu.isa: ISA system set to: 0 0x5949040
|
||||
0: system.cpu.isa: ISA system set to: 0 0x4f074c0
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
|
||||
|
|
@ -22,4 +22,4 @@ info: Increasing stack size by one page.
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 74219931000 because target called exit()
|
||||
122 123 124 Exiting @ tick 74056845500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -18,6 +18,7 @@ eventq_index=0
|
|||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
|
|
@ -115,6 +116,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -632,7 +634,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/x86/linux/twolf
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -661,9 +663,9 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s
|
|||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -674,27 +676,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 17:10:34
|
||||
gem5 started Jan 22 2014 21:43:52
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
|
||||
gem5 compiled Jun 21 2014 11:13:07
|
||||
gem5 started Jun 21 2014 22:44:43
|
||||
gem5 executing on phenom
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
|
||||
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
|
||||
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -24,4 +24,4 @@ info: Increasing stack size by one page.
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 144463317000 because target called exit()
|
||||
122 123 124 Exiting @ tick 145782984000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -18,6 +18,7 @@ eventq_index=0
|
|||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
|
|
@ -115,6 +116,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -599,7 +601,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -628,9 +630,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -641,27 +643,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:27:55
|
||||
gem5 started Jan 22 2014 17:24:08
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
|
||||
gem5 compiled Jun 21 2014 10:36:29
|
||||
gem5 started Jun 21 2014 10:37:19
|
||||
gem5 executing on phenom
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 21065000 because target called exit()
|
||||
Exiting @ tick 21025000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -18,6 +18,7 @@ eventq_index=0
|
|||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
|
|
@ -115,6 +116,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -599,7 +601,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -628,9 +630,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -641,27 +643,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:27:55
|
||||
gem5 started Jan 22 2014 17:24:20
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
|
||||
gem5 compiled Jun 21 2014 10:36:29
|
||||
gem5 started Jun 21 2014 10:38:16
|
||||
gem5 executing on phenom
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 11990500 because target called exit()
|
||||
Exiting @ tick 11975500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu
|
|||
sim_ticks 11975500 # Number of ticks simulated
|
||||
final_tick 11975500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 56599 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 56579 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 283759448 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 265424 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_inst_rate 28986 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 28981 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 145369893 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 220536 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_ops 2387 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -238,40 +238,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17472 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 344500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2556250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 2554750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.3 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 1176 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 619 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 1179 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 620 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 804 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 253 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 806 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 254 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 31.467662 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 31.513648 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 212 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 37 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 710 # DTB read hits
|
||||
system.cpu.dtb.read_hits 712 # DTB read hits
|
||||
system.cpu.dtb.read_misses 31 # DTB read misses
|
||||
system.cpu.dtb.read_acv 1 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 741 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 743 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 368 # DTB write hits
|
||||
system.cpu.dtb.write_misses 20 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 388 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 1078 # DTB hits
|
||||
system.cpu.dtb.data_hits 1080 # DTB hits
|
||||
system.cpu.dtb.data_misses 51 # DTB misses
|
||||
system.cpu.dtb.data_acv 1 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 1129 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 1065 # ITB hits
|
||||
system.cpu.dtb.data_accesses 1131 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 1070 # ITB hits
|
||||
system.cpu.itb.fetch_misses 30 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 1095 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 1100 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -288,93 +288,92 @@ system.cpu.workload.num_syscalls 4 # Nu
|
|||
system.cpu.numCycles 23952 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 4342 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 7011 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 1176 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 1209 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 531 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 7041 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 1179 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 466 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 1215 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 872 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 516 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 1065 # Number of cache lines fetched
|
||||
system.cpu.fetch.CacheLines 1070 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 7705 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.909929 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.316850 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 7706 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.913704 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.320621 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 6496 84.31% 84.31% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 53 0.69% 85.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 115 1.49% 86.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 95 1.23% 87.72% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 176 2.28% 90.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 76 0.99% 90.99% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 64 0.83% 91.82% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 65 0.84% 92.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 565 7.33% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 6491 84.23% 84.23% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 53 0.69% 84.92% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 117 1.52% 86.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 96 1.25% 87.68% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 176 2.28% 89.97% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 76 0.99% 90.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 64 0.83% 91.79% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 66 0.86% 92.64% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 567 7.36% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 7705 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.049098 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.292710 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5480 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 569 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 1153 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch
|
||||
system.cpu.fetch.rateDist::total 7706 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.049223 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.293963 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5479 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 562 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 1164 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 4 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 497 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 166 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 6199 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 6225 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 5578 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking
|
||||
system.cpu.rename.SquashCycles 497 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 5576 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 257 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 280 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 1063 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 5900 # Number of instructions processed by rename
|
||||
system.cpu.rename.RunCycles 1068 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 28 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 5913 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 13 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 4279 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 6674 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 6667 # Number of integer rename lookups
|
||||
system.cpu.rename.IQFullEvents 20 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RenamedOperands 4287 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 6690 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 6683 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 2511 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 2519 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 139 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 956 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 469 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.rename.skidInsts 93 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 957 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 470 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 4966 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 4974 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 4045 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 4048 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 2341 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1389 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 2349 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1396 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 7705 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.524984 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.239779 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 7706 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.525305 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.241065 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 6081 78.92% 78.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 6082 78.93% 78.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 565 7.33% 86.26% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 401 5.20% 91.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 263 3.41% 94.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 200 2.60% 97.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 120 1.56% 99.03% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 47 0.61% 99.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 198 2.57% 97.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 121 1.57% 99.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 48 0.62% 99.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 7705 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 7706 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available
|
||||
|
|
@ -410,7 +409,7 @@ system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 2864 70.80% 70.80% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 2866 70.80% 70.80% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.83% # Type of FU issued
|
||||
|
|
@ -439,40 +438,40 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.83% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 785 19.41% 90.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 395 9.77% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 786 19.42% 90.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 395 9.76% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 4045 # Type of FU issued
|
||||
system.cpu.iq.rate 0.168879 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 4048 # Type of FU issued
|
||||
system.cpu.iq.rate 0.169005 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 44 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.010878 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 15880 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 7311 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 3652 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fu_busy_rate 0.010870 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 15887 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 7327 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 3655 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 4082 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 4085 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 541 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 542 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 175 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 176 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 228 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 5308 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewSquashCycles 497 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 231 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 5316 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 956 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 469 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispLoadInsts 957 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 470 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
|
|
@ -480,31 +479,31 @@ system.cpu.iew.memOrderViolationEvents 4 # Nu
|
|||
system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 162 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 215 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 3855 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 742 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 190 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 3860 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 744 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 188 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 336 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 1130 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_refs 1132 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 644 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 388 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.160947 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 3738 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 3658 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1710 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2211 # num instructions consuming a value
|
||||
system.cpu.iew.exec_rate 0.161156 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 3742 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 3661 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1713 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2215 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.152722 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.773406 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.152847 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.773363 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 2726 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 2734 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 7211 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.357232 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.199732 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 7209 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.357331 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.199884 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 6342 87.95% 87.95% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 6340 87.95% 87.95% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 204 2.83% 90.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 308 4.27% 95.05% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 114 1.58% 96.63% # Number of insts commited each cycle
|
||||
|
|
@ -516,7 +515,7 @@ system.cpu.commit.committed_per_cycle::8 63 0.87% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 7211 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 7209 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 2576 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -564,18 +563,18 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% #
|
|||
system.cpu.commit.op_class_0::total 2576 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 12203 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 11111 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 12209 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 11130 # The number of ROB writes
|
||||
system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 16247 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 16246 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 10.034353 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 10.034353 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.099658 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.099658 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 4672 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2825 # number of integer regfile writes
|
||||
system.cpu.int_regfile_reads 4676 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2829 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
|
|
@ -599,56 +598,56 @@ system.cpu.toL2Bus.respLayer0.utilization 2.6 # L
|
|||
system.cpu.toL2Bus.respLayer1.occupancy 133500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 93.052511 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 815 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 93.052678 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 820 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4.335106 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4.361702 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 93.052511 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 93.052678 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.045436 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.045436 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.091797 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 2318 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 2318 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 815 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 815 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 815 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 815 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 815 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 815 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 2328 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 2328 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 820 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 820 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 820 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 820 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 820 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 820 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 250 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17506249 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17506249 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17506249 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17506249 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17506249 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17506249 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1065 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1065 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1065 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1065 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1065 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1065 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234742 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.234742 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.234742 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.234742 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.234742 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.234742 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70024.996000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70024.996000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70024.996000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70024.996000 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17505249 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17505249 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17505249 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17505249 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17505249 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17505249 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1070 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1070 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1070 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1070 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1070 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1070 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233645 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.233645 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.233645 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.233645 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.233645 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.233645 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70020.996000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70020.996000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70020.996000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70020.996000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70020.996000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70020.996000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
|
|
@ -669,33 +668,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 188
|
|||
system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13110499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13110499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13110499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13110499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13110499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13110499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176526 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.176526 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.176526 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69736.696809 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69736.696809 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13109499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13109499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13109499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13109499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13109499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13109499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175701 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175701 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175701 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.175701 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175701 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.175701 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69731.377660 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69731.377660 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69731.377660 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 69731.377660 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69731.377660 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 69731.377660 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 121.888429 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 121.888470 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.250749 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.637680 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.250833 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.637638 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002846 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000874 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003720 # Average percentage of cache occupancy
|
||||
|
|
@ -716,17 +715,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 273 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12921750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4652500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 17574250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12920750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4652000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 17572750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1688000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1688000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 12921750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6340500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 19262250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 12921750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6340500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 19262250 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 12920750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6340000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 19260750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 12920750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6340000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 19260750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -749,17 +748,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68732.712766 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76270.491803 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70579.317269 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68727.393617 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76262.295082 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70573.293173 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70333.333333 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70333.333333 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70557.692308 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70557.692308 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68727.393617 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74588.235294 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70552.197802 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68727.393617 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74588.235294 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70552.197802 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -815,9 +814,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58044.871795
|
|||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 45.583444 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 759 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 761 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 8.929412 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 8.952941 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 45.583444 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011129 # Average percentage of cache occupancy
|
||||
|
|
@ -826,16 +825,16 @@ system.cpu.dcache.tags.occ_task_id_blocks::1024 85
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1995 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1995 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 546 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 546 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 1999 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1999 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 548 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 548 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 759 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 759 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 759 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 759 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 761 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 761 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 761 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 761 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
|
||||
|
|
@ -852,22 +851,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 13179000
|
|||
system.cpu.dcache.demand_miss_latency::total 13179000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13179000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13179000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 661 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 661 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 955 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 955 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 955 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 955 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.173979 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.173979 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 957 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 957 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 957 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 957 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.173454 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.173454 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.205236 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.205236 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.205236 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.205236 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.204807 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.204807 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.204807 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.204807 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68493.478261 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 68493.478261 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65459.876543 # average WriteReq miss latency
|
||||
|
|
@ -900,30 +899,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85
|
|||
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4713500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4713500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4713000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4713000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6427000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6427000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6427000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6427000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6426500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6426500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089005 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.089005 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089005 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.089005 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77270.491803 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77270.491803 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088819 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.088819 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088819 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.088819 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77262.295082 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77262.295082 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71395.833333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71395.833333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75605.882353 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75605.882353 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75605.882353 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75605.882353 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -118,6 +118,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -174,6 +175,7 @@ numThreads=1
|
|||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.checker.tracer
|
||||
|
|
@ -847,7 +849,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/test-progs/hello/bin/arm/linux/hello
|
||||
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -876,9 +878,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -889,27 +891,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,13 +1,15 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 17:05:52
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 11:25:19
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu.checker.isa: ISA system set to: 0 0x5d826c0
|
||||
0: system.cpu.isa: ISA system set to: 0 0x5d826c0
|
||||
0: system.cpu.checker.isa: ISA system set to: 0 0x54ee6d0
|
||||
0: system.cpu.isa: ISA system set to: 0 0x54ee6d0
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
Exiting @ tick 16981000 because target called exit()
|
||||
Exiting @ tick 16786000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -118,6 +118,7 @@ smtLSQThreshold=100
|
|||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
|
|
@ -698,7 +699,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/dist/test-progs/hello/bin/arm/linux/hello
|
||||
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -727,9 +728,9 @@ master=system.physmem.port
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
type=DRAMCtrl
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
addr_mapping=RoRaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -740,27 +741,33 @@ device_rowbuffer_size=1024
|
|||
devices_per_rank=8
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open
|
||||
page_policy=open_adaptive
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6250
|
||||
tRRD=6000
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_high_thresh_perc=70
|
||||
write_low_thresh_perc=0
|
||||
tXAW=30000
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2014 12:08:08
|
||||
gem5 started Jan 23 2014 17:05:41
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
|
||||
gem5 compiled Jun 21 2014 11:22:42
|
||||
gem5 started Jun 21 2014 11:25:21
|
||||
gem5 executing on phenom
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu.isa: ISA system set to: 0 0x578c380
|
||||
0: system.cpu.isa: ISA system set to: 0 0x4e56660
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
Exiting @ tick 16981000 because target called exit()
|
||||
Exiting @ tick 16786000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
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Reference in a new issue