MOESI_hammer: tbe allocation and dependent wakeup fixes
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@ -1481,6 +1481,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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transition(SR, {Load, Ifetch}, S) {
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transition(SR, {Load, Ifetch}, S) {
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h_load_hit;
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h_load_hit;
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k_popMandatoryQueue;
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k_popMandatoryQueue;
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ka_wakeUpAllDependents;
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}
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}
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transition({S, SR}, Store, SM) {
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transition({S, SR}, Store, SM) {
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@ -1525,6 +1526,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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transition(OR, {Load, Ifetch}, O) {
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transition(OR, {Load, Ifetch}, O) {
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h_load_hit;
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h_load_hit;
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k_popMandatoryQueue;
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k_popMandatoryQueue;
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ka_wakeUpAllDependents;
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}
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}
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transition({O, OR}, Store, OM) {
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transition({O, OR}, Store, OM) {
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@ -1569,16 +1571,28 @@ machine(L1Cache, "AMD Hammer-like protocol")
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}
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}
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// Transitions from Modified
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// Transitions from Modified
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transition({MM, MMR}, {Load, Ifetch}, MM) {
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transition({MM, M}, {Load, Ifetch}) {
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h_load_hit;
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h_load_hit;
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k_popMandatoryQueue;
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k_popMandatoryQueue;
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}
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}
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transition({MM, MMR}, Store, MM) {
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transition(MM, Store) {
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hh_store_hit;
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hh_store_hit;
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k_popMandatoryQueue;
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k_popMandatoryQueue;
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}
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}
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transition(MMR, {Load, Ifetch}, MM) {
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h_load_hit;
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k_popMandatoryQueue;
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ka_wakeUpAllDependents;
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}
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transition(MMR, Store, MM) {
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hh_store_hit;
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k_popMandatoryQueue;
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ka_wakeUpAllDependents;
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}
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transition({MM, M, MMR, MR}, Flush_line, MM_F) {
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transition({MM, M, MMR, MR}, Flush_line, MM_F) {
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i_allocateTBE;
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i_allocateTBE;
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bf_issueGETF;
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bf_issueGETF;
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@ -1630,14 +1644,21 @@ machine(L1Cache, "AMD Hammer-like protocol")
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}
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}
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// Transitions from Dirty Exclusive
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// Transitions from Dirty Exclusive
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transition({M, MR}, {Load, Ifetch}, M) {
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transition(M, Store, MM) {
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h_load_hit;
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hh_store_hit;
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k_popMandatoryQueue;
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k_popMandatoryQueue;
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}
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}
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transition({M, MR}, Store, MM) {
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transition(MR, {Load, Ifetch}, M) {
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h_load_hit;
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k_popMandatoryQueue;
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ka_wakeUpAllDependents;
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}
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transition(MR, Store, MM) {
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hh_store_hit;
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hh_store_hit;
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k_popMandatoryQueue;
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k_popMandatoryQueue;
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ka_wakeUpAllDependents;
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}
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}
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transition(M, L2_Replacement, MI) {
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transition(M, L2_Replacement, MI) {
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@ -542,6 +542,7 @@ machine(Directory, "AMD Hammer-like protocol")
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}
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}
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action(v_allocateTBE, "v", desc="Allocate TBE") {
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action(v_allocateTBE, "v", desc="Allocate TBE") {
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check_allocate(TBEs);
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peek(requestQueue_in, RequestMsg) {
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peek(requestQueue_in, RequestMsg) {
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TBEs.allocate(address);
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TBEs.allocate(address);
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set_tbe(TBEs[address]);
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set_tbe(TBEs[address]);
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@ -551,6 +552,7 @@ machine(Directory, "AMD Hammer-like protocol")
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}
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}
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action(vd_allocateDmaRequestInTBE, "vd", desc="Record Data in TBE") {
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action(vd_allocateDmaRequestInTBE, "vd", desc="Record Data in TBE") {
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check_allocate(TBEs);
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peek(dmaRequestQueue_in, DMARequestMsg) {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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TBEs.allocate(address);
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TBEs.allocate(address);
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set_tbe(TBEs[address]);
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set_tbe(TBEs[address]);
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@ -1258,6 +1260,8 @@ machine(Directory, "AMD Hammer-like protocol")
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peek(unblockNetwork_in, ResponseMsg) {
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peek(unblockNetwork_in, ResponseMsg) {
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assert(in_msg.Dirty == false);
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assert(in_msg.Dirty == false);
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assert(in_msg.MessageSize == MessageSizeType:Writeback_Control);
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assert(in_msg.MessageSize == MessageSizeType:Writeback_Control);
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DPRINTF(RubySlicc, "%s\n", in_msg.DataBlk);
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DPRINTF(RubySlicc, "%s\n", getDirectoryEntry(address).DataBlk);
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// NOTE: The following check would not be valid in a real
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// NOTE: The following check would not be valid in a real
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// implementation. We include the data in the "dataless"
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// implementation. We include the data in the "dataless"
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