From 5838ed7290461a253587d854226758b84afbb54d Mon Sep 17 00:00:00 2001
From: Brad Beckmann <Brad.Beckmann@amd.com>
Date: Fri, 6 Apr 2012 13:47:07 -0700
Subject: [PATCH] MOESI_hammer: tbe allocation and dependent wakeup fixes

---
 src/mem/protocol/MOESI_hammer-cache.sm | 31 +++++++++++++++++++++-----
 src/mem/protocol/MOESI_hammer-dir.sm   |  4 ++++
 2 files changed, 30 insertions(+), 5 deletions(-)

diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index 219096d26..1fe353ce5 100644
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -1481,6 +1481,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   transition(SR, {Load, Ifetch}, S) {
     h_load_hit;
     k_popMandatoryQueue;
+    ka_wakeUpAllDependents;
   }
 
   transition({S, SR}, Store, SM) {
@@ -1525,6 +1526,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   transition(OR, {Load, Ifetch}, O) {
     h_load_hit;
     k_popMandatoryQueue;
+    ka_wakeUpAllDependents;
   }
 
   transition({O, OR}, Store, OM) {
@@ -1569,16 +1571,28 @@ machine(L1Cache, "AMD Hammer-like protocol")
   }
 
   // Transitions from Modified
-  transition({MM, MMR}, {Load, Ifetch}, MM) {
+  transition({MM, M}, {Load, Ifetch}) {
     h_load_hit;
     k_popMandatoryQueue;
   }
 
-  transition({MM, MMR}, Store, MM) {
+  transition(MM, Store) {
     hh_store_hit;
     k_popMandatoryQueue;
   }
 
+  transition(MMR, {Load, Ifetch}, MM) {
+    h_load_hit;
+    k_popMandatoryQueue;
+    ka_wakeUpAllDependents;
+  }
+
+  transition(MMR, Store, MM) {
+    hh_store_hit;
+    k_popMandatoryQueue;
+    ka_wakeUpAllDependents;
+  }
+
   transition({MM, M, MMR, MR}, Flush_line, MM_F) {
     i_allocateTBE;
     bf_issueGETF;
@@ -1630,14 +1644,21 @@ machine(L1Cache, "AMD Hammer-like protocol")
   }
  
   // Transitions from Dirty Exclusive
-  transition({M, MR}, {Load, Ifetch}, M) {
-    h_load_hit;
+  transition(M, Store, MM) {
+    hh_store_hit;
     k_popMandatoryQueue;
   }
 
-  transition({M, MR}, Store, MM) {
+  transition(MR, {Load, Ifetch}, M) {
+    h_load_hit;
+    k_popMandatoryQueue;
+    ka_wakeUpAllDependents;
+  }
+
+  transition(MR, Store, MM) {
     hh_store_hit;
     k_popMandatoryQueue;
+    ka_wakeUpAllDependents;
   }
 
   transition(M, L2_Replacement, MI) {
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index 24d64349e..1fc946386 100644
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -542,6 +542,7 @@ machine(Directory, "AMD Hammer-like protocol")
   }
 
   action(v_allocateTBE, "v", desc="Allocate TBE") {
+    check_allocate(TBEs);
     peek(requestQueue_in, RequestMsg) {
       TBEs.allocate(address);
       set_tbe(TBEs[address]);
@@ -551,6 +552,7 @@ machine(Directory, "AMD Hammer-like protocol")
   }
 
   action(vd_allocateDmaRequestInTBE, "vd", desc="Record Data in TBE") {
+    check_allocate(TBEs);
     peek(dmaRequestQueue_in, DMARequestMsg) {
       TBEs.allocate(address);
       set_tbe(TBEs[address]);
@@ -1258,6 +1260,8 @@ machine(Directory, "AMD Hammer-like protocol")
     peek(unblockNetwork_in, ResponseMsg) {
       assert(in_msg.Dirty == false);
       assert(in_msg.MessageSize == MessageSizeType:Writeback_Control);
+      DPRINTF(RubySlicc, "%s\n", in_msg.DataBlk);
+      DPRINTF(RubySlicc, "%s\n", getDirectoryEntry(address).DataBlk);
 
       // NOTE: The following check would not be valid in a real
       // implementation.  We include the data in the "dataless"