ARM: Ignore reads and writes to DCIMVAC.
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@ -107,6 +107,9 @@ let {{
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case MISCREG_DCCIMVAC:
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return new WarnUnimplemented(
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isRead ? "mrc dccimvac" : "mcr dccimvac", machInst);
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case MISCREG_DCIMVAC:
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return new WarnUnimplemented(
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isRead ? "mrc dcimvac" : "mcr dcimvac", machInst);
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case MISCREG_DCCMVAC:
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return new WarnUnimplemented(
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isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
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