Add the ability for a DMA to tack on an extra delay after the DMA is actually finished.
This commit is contained in:
parent
05954e1ba7
commit
549c43b2d0
2 changed files with 18 additions and 11 deletions
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@ -138,6 +138,9 @@ DmaPort::recvTiming(PacketPtr pkt)
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state->numBytes += pkt->req->getSize();
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state->numBytes += pkt->req->getSize();
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assert(state->totBytes >= state->numBytes);
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assert(state->totBytes >= state->numBytes);
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if (state->totBytes == state->numBytes) {
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if (state->totBytes == state->numBytes) {
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if (state->delay)
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state->completionEvent->schedule(state->delay + curTick);
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else
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state->completionEvent->process();
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state->completionEvent->process();
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delete state;
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delete state;
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}
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}
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@ -216,13 +219,13 @@ DmaPort::recvRetry()
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void
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void
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DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
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DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
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uint8_t *data)
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uint8_t *data, Tick delay)
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{
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{
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assert(event);
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assert(event);
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assert(device->getState() == SimObject::Running);
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assert(device->getState() == SimObject::Running);
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DmaReqState *reqState = new DmaReqState(event, this, size);
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DmaReqState *reqState = new DmaReqState(event, this, size, delay);
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DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
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DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
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@ -314,7 +317,7 @@ DmaPort::sendDma()
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if (state->totBytes == state->numBytes) {
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if (state->totBytes == state->numBytes) {
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assert(!state->completionEvent->scheduled());
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assert(!state->completionEvent->scheduled());
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state->completionEvent->schedule(curTick + lat);
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state->completionEvent->schedule(curTick + lat + state->delay);
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delete state;
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delete state;
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delete pkt->req;
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delete pkt->req;
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}
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}
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@ -89,8 +89,12 @@ class DmaPort : public Port
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/** Number of bytes that have been acked for this transaction. */
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/** Number of bytes that have been acked for this transaction. */
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Addr numBytes;
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Addr numBytes;
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DmaReqState(Event *ce, Port *p, Addr tb)
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/** Amount to delay completion of dma by */
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: completionEvent(ce), outPort(p), totBytes(tb), numBytes(0)
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Tick delay;
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DmaReqState(Event *ce, Port *p, Addr tb, Tick _delay)
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: completionEvent(ce), outPort(p), totBytes(tb), numBytes(0),
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delay(_delay)
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{}
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{}
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};
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};
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@ -144,7 +148,7 @@ class DmaPort : public Port
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DmaPort(DmaDevice *dev, System *s);
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DmaPort(DmaDevice *dev, System *s);
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void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
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void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
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uint8_t *data = NULL);
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uint8_t *data, Tick delay);
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bool dmaPending() { return pendingCount > 0; }
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bool dmaPending() { return pendingCount > 0; }
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@ -265,14 +269,14 @@ class DmaDevice : public PioDevice
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return dynamic_cast<const Params *>(_params);
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return dynamic_cast<const Params *>(_params);
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}
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}
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void dmaWrite(Addr addr, int size, Event *event, uint8_t *data)
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void dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay = 0)
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{
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{
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dmaPort->dmaAction(MemCmd::WriteReq, addr, size, event, data);
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dmaPort->dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
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}
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}
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void dmaRead(Addr addr, int size, Event *event, uint8_t *data)
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void dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay = 0)
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{
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{
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dmaPort->dmaAction(MemCmd::ReadReq, addr, size, event, data);
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dmaPort->dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
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}
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}
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bool dmaPending() { return dmaPort->dmaPending(); }
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bool dmaPending() { return dmaPort->dmaPending(); }
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