TimingSimpleCPU: Fixed uncacacheable request read bug
Previously the recording of an uncached read occurred after the request was possibly deleted within the translateTiming function.
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@ -432,6 +432,10 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
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Addr split_addr = roundDown(addr + data_size - 1, block_size);
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assert(split_addr <= addr || split_addr - addr < block_size);
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// This will need a new way to tell if it's hooked up to a cache or not.
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if (req->isUncacheable())
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recordEvent("Uncached Write");
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_status = DTBWaitResponse;
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if (split_addr > addr) {
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RequestPtr req1, req2;
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@ -461,10 +465,6 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
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traceData->setAddr(addr);
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}
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// This will need a new way to tell if it has a dcache attached.
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if (req->isUncacheable())
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recordEvent("Uncached Read");
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return NoFault;
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}
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@ -510,7 +510,6 @@ TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
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return read(addr, *(uint32_t*)&data, flags);
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}
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template<>
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Fault
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TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
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@ -555,6 +554,10 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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Addr split_addr = roundDown(addr + data_size - 1, block_size);
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assert(split_addr <= addr || split_addr - addr < block_size);
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// This will need a new way to tell if it's hooked up to a cache or not.
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if (req->isUncacheable())
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recordEvent("Uncached Write");
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T *dataP = new T;
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*dataP = TheISA::htog(data);
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_status = DTBWaitResponse;
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@ -586,10 +589,6 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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traceData->setData(data);
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}
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// This will need a new way to tell if it's hooked up to a cache or not.
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if (req->isUncacheable())
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recordEvent("Uncached Write");
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// If the write needs to have a fault on the access, consider calling
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// changeStatus() and changing it to "bad addr write" or something.
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return NoFault;
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