config: Add a BaseSESystem builder for re-use in regressions
This patch extends the existing system builders to also include a syscall-emulation builder. This builder is deployed in all syscall-emulation regressions that do not involve Ruby, i.e. o3-timing, simple-timing and simple-atomic, as well as the multi-processor regressions o3-timing-mp, simple-timing-mp and simple-atomic-mp (the latter are only used by SPARC at this point). The values chosen for the cache sizes match those that were used in the existing config scripts (despite being on the large side). Similarly, a mem_class parameter is added to the builder base class to enable simple-atomic to use SimpleMemory and o3-timing to use the default DDR3 configuration. Due to the different order the ports are connected, the bus stats get shuffled around for the multi-processor regressions. A separate patch bumps the port indices. Besides this, all behaviour is exactly the same.
This commit is contained in:
Andreas Hansson
parent
597d2aa3a6
commit
4de3205afa
21 changed files with 195 additions and 274 deletions
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@ -1,4 +1,4 @@
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# Copyright (c) 2012 ARM Limited
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# Copyright (c) 2012-2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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@ -34,6 +34,7 @@
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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# Andreas Hansson
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from abc import ABCMeta, abstractmethod
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import m5
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@ -56,17 +57,19 @@ class BaseSystem(object):
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__metaclass__ = ABCMeta
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def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU,
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num_cpus=1, checker=False):
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"""Initialize a simple ARM system.
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def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
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cpu_class=TimingSimpleCPU, num_cpus=1, checker=False):
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"""Initialize a simple base system.
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Keyword Arguments:
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mem_mode -- String describing the memory mode (timing or atomic)
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mem_class -- Memory controller class to use
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cpu_class -- CPU class to use
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num_cpus -- Number of CPUs to instantiate
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checker -- Set to True to add checker CPUs
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"""
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self.mem_mode = mem_mode
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self.mem_class = mem_class
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self.cpu_class = cpu_class
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self.num_cpus = num_cpus
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self.checker = checker
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@ -153,6 +156,50 @@ class BaseSystem(object):
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defined by this class."""
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pass
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class BaseSESystem(BaseSystem):
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"""Basic syscall-emulation builder."""
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def __init__(self, **kwargs):
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BaseSystem.__init__(self, **kwargs)
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def init_system(self, system):
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BaseSystem.init_system(self, system)
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def create_system(self):
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system = System(physmem = self.mem_class(),
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membus = CoherentBus(),
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mem_mode = self.mem_mode)
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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self.init_system(system)
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return system
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def create_root(self):
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system = self.create_system()
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m5.ticks.setGlobalFrequency('1THz')
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return Root(full_system=False, system=system)
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class BaseSESystemUniprocessor(BaseSESystem):
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"""Basic syscall-emulation builder for uniprocessor systems.
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Note: This class is only really needed to provide backwards
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compatibility in existing test cases.
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"""
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def __init__(self, **kwargs):
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BaseSESystem.__init__(self, **kwargs)
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def create_caches_private(self, cpu):
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# The atomic SE configurations do not use caches
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if self.mem_mode == "timing":
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# @todo We might want to revisit these rather enthusiastic L1 sizes
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cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'),
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L1Cache(size='256kB'),
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L2Cache(size='2MB'))
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def create_caches_shared(self, system):
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return None
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class BaseFSSystem(BaseSystem):
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"""Basic full system builder."""
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@ -1,3 +1,15 @@
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# Copyright (c) 2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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@ -24,29 +36,10 @@
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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# Authors: Andreas Hansson
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import m5
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from m5.objects import *
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m5.util.addToPath('../configs/common')
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from Caches import *
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from base_config import *
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cpu = InOrderCPU(cpu_id=0)
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cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
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L1Cache(size = '256kB'),
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L2Cache(size = '2MB'))
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cpu.clock = '2GHz'
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system = System(cpu = cpu,
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physmem = DDR3_1600_x64(),
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membus = CoherentBus(),
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mem_mode = "timing")
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system.clock = '1GHz'
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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# create the interrupt controller
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cpu.createInterruptController()
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cpu.connectAllPorts(system.membus)
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root = Root(full_system = False, system = system)
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root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
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cpu_class=InOrderCPU).create_root()
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@ -1,5 +1,5 @@
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# Copyright (c) 2011 ARM Limited
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# All rights reserved
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# Copyright (c) 2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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@ -33,31 +33,11 @@
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Geoffrey Blake
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# Authors: Andreas Hansson
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import m5
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from m5.objects import *
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m5.util.addToPath('../configs/common')
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from Caches import *
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from base_config import *
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cpu = DerivO3CPU(cpu_id=0)
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cpu.createInterruptController()
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cpu.addCheckerCpu()
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cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
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L1Cache(size = '256kB'),
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L2Cache(size = '2MB'))
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# @todo Note that the L2 latency here is unmodified and 2 cycles,
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# should set hit latency and response latency to 20 cycles as for
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# other scripts
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cpu.clock = '2GHz'
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system = System(cpu = cpu,
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physmem = DDR3_1600_x64(),
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membus = CoherentBus(),
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mem_mode = "timing")
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system.clock = '1GHz'
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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cpu.connectAllPorts(system.membus)
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root = Root(full_system = False, system = system)
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root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
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cpu_class=DerivO3CPU,
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checker=True).create_root()
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@ -1,3 +1,15 @@
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# Copyright (c) 2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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@ -24,52 +36,11 @@
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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# Authors: Andreas Hansson
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import m5
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from m5.objects import *
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m5.util.addToPath('../configs/common')
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from Caches import *
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from base_config import *
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nb_cores = 4
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cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
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# system simulated
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system = System(cpu = cpus,
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physmem = DDR3_1600_x64(),
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membus = CoherentBus(),
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mem_mode = "timing")
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system.clock = '1GHz'
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# l2cache & bus
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system.toL2Bus = CoherentBus(clock = '2GHz')
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system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
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system.l2c.cpu_side = system.toL2Bus.master
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# connect l2c to membus
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system.l2c.mem_side = system.membus.slave
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# add L1 caches
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for cpu in cpus:
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cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
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L1Cache(size = '32kB', assoc = 4))
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# create the interrupt controller
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cpu.createInterruptController()
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# connect cpu level-1 caches to shared level-2 cache
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.clock = '2GHz'
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# connect memory to membus
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system.physmem.port = system.membus.master
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# connect system port to membus
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system.system_port = system.membus.slave
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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#root.trace.flags="Bus Cache"
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#root.trace.flags = "BusAddrRanges"
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root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_x64,
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cpu_class=DerivO3CPU, num_cpus=nb_cores).create_root()
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@ -1,3 +1,15 @@
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# Copyright (c) 2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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@ -24,31 +36,10 @@
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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# Authors: Andreas Hansson
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import m5
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from m5.objects import *
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m5.util.addToPath('../configs/common')
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from Caches import *
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from base_config import *
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cpu = DerivO3CPU(cpu_id=0)
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cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
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L1Cache(size = '256kB'),
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L2Cache(size = '2MB'))
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# @todo Note that the L2 latency here is unmodified and 2 cycles,
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# should set hit latency and response latency to 20 cycles as for
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# other scripts
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cpu.clock = '2GHz'
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system = System(cpu = cpu,
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physmem = DDR3_1600_x64(),
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membus = CoherentBus(),
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mem_mode = "timing")
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system.clock = '1GHz'
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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# create the interrupt controller
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cpu.createInterruptController()
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cpu.connectAllPorts(system.membus)
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root = Root(full_system = False, system = system)
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root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
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cpu_class=DerivO3CPU).create_root()
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# Copyright (c) 2011 ARM Limited
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# All rights reserved
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# Copyright (c) 2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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@ -33,20 +33,11 @@
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Geoffrey Blake
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# Authors: Andreas Hansson
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import m5
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from m5.objects import *
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from base_config import *
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system = System(cpu = AtomicSimpleCPU(cpu_id=0),
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physmem = SimpleMemory(),
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membus = CoherentBus())
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system.clock = '1GHz'
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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system.cpu.addCheckerCpu()
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system.cpu.createInterruptController()
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system.cpu.connectAllPorts(system.membus)
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system.cpu.clock = '2GHz'
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root = Root(full_system = False, system = system)
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root = BaseSESystemUniprocessor(mem_mode='atomic',
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cpu_class=AtomicSimpleCPU,
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checker=True).create_root()
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@ -1,3 +1,15 @@
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# Copyright (c) 2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
|
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
|
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
|
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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@ -24,48 +36,11 @@
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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# Authors: Andreas Hansson
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import m5
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from m5.objects import *
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m5.util.addToPath('../configs/common')
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from Caches import *
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from base_config import *
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nb_cores = 4
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cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
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# system simulated
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system = System(cpu = cpus,
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physmem = SimpleMemory(range = AddrRange('1024MB')),
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membus = CoherentBus())
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system.clock = '1GHz'
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# l2cache & bus
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system.toL2Bus = CoherentBus(clock = '2GHz')
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system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
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system.l2c.cpu_side = system.toL2Bus.master
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# connect l2c to membus
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system.l2c.mem_side = system.membus.slave
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# add L1 caches
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for cpu in cpus:
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cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
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L1Cache(size = '32kB', assoc = 4))
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# create the interrupt controller
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cpu.createInterruptController()
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# connect cpu level-1 caches to shared level-2 cache
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.clock = '2GHz'
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# connect memory to membus
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system.physmem.port = system.membus.master
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# connect system port to membus
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system.system_port = system.membus.slave
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'atomic'
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root = BaseSESystem(mem_mode='atomic', cpu_class=AtomicSimpleCPU,
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num_cpus=nb_cores).create_root()
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@ -1,3 +1,15 @@
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# Copyright (c) 2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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@ -24,20 +36,10 @@
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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# Authors: Andreas Hansson
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import m5
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from m5.objects import *
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from base_config import *
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system = System(cpu = AtomicSimpleCPU(cpu_id=0),
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physmem = SimpleMemory(),
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membus = CoherentBus())
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system.clock = '1GHz'
|
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system.system_port = system.membus.slave
|
||||
system.physmem.port = system.membus.master
|
||||
# create the interrupt controller
|
||||
system.cpu.createInterruptController()
|
||||
system.cpu.connectAllPorts(system.membus)
|
||||
system.cpu.clock = '2GHz'
|
||||
|
||||
root = Root(full_system = False, system = system)
|
||||
root = BaseSESystemUniprocessor(mem_mode='atomic',
|
||||
cpu_class=AtomicSimpleCPU).create_root()
|
||||
|
|
|
|||
|
|
@ -1,3 +1,15 @@
|
|||
# Copyright (c) 2013 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
|
|
@ -24,47 +36,11 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ron Dreslinski
|
||||
# Authors: Andreas Hansson
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
from Caches import *
|
||||
from base_config import *
|
||||
|
||||
nb_cores = 4
|
||||
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
|
||||
|
||||
# system simulated
|
||||
system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
|
||||
system.clock = '1GHz'
|
||||
|
||||
# l2cache & bus
|
||||
system.toL2Bus = CoherentBus(clock = '2GHz')
|
||||
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
|
||||
system.l2c.cpu_side = system.toL2Bus.master
|
||||
|
||||
# connect l2c to membus
|
||||
system.l2c.mem_side = system.membus.slave
|
||||
|
||||
# add L1 caches
|
||||
for cpu in cpus:
|
||||
cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4))
|
||||
# create the interrupt controller
|
||||
cpu.createInterruptController()
|
||||
# connect cpu level-1 caches to shared level-2 cache
|
||||
cpu.connectAllPorts(system.toL2Bus, system.membus)
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
system.system_port = system.membus.slave
|
||||
|
||||
# connect memory to membus
|
||||
system.physmem.port = system.membus.master
|
||||
|
||||
|
||||
# -----------------------
|
||||
# run simulation
|
||||
# -----------------------
|
||||
|
||||
root = Root( full_system = False, system = system )
|
||||
root.system.mem_mode = 'timing'
|
||||
root = BaseSESystem(mem_mode='timing', cpu_class=TimingSimpleCPU,
|
||||
num_cpus=nb_cores).create_root()
|
||||
|
|
|
|||
|
|
@ -1,3 +1,15 @@
|
|||
# Copyright (c) 2013 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
|
|
@ -24,27 +36,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Hansson
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
from Caches import *
|
||||
from base_config import *
|
||||
|
||||
cpu = TimingSimpleCPU(cpu_id=0)
|
||||
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
|
||||
L1Cache(size = '256kB'),
|
||||
L2Cache(size = '2MB'))
|
||||
system = System(cpu = cpu,
|
||||
physmem = SimpleMemory(),
|
||||
membus = CoherentBus(),
|
||||
mem_mode = "timing")
|
||||
system.clock = '1GHz'
|
||||
system.system_port = system.membus.slave
|
||||
system.physmem.port = system.membus.master
|
||||
# create the interrupt controller
|
||||
cpu.createInterruptController()
|
||||
cpu.connectAllPorts(system.membus)
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=False, system = system)
|
||||
root = BaseSESystemUniprocessor(mem_mode='timing',
|
||||
cpu_class=TimingSimpleCPU).create_root()
|
||||
|
|
|
|||
|
|
@ -30,5 +30,5 @@ m5.util.addToPath('../configs/common')
|
|||
from cpu2000 import mcf
|
||||
|
||||
workload = mcf(isa, opsys, 'smred')
|
||||
root.system.cpu.workload = workload.makeLiveProcess()
|
||||
root.system.cpu[0].workload = workload.makeLiveProcess()
|
||||
root.system.physmem.range=AddrRange('256MB')
|
||||
|
|
|
|||
|
|
@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
|
|||
from cpu2000 import parser
|
||||
|
||||
workload = parser(isa, opsys, 'mdred')
|
||||
root.system.cpu.workload = workload.makeLiveProcess()
|
||||
root.system.cpu[0].workload = workload.makeLiveProcess()
|
||||
|
|
|
|||
|
|
@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
|
|||
from cpu2000 import eon_cook
|
||||
|
||||
workload = eon_cook(isa, opsys, 'mdred')
|
||||
root.system.cpu.workload = workload.makeLiveProcess()
|
||||
root.system.cpu[0].workload = workload.makeLiveProcess()
|
||||
|
|
|
|||
|
|
@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
|
|||
from cpu2000 import perlbmk_makerand
|
||||
|
||||
workload = perlbmk_makerand(isa, opsys, 'lgred')
|
||||
root.system.cpu.workload = workload.makeLiveProcess()
|
||||
root.system.cpu[0].workload = workload.makeLiveProcess()
|
||||
|
|
|
|||
|
|
@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
|
|||
from cpu2000 import vortex
|
||||
|
||||
workload = vortex(isa, opsys, 'smred')
|
||||
root.system.cpu.workload = workload.makeLiveProcess()
|
||||
root.system.cpu[0].workload = workload.makeLiveProcess()
|
||||
|
|
|
|||
|
|
@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
|
|||
from cpu2000 import bzip2_source
|
||||
|
||||
workload = bzip2_source(isa, opsys, 'lgred')
|
||||
root.system.cpu.workload = workload.makeLiveProcess()
|
||||
root.system.cpu[0].workload = workload.makeLiveProcess()
|
||||
|
|
|
|||
|
|
@ -31,8 +31,8 @@ from cpu2000 import twolf
|
|||
import os
|
||||
|
||||
workload = twolf(isa, opsys, 'smred')
|
||||
root.system.cpu.workload = workload.makeLiveProcess()
|
||||
cwd = root.system.cpu.workload[0].cwd
|
||||
root.system.cpu[0].workload = workload.makeLiveProcess()
|
||||
cwd = root.system.cpu[0].workload[0].cwd
|
||||
|
||||
#Remove two files who's presence or absence affects execution
|
||||
sav_file = os.path.join(cwd, workload.input_set + '.sav')
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
#
|
||||
# Authors: Steve Reinhardt
|
||||
|
||||
root.system.cpu.workload = LiveProcess(cmd = 'hello',
|
||||
root.system.cpu[0].workload = LiveProcess(cmd = 'hello',
|
||||
executable = binpath('hello'))
|
||||
if root.system.cpu.checker != NULL:
|
||||
root.system.cpu.checker.workload = root.system.cpu.workload
|
||||
if root.system.cpu[0].checker != NULL:
|
||||
root.system.cpu[0].checker.workload = root.system.cpu[0].workload
|
||||
|
|
|
|||
|
|
@ -29,5 +29,5 @@
|
|||
process1 = LiveProcess(cmd = 'hello', executable = binpath('hello'))
|
||||
process2 = LiveProcess(cmd = 'hello', executable = binpath('hello'))
|
||||
|
||||
root.system.cpu.workload = [process1, process2]
|
||||
root.system.cpu.numThreads = 2
|
||||
root.system.cpu[0].workload = [process1, process2]
|
||||
root.system.cpu[0].numThreads = 2
|
||||
|
|
|
|||
|
|
@ -26,5 +26,5 @@
|
|||
#
|
||||
# Authors: Ali Saidi
|
||||
|
||||
root.system.cpu.workload = LiveProcess(cmd = 'insttest',
|
||||
root.system.cpu[0].workload = LiveProcess(cmd = 'insttest',
|
||||
executable = binpath('insttest'))
|
||||
|
|
|
|||
|
|
@ -28,6 +28,6 @@
|
|||
|
||||
require_sim_object("EioProcess")
|
||||
|
||||
root.system.cpu.workload = EioProcess(file = binpath('anagram',
|
||||
root.system.cpu[0].workload = EioProcess(file = binpath('anagram',
|
||||
'anagram-vshort.eio.gz'))
|
||||
root.system.cpu.max_insts_any_thread = 500000
|
||||
root.system.cpu[0].max_insts_any_thread = 500000
|
||||
|
|
|
|||
Loading…
Reference in a new issue