diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index a4b3969ef..0cafacdda 100644
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -34,6 +34,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Andreas Sandberg
+#          Andreas Hansson
 
 from abc import ABCMeta, abstractmethod
 import m5
@@ -56,17 +57,19 @@ class BaseSystem(object):
 
     __metaclass__ = ABCMeta
 
-    def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU,
-                 num_cpus=1, checker=False):
-        """Initialize a simple ARM system.
+    def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
+                 cpu_class=TimingSimpleCPU, num_cpus=1, checker=False):
+        """Initialize a simple base system.
 
         Keyword Arguments:
           mem_mode -- String describing the memory mode (timing or atomic)
+          mem_class -- Memory controller class to use
           cpu_class -- CPU class to use
           num_cpus -- Number of CPUs to instantiate
           checker -- Set to True to add checker CPUs
         """
         self.mem_mode = mem_mode
+        self.mem_class = mem_class
         self.cpu_class = cpu_class
         self.num_cpus = num_cpus
         self.checker = checker
@@ -153,6 +156,50 @@ class BaseSystem(object):
         defined by this class."""
         pass
 
+class BaseSESystem(BaseSystem):
+    """Basic syscall-emulation builder."""
+
+    def __init__(self, **kwargs):
+        BaseSystem.__init__(self, **kwargs)
+
+    def init_system(self, system):
+        BaseSystem.init_system(self, system)
+
+    def create_system(self):
+        system = System(physmem = self.mem_class(),
+                        membus = CoherentBus(),
+                        mem_mode = self.mem_mode)
+        system.system_port = system.membus.slave
+        system.physmem.port = system.membus.master
+        self.init_system(system)
+        return system
+
+    def create_root(self):
+        system = self.create_system()
+        m5.ticks.setGlobalFrequency('1THz')
+        return Root(full_system=False, system=system)
+
+class BaseSESystemUniprocessor(BaseSESystem):
+    """Basic syscall-emulation builder for uniprocessor systems.
+
+    Note: This class is only really needed to provide backwards
+    compatibility in existing test cases.
+    """
+
+    def __init__(self, **kwargs):
+        BaseSESystem.__init__(self, **kwargs)
+
+    def create_caches_private(self, cpu):
+        # The atomic SE configurations do not use caches
+        if self.mem_mode == "timing":
+            # @todo We might want to revisit these rather enthusiastic L1 sizes
+            cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'),
+                                          L1Cache(size='256kB'),
+                                          L2Cache(size='2MB'))
+
+    def create_caches_shared(self, system):
+        return None
+
 class BaseFSSystem(BaseSystem):
     """Basic full system builder."""
 
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index 30e12f777..a5fbd7763 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,29 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
+from base_config import *
 
-cpu = InOrderCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
-                              L1Cache(size = '256kB'),
-                              L2Cache(size = '2MB'))
-
-cpu.clock = '2GHz'
-
-system = System(cpu = cpu,
-                physmem = DDR3_1600_x64(),
-                membus = CoherentBus(),
-                mem_mode = "timing")
-system.clock = '1GHz'
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-# create the interrupt controller
-cpu.createInterruptController()
-cpu.connectAllPorts(system.membus)
-
-root = Root(full_system = False, system = system)
+root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+                                cpu_class=InOrderCPU).create_root()
diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py
index 14948fc87..94131d745 100644
--- a/tests/configs/o3-timing-checker.py
+++ b/tests/configs/o3-timing-checker.py
@@ -1,5 +1,5 @@
-# Copyright (c) 2011 ARM Limited
-# All rights reserved
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
 # not be construed as granting a license to any other intellectual
@@ -33,31 +33,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Geoffrey Blake
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
+from base_config import *
 
-cpu = DerivO3CPU(cpu_id=0)
-cpu.createInterruptController()
-cpu.addCheckerCpu()
-cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
-                              L1Cache(size = '256kB'),
-                              L2Cache(size = '2MB'))
-# @todo Note that the L2 latency here is unmodified and 2 cycles,
-# should set hit latency and response latency to 20 cycles as for
-# other scripts
-cpu.clock = '2GHz'
-
-system = System(cpu = cpu,
-                physmem = DDR3_1600_x64(),
-                membus = CoherentBus(),
-                mem_mode = "timing")
-system.clock = '1GHz'
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-cpu.connectAllPorts(system.membus)
-
-root = Root(full_system = False, system = system)
+root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+                                cpu_class=DerivO3CPU,
+                                checker=True).create_root()
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 9b4f362e7..1ec4182bd 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,52 +36,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Ron Dreslinski
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
+from base_config import *
 
 nb_cores = 4
-cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
-
-# system simulated
-system = System(cpu = cpus,
-                physmem = DDR3_1600_x64(),
-                membus = CoherentBus(),
-                mem_mode = "timing")
-system.clock = '1GHz'
-
-# l2cache & bus
-system.toL2Bus = CoherentBus(clock = '2GHz')
-system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-
-# connect l2c to membus
-system.l2c.mem_side = system.membus.slave
-
-# add L1 caches
-for cpu in cpus:
-    cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
-                                L1Cache(size = '32kB', assoc = 4))
-    # create the interrupt controller
-    cpu.createInterruptController()
-    # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectAllPorts(system.toL2Bus, system.membus)
-    cpu.clock = '2GHz'
-
-# connect memory to membus
-system.physmem.port = system.membus.master
-
-# connect system port to membus
-system.system_port = system.membus.slave
-
-# -----------------------
-# run simulation
-# -----------------------
-
-root = Root( full_system = False, system = system )
-root.system.mem_mode = 'timing'
-#root.trace.flags="Bus Cache"
-#root.trace.flags = "BusAddrRanges"
+root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_x64,
+                    cpu_class=DerivO3CPU, num_cpus=nb_cores).create_root()
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 2be0556a6..2f9ea52c2 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,31 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
+from base_config import *
 
-cpu = DerivO3CPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
-                              L1Cache(size = '256kB'),
-                              L2Cache(size = '2MB'))
-# @todo Note that the L2 latency here is unmodified and 2 cycles,
-# should set hit latency and response latency to 20 cycles as for
-# other scripts
-cpu.clock = '2GHz'
-
-system = System(cpu = cpu,
-                physmem = DDR3_1600_x64(),
-                membus = CoherentBus(),
-                mem_mode = "timing")
-system.clock = '1GHz'
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-# create the interrupt controller
-cpu.createInterruptController()
-cpu.connectAllPorts(system.membus)
-
-root = Root(full_system = False, system = system)
+root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+                                cpu_class=DerivO3CPU).create_root()
diff --git a/tests/configs/simple-atomic-dummychecker.py b/tests/configs/simple-atomic-dummychecker.py
index d28501403..f3b322f60 100644
--- a/tests/configs/simple-atomic-dummychecker.py
+++ b/tests/configs/simple-atomic-dummychecker.py
@@ -1,5 +1,5 @@
-# Copyright (c) 2011 ARM Limited
-# All rights reserved
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
 # not be construed as granting a license to any other intellectual
@@ -33,20 +33,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Geoffrey Blake
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
+from base_config import *
 
-system = System(cpu = AtomicSimpleCPU(cpu_id=0),
-                physmem = SimpleMemory(),
-                membus = CoherentBus())
-system.clock = '1GHz'
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-system.cpu.addCheckerCpu()
-system.cpu.createInterruptController()
-system.cpu.connectAllPorts(system.membus)
-system.cpu.clock = '2GHz'
-
-root = Root(full_system = False, system = system)
+root = BaseSESystemUniprocessor(mem_mode='atomic',
+                                cpu_class=AtomicSimpleCPU,
+                                checker=True).create_root()
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index d43371eb5..308caade0 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,48 +36,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Ron Dreslinski
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
+from base_config import *
 
 nb_cores = 4
-cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
-
-# system simulated
-system = System(cpu = cpus,
-                physmem = SimpleMemory(range = AddrRange('1024MB')),
-                membus = CoherentBus())
-system.clock = '1GHz'
-# l2cache & bus
-system.toL2Bus = CoherentBus(clock = '2GHz')
-system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-
-# connect l2c to membus
-system.l2c.mem_side = system.membus.slave
-
-# add L1 caches
-for cpu in cpus:
-    cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
-                                L1Cache(size = '32kB', assoc = 4))
-    # create the interrupt controller
-    cpu.createInterruptController()
-    # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectAllPorts(system.toL2Bus, system.membus)
-    cpu.clock = '2GHz'
-
-# connect memory to membus
-system.physmem.port = system.membus.master
-
-# connect system port to membus
-system.system_port = system.membus.slave
-
-# -----------------------
-# run simulation
-# -----------------------
-
-root = Root( full_system = False, system = system )
-root.system.mem_mode = 'atomic'
+root = BaseSESystem(mem_mode='atomic', cpu_class=AtomicSimpleCPU,
+                    num_cpus=nb_cores).create_root()
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index b9baba164..59eb60899 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,20 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
+from base_config import *
 
-system = System(cpu = AtomicSimpleCPU(cpu_id=0),
-                physmem = SimpleMemory(),
-                membus = CoherentBus())
-system.clock = '1GHz'
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-# create the interrupt controller
-system.cpu.createInterruptController()
-system.cpu.connectAllPorts(system.membus)
-system.cpu.clock = '2GHz'
-
-root = Root(full_system = False, system = system)
+root = BaseSESystemUniprocessor(mem_mode='atomic',
+                                cpu_class=AtomicSimpleCPU).create_root()
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 1acfacbdf..d8a904b53 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,47 +36,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Ron Dreslinski
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
+from base_config import *
 
 nb_cores = 4
-cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
-
-# system simulated
-system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
-system.clock = '1GHz'
-
-# l2cache & bus
-system.toL2Bus = CoherentBus(clock = '2GHz')
-system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-
-# connect l2c to membus
-system.l2c.mem_side = system.membus.slave
-
-# add L1 caches
-for cpu in cpus:
-    cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
-                                L1Cache(size = '32kB', assoc = 4))
-    # create the interrupt controller
-    cpu.createInterruptController()
-    # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectAllPorts(system.toL2Bus, system.membus)
-    cpu.clock = '2GHz'
-
-system.system_port = system.membus.slave
-
-# connect memory to membus
-system.physmem.port = system.membus.master
-
-
-# -----------------------
-# run simulation
-# -----------------------
-
-root = Root( full_system = False, system = system )
-root.system.mem_mode = 'timing'
+root = BaseSESystem(mem_mode='timing', cpu_class=TimingSimpleCPU,
+                    num_cpus=nb_cores).create_root()
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 046ee96dd..4b11a5d3c 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,27 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
+from base_config import *
 
-cpu = TimingSimpleCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
-                              L1Cache(size = '256kB'),
-                              L2Cache(size = '2MB'))
-system = System(cpu = cpu,
-                physmem = SimpleMemory(),
-                membus = CoherentBus(),
-                mem_mode = "timing")
-system.clock = '1GHz'
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-# create the interrupt controller
-cpu.createInterruptController()
-cpu.connectAllPorts(system.membus)
-cpu.clock = '2GHz'
-
-root = Root(full_system=False, system = system)
+root = BaseSESystemUniprocessor(mem_mode='timing',
+                                cpu_class=TimingSimpleCPU).create_root()
diff --git a/tests/long/se/10.mcf/test.py b/tests/long/se/10.mcf/test.py
index 9bd18a83f..0ea3f370d 100644
--- a/tests/long/se/10.mcf/test.py
+++ b/tests/long/se/10.mcf/test.py
@@ -30,5 +30,5 @@ m5.util.addToPath('../configs/common')
 from cpu2000 import mcf
 
 workload = mcf(isa, opsys, 'smred')
-root.system.cpu.workload = workload.makeLiveProcess()
+root.system.cpu[0].workload = workload.makeLiveProcess()
 root.system.physmem.range=AddrRange('256MB')
diff --git a/tests/long/se/20.parser/test.py b/tests/long/se/20.parser/test.py
index c96a46e60..fa72847c7 100644
--- a/tests/long/se/20.parser/test.py
+++ b/tests/long/se/20.parser/test.py
@@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
 from cpu2000 import parser
 
 workload = parser(isa, opsys, 'mdred')
-root.system.cpu.workload = workload.makeLiveProcess()
+root.system.cpu[0].workload = workload.makeLiveProcess()
diff --git a/tests/long/se/30.eon/test.py b/tests/long/se/30.eon/test.py
index de4d12dd8..2ad1ef429 100644
--- a/tests/long/se/30.eon/test.py
+++ b/tests/long/se/30.eon/test.py
@@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
 from cpu2000 import eon_cook
 
 workload = eon_cook(isa, opsys, 'mdred')
-root.system.cpu.workload = workload.makeLiveProcess()
+root.system.cpu[0].workload = workload.makeLiveProcess()
diff --git a/tests/long/se/40.perlbmk/test.py b/tests/long/se/40.perlbmk/test.py
index 8fe5d6047..74c876978 100644
--- a/tests/long/se/40.perlbmk/test.py
+++ b/tests/long/se/40.perlbmk/test.py
@@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
 from cpu2000 import perlbmk_makerand
 
 workload = perlbmk_makerand(isa, opsys, 'lgred')
-root.system.cpu.workload = workload.makeLiveProcess()
+root.system.cpu[0].workload = workload.makeLiveProcess()
diff --git a/tests/long/se/50.vortex/test.py b/tests/long/se/50.vortex/test.py
index 92422c234..794a11aa1 100644
--- a/tests/long/se/50.vortex/test.py
+++ b/tests/long/se/50.vortex/test.py
@@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
 from cpu2000 import vortex
 
 workload = vortex(isa, opsys, 'smred')
-root.system.cpu.workload = workload.makeLiveProcess()
+root.system.cpu[0].workload = workload.makeLiveProcess()
diff --git a/tests/long/se/60.bzip2/test.py b/tests/long/se/60.bzip2/test.py
index fa74d0860..c217f159c 100644
--- a/tests/long/se/60.bzip2/test.py
+++ b/tests/long/se/60.bzip2/test.py
@@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
 from cpu2000 import bzip2_source
 
 workload = bzip2_source(isa, opsys, 'lgred')
-root.system.cpu.workload = workload.makeLiveProcess()
+root.system.cpu[0].workload = workload.makeLiveProcess()
diff --git a/tests/long/se/70.twolf/test.py b/tests/long/se/70.twolf/test.py
index 761ec8b2e..5b99b86fa 100644
--- a/tests/long/se/70.twolf/test.py
+++ b/tests/long/se/70.twolf/test.py
@@ -31,8 +31,8 @@ from cpu2000 import twolf
 import os
 
 workload = twolf(isa, opsys, 'smred')
-root.system.cpu.workload = workload.makeLiveProcess()
-cwd = root.system.cpu.workload[0].cwd
+root.system.cpu[0].workload = workload.makeLiveProcess()
+cwd = root.system.cpu[0].workload[0].cwd
 
 #Remove two files who's presence or absence affects execution
 sav_file = os.path.join(cwd, workload.input_set + '.sav')
diff --git a/tests/quick/se/00.hello/test.py b/tests/quick/se/00.hello/test.py
index 000181850..c37f8415c 100644
--- a/tests/quick/se/00.hello/test.py
+++ b/tests/quick/se/00.hello/test.py
@@ -26,7 +26,7 @@
 #
 # Authors: Steve Reinhardt
 
-root.system.cpu.workload = LiveProcess(cmd = 'hello',
-                                       executable = binpath('hello'))
-if root.system.cpu.checker != NULL:
-    root.system.cpu.checker.workload = root.system.cpu.workload
+root.system.cpu[0].workload = LiveProcess(cmd = 'hello',
+                                          executable = binpath('hello'))
+if root.system.cpu[0].checker != NULL:
+    root.system.cpu[0].checker.workload = root.system.cpu[0].workload
diff --git a/tests/quick/se/01.hello-2T-smt/test.py b/tests/quick/se/01.hello-2T-smt/test.py
index 2db81da93..885de10f3 100644
--- a/tests/quick/se/01.hello-2T-smt/test.py
+++ b/tests/quick/se/01.hello-2T-smt/test.py
@@ -29,5 +29,5 @@
 process1 = LiveProcess(cmd = 'hello', executable = binpath('hello'))
 process2 = LiveProcess(cmd = 'hello', executable = binpath('hello'))
 
-root.system.cpu.workload = [process1, process2]
-root.system.cpu.numThreads = 2
+root.system.cpu[0].workload = [process1, process2]
+root.system.cpu[0].numThreads = 2
diff --git a/tests/quick/se/02.insttest/test.py b/tests/quick/se/02.insttest/test.py
index 93664fbef..23e028d25 100644
--- a/tests/quick/se/02.insttest/test.py
+++ b/tests/quick/se/02.insttest/test.py
@@ -26,5 +26,5 @@
 #
 # Authors: Ali Saidi
 
-root.system.cpu.workload = LiveProcess(cmd = 'insttest',
-                                       executable = binpath('insttest'))
+root.system.cpu[0].workload = LiveProcess(cmd = 'insttest',
+                                          executable = binpath('insttest'))
diff --git a/tests/quick/se/20.eio-short/test.py b/tests/quick/se/20.eio-short/test.py
index 67d8a582c..36a86889d 100644
--- a/tests/quick/se/20.eio-short/test.py
+++ b/tests/quick/se/20.eio-short/test.py
@@ -28,6 +28,6 @@
 
 require_sim_object("EioProcess")
 
-root.system.cpu.workload = EioProcess(file = binpath('anagram',
+root.system.cpu[0].workload = EioProcess(file = binpath('anagram',
                                                      'anagram-vshort.eio.gz'))
-root.system.cpu.max_insts_any_thread = 500000
+root.system.cpu[0].max_insts_any_thread = 500000