tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)
This patch avoids compiling ALPHA six times as part of running 'util/regress', and instead relis on NULL with different protocols to run the rubytest. All we need is the memory system, so there is really no need to compile the ISA over and over again. The one downside is the removal of running 'hello' for the variuos ALPHA and protocol combinations, but if this is a concern we should rather beef up the synthetic tests for the variuos protocols. --HG-- rename : build_opts/NULL => build_opts/NULL_MESI_Two_Level rename : build_opts/NULL => build_opts/NULL_MOESI_CMP_directory rename : build_opts/NULL => build_opts/NULL_MOESI_CMP_token rename : build_opts/NULL => build_opts/NULL_MOESI_hammer rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/simerr rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/simout rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/simout rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_token/simerr rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_token/simout rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_hammer/config.ini rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_hammer/simerr rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_hammer/simout rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_hammer/stats.txt rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/config.ini rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/simerr rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/simout rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/stats.txt
This commit is contained in:
Andreas Hansson
parent
6ed567d600
commit
4cf7f6c4ca
42 changed files with 18 additions and 9816 deletions
3
build_opts/NULL_MESI_Two_Level
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3
build_opts/NULL_MESI_Two_Level
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TARGET_ISA = 'null'
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CPU_MODELS = ''
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PROTOCOL = 'MESI_Two_Level'
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3
build_opts/NULL_MOESI_CMP_directory
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3
build_opts/NULL_MOESI_CMP_directory
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@ -0,0 +1,3 @@
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TARGET_ISA = 'null'
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CPU_MODELS = ''
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PROTOCOL='MOESI_CMP_directory'
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3
build_opts/NULL_MOESI_CMP_token
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3
build_opts/NULL_MOESI_CMP_token
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@ -0,0 +1,3 @@
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TARGET_ISA = 'null'
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CPU_MODELS = ''
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PROTOCOL='MOESI_CMP_token'
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3
build_opts/NULL_MOESI_hammer
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3
build_opts/NULL_MOESI_hammer
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@ -0,0 +1,3 @@
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TARGET_ISA = 'null'
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CPU_MODELS = ''
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PROTOCOL='MOESI_hammer'
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@ -40,7 +40,7 @@ from ruby import Ruby
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from common import Options
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from common import Options
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parser = optparse.OptionParser()
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Options.addNoISAOptions(parser)
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# Add the ruby specific and protocol specific options
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# Add the ruby specific and protocol specific options
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Ruby.define_options(parser)
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Ruby.define_options(parser)
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File diff suppressed because it is too large
Load diff
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@ -1,10 +0,0 @@
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
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warn: Sockets disabled, not accepting gdb connections
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warn: ClockedObject: More than one power state change request encountered within the same simulation tick
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warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
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@ -1,15 +0,0 @@
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Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
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Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Oct 13 2016 20:28:06
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gem5 started Oct 13 2016 20:28:31
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gem5 executing on e108600-lin, pid 8233
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command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
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Global frequency set at 1000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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Hello world!
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Exiting @ tick 129075 because target called exit()
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@ -1,764 +0,0 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000129 # Number of seconds simulated
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sim_ticks 129075 # Number of ticks simulated
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final_tick 129075 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000 # Frequency of simulated ticks
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host_inst_rate 77143 # Simulator instruction rate (inst/s)
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host_op_rate 77134 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1554751 # Simulator tick rate (ticks/s)
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host_mem_usage 412952 # Number of bytes of host memory used
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host_seconds 0.08 # Real time elapsed on the host
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sim_insts 6403 # Number of instructions simulated
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sim_ops 6403 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1 # Clock period in ticks
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system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
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system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93504 # Number of bytes read from this memory
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system.mem_ctrls.bytes_read::total 93504 # Number of bytes read from this memory
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system.mem_ctrls.bytes_written::ruby.dir_cntrl0 17728 # Number of bytes written to this memory
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system.mem_ctrls.bytes_written::total 17728 # Number of bytes written to this memory
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system.mem_ctrls.num_reads::ruby.dir_cntrl0 1461 # Number of read requests responded to by this memory
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system.mem_ctrls.num_reads::total 1461 # Number of read requests responded to by this memory
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system.mem_ctrls.num_writes::ruby.dir_cntrl0 277 # Number of write requests responded to by this memory
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system.mem_ctrls.num_writes::total 277 # Number of write requests responded to by this memory
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system.mem_ctrls.bw_read::ruby.dir_cntrl0 724416037 # Total read bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_read::total 724416037 # Total read bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_write::ruby.dir_cntrl0 137346504 # Write bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_write::total 137346504 # Write bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_total::ruby.dir_cntrl0 861762541 # Total bandwidth to/from this memory (bytes/s)
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system.mem_ctrls.bw_total::total 861762541 # Total bandwidth to/from this memory (bytes/s)
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system.mem_ctrls.readReqs 1461 # Number of read requests accepted
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system.mem_ctrls.writeReqs 277 # Number of write requests accepted
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system.mem_ctrls.readBursts 1461 # Number of DRAM read bursts, including those serviced by the write queue
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system.mem_ctrls.writeBursts 277 # Number of DRAM write bursts, including those merged in the write queue
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system.mem_ctrls.bytesReadDRAM 74368 # Total number of bytes read from DRAM
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system.mem_ctrls.bytesReadWrQ 19136 # Total number of bytes read from write queue
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system.mem_ctrls.bytesWritten 6400 # Total number of bytes written to DRAM
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system.mem_ctrls.bytesReadSys 93504 # Total read bytes from the system interface side
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system.mem_ctrls.bytesWrittenSys 17728 # Total written bytes from the system interface side
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system.mem_ctrls.servicedByWrQ 299 # Number of DRAM read bursts serviced by the write queue
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system.mem_ctrls.mergedWrBursts 160 # Number of DRAM write bursts merged with an existing one
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system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::1 61 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::2 90 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::3 90 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::4 101 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::5 22 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::7 4 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::10 78 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::11 75 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::13 395 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::15 49 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::4 24 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::5 7 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::10 7 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::13 21 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::14 41 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
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system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
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system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
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system.mem_ctrls.totGap 128982 # Total gap between requests
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system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::6 1461 # Read request sizes (log2)
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system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::6 277 # Write request sizes (log2)
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system.mem_ctrls.rdQLenPdf::0 1162 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
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|
||||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::32 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.bytesPerActivate::samples 215 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::mean 364.055814 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::gmean 222.075931 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::stdev 347.859995 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::0-127 60 27.91% 27.91% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::128-255 55 25.58% 53.49% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::256-383 24 11.16% 64.65% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::384-511 15 6.98% 71.63% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::512-639 8 3.72% 75.35% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::640-767 9 4.19% 79.53% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::768-895 8 3.72% 83.26% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::896-1023 5 2.33% 85.58% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::1024-1151 31 14.42% 100.00% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::total 215 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::mean 193.166667 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::gmean 134.817545 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::stdev 132.906609 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::64-79 1 16.67% 33.33% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::192-207 1 16.67% 50.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::224-239 1 16.67% 66.67% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::240-255 1 16.67% 83.33% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::384-399 1 16.67% 100.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::total 6 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::gmean 16.640671 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::stdev 1.032796 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::16 4 66.67% 66.67% # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::18 2 33.33% 100.00% # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.totQLat 15493 # Total ticks spent queuing
|
|
||||||
system.mem_ctrls.totMemAccLat 37571 # Total ticks spent from burst creation until serviced by the DRAM
|
|
||||||
system.mem_ctrls.totBusLat 5810 # Total ticks spent in databus transfers
|
|
||||||
system.mem_ctrls.avgQLat 13.33 # Average queueing delay per DRAM burst
|
|
||||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
|
||||||
system.mem_ctrls.avgMemAccLat 32.33 # Average memory access latency per DRAM burst
|
|
||||||
system.mem_ctrls.avgRdBW 576.16 # Average DRAM read bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.avgWrBW 49.58 # Average achieved write bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.avgRdBWSys 724.42 # Average system read bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.avgWrBWSys 137.35 # Average system write bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.busUtil 4.89 # Data bus utilization in percentage
|
|
||||||
system.mem_ctrls.busUtilRead 4.50 # Data bus utilization in percentage for reads
|
|
||||||
system.mem_ctrls.busUtilWrite 0.39 # Data bus utilization in percentage for writes
|
|
||||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
||||||
system.mem_ctrls.avgWrQLen 22.78 # Average write queue length when enqueuing
|
|
||||||
system.mem_ctrls.readRowHits 949 # Number of row buffer hits during reads
|
|
||||||
system.mem_ctrls.writeRowHits 91 # Number of row buffer hits during writes
|
|
||||||
system.mem_ctrls.readRowHitRate 81.67 # Row buffer hit rate for reads
|
|
||||||
system.mem_ctrls.writeRowHitRate 77.78 # Row buffer hit rate for writes
|
|
||||||
system.mem_ctrls.avgGap 74.21 # Average gap between requests
|
|
||||||
system.mem_ctrls.pageHitRate 81.31 # Row buffer hit rate, read and write combined
|
|
||||||
system.mem_ctrls_0.actEnergy 514080 # Energy for activate commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.preEnergy 270480 # Energy for precharge commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.readEnergy 5380704 # Energy for read commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.writeEnergy 258912 # Energy for write commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.actBackEnergy 8608824 # Energy for active background per rank (pJ)
|
|
||||||
system.mem_ctrls_0.preBackEnergy 320256 # Energy for precharge background per rank (pJ)
|
|
||||||
system.mem_ctrls_0.actPowerDownEnergy 37409784 # Energy for active power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_0.prePowerDownEnergy 6725376 # Energy for precharge power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_0.selfRefreshEnergy 2906400 # Energy for self refresh per rank (pJ)
|
|
||||||
system.mem_ctrls_0.totalEnergy 72229056 # Total energy per rank (pJ)
|
|
||||||
system.mem_ctrls_0.averagePower 559.589820 # Core power per rank (mW)
|
|
||||||
system.mem_ctrls_0.totalIdleTime 109312 # Total Idle time Per DRAM Rank
|
|
||||||
system.mem_ctrls_0.memoryStateTime::IDLE 366 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::REF 4166 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::SREF 9809 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 17514 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::ACT 15181 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 82039 # Time in different power states
|
|
||||||
system.mem_ctrls_1.actEnergy 1071000 # Energy for activate commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.preEnergy 560280 # Energy for precharge commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.readEnergy 7893984 # Energy for read commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.writeEnergy 576288 # Energy for write commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.actBackEnergy 12597000 # Energy for active background per rank (pJ)
|
|
||||||
system.mem_ctrls_1.preBackEnergy 372480 # Energy for precharge background per rank (pJ)
|
|
||||||
system.mem_ctrls_1.actPowerDownEnergy 45058272 # Energy for active power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_1.prePowerDownEnergy 640512 # Energy for precharge power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
|
||||||
system.mem_ctrls_1.totalEnergy 78604056 # Total energy per rank (pJ)
|
|
||||||
system.mem_ctrls_1.averagePower 608.979709 # Core power per rank (mW)
|
|
||||||
system.mem_ctrls_1.totalIdleTime 100248 # Total Idle time Per DRAM Rank
|
|
||||||
system.mem_ctrls_1.memoryStateTime::IDLE 270 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::REF 4160 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 1668 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::ACT 24165 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 98812 # Time in different power states
|
|
||||||
system.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
|
|
||||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
|
||||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
||||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
|
||||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
|
||||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
||||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
|
||||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 10 # DTB misses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
|
||||||
system.cpu.itb.fetch_hits 6414 # ITB hits
|
|
||||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_accesses 6431 # ITB accesses
|
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
||||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
|
||||||
system.cpu.pwrStateResidencyTicks::ON 129075 # Cumulative time (in ticks) in various power states
|
|
||||||
system.cpu.numCycles 129075 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.committedInsts 6403 # Number of instructions committed
|
|
||||||
system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
|
|
||||||
system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
|
|
||||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
|
||||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
|
||||||
system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_int_insts 6329 # number of integer instructions
|
|
||||||
system.cpu.num_fp_insts 10 # number of float instructions
|
|
||||||
system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
|
|
||||||
system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
|
|
||||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
|
||||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
|
||||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
|
||||||
system.cpu.num_store_insts 868 # Number of store instructions
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_busy_cycles 129075 # Number of busy cycles
|
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
||||||
system.cpu.Branches 1056 # Number of branches fetched
|
|
||||||
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction
|
|
||||||
system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
||||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
||||||
system.cpu.op_class::total 6413 # Class of executed instruction
|
|
||||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
|
||||||
system.ruby.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
|
|
||||||
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
|
|
||||||
system.ruby.delayHist::samples 9652 # delay histogram for all message
|
|
||||||
system.ruby.delayHist::mean 0.163697 # delay histogram for all message
|
|
||||||
system.ruby.delayHist::stdev 1.010840 # delay histogram for all message
|
|
||||||
system.ruby.delayHist | 9297 96.32% 96.32% | 0 0.00% 96.32% | 210 2.18% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
|
||||||
system.ruby.delayHist::total 9652 # delay histogram for all message
|
|
||||||
system.ruby.outstanding_req_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.outstanding_req_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.outstanding_req_hist_seqr::samples 8464
|
|
||||||
system.ruby.outstanding_req_hist_seqr::mean 1
|
|
||||||
system.ruby.outstanding_req_hist_seqr::gmean 1
|
|
||||||
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.outstanding_req_hist_seqr::total 8464
|
|
||||||
system.ruby.latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.latency_hist_seqr::samples 8463
|
|
||||||
system.ruby.latency_hist_seqr::mean 14.251684
|
|
||||||
system.ruby.latency_hist_seqr::gmean 2.119385
|
|
||||||
system.ruby.latency_hist_seqr::stdev 32.289040
|
|
||||||
system.ruby.latency_hist_seqr | 7301 86.27% 86.27% | 1142 13.49% 99.76% | 3 0.04% 99.80% | 1 0.01% 99.81% | 6 0.07% 99.88% | 9 0.11% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00%
|
|
||||||
system.ruby.latency_hist_seqr::total 8463
|
|
||||||
system.ruby.hit_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.hit_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.hit_latency_hist_seqr::samples 6972
|
|
||||||
system.ruby.hit_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.hit_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6972 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.hit_latency_hist_seqr::total 6972
|
|
||||||
system.ruby.miss_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.miss_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.miss_latency_hist_seqr::samples 1491
|
|
||||||
system.ruby.miss_latency_hist_seqr::mean 76.217304
|
|
||||||
system.ruby.miss_latency_hist_seqr::gmean 71.053455
|
|
||||||
system.ruby.miss_latency_hist_seqr::stdev 35.454362
|
|
||||||
system.ruby.miss_latency_hist_seqr | 329 22.07% 22.07% | 1142 76.59% 98.66% | 3 0.20% 98.86% | 1 0.07% 98.93% | 6 0.40% 99.33% | 9 0.60% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00%
|
|
||||||
system.ruby.miss_latency_hist_seqr::total 1491
|
|
||||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1250 # Number of cache demand hits
|
|
||||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 800 # Number of cache demand misses
|
|
||||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
|
|
||||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 5722 # Number of cache demand hits
|
|
||||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 691 # Number of cache demand misses
|
|
||||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
|
|
||||||
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
|
|
||||||
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
|
|
||||||
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
|
|
||||||
system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
|
|
||||||
system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
|
|
||||||
system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
|
|
||||||
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
|
|
||||||
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
|
|
||||||
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
|
|
||||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
|
|
||||||
system.ruby.l2_cntrl0.L2cache.demand_misses 1461 # Number of cache demand misses
|
|
||||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 1491 # Number of cache demand accesses
|
|
||||||
system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
|
||||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers0.percent_links_utilized 4.058493
|
|
||||||
system.ruby.network.routers0.msg_count.Control::0 1491
|
|
||||||
system.ruby.network.routers0.msg_count.Request_Control::2 1041
|
|
||||||
system.ruby.network.routers0.msg_count.Response_Data::1 1491
|
|
||||||
system.ruby.network.routers0.msg_count.Response_Control::1 1337
|
|
||||||
system.ruby.network.routers0.msg_count.Response_Control::2 800
|
|
||||||
system.ruby.network.routers0.msg_count.Writeback_Data::0 145
|
|
||||||
system.ruby.network.routers0.msg_count.Writeback_Data::1 141
|
|
||||||
system.ruby.network.routers0.msg_count.Writeback_Control::0 292
|
|
||||||
system.ruby.network.routers0.msg_bytes.Control::0 11928
|
|
||||||
system.ruby.network.routers0.msg_bytes.Request_Control::2 8328
|
|
||||||
system.ruby.network.routers0.msg_bytes.Response_Data::1 107352
|
|
||||||
system.ruby.network.routers0.msg_bytes.Response_Control::1 10696
|
|
||||||
system.ruby.network.routers0.msg_bytes.Response_Control::2 6400
|
|
||||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440
|
|
||||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152
|
|
||||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2336
|
|
||||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers1.percent_links_utilized 7.880302
|
|
||||||
system.ruby.network.routers1.msg_count.Control::0 2952
|
|
||||||
system.ruby.network.routers1.msg_count.Request_Control::2 1041
|
|
||||||
system.ruby.network.routers1.msg_count.Response_Data::1 3229
|
|
||||||
system.ruby.network.routers1.msg_count.Response_Control::1 3966
|
|
||||||
system.ruby.network.routers1.msg_count.Response_Control::2 800
|
|
||||||
system.ruby.network.routers1.msg_count.Writeback_Data::0 145
|
|
||||||
system.ruby.network.routers1.msg_count.Writeback_Data::1 141
|
|
||||||
system.ruby.network.routers1.msg_count.Writeback_Control::0 292
|
|
||||||
system.ruby.network.routers1.msg_bytes.Control::0 23616
|
|
||||||
system.ruby.network.routers1.msg_bytes.Request_Control::2 8328
|
|
||||||
system.ruby.network.routers1.msg_bytes.Response_Data::1 232488
|
|
||||||
system.ruby.network.routers1.msg_bytes.Response_Control::1 31728
|
|
||||||
system.ruby.network.routers1.msg_bytes.Response_Control::2 6400
|
|
||||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440
|
|
||||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152
|
|
||||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2336
|
|
||||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers2.percent_links_utilized 3.821809
|
|
||||||
system.ruby.network.routers2.msg_count.Control::0 1461
|
|
||||||
system.ruby.network.routers2.msg_count.Response_Data::1 1738
|
|
||||||
system.ruby.network.routers2.msg_count.Response_Control::1 2629
|
|
||||||
system.ruby.network.routers2.msg_bytes.Control::0 11688
|
|
||||||
system.ruby.network.routers2.msg_bytes.Response_Data::1 125136
|
|
||||||
system.ruby.network.routers2.msg_bytes.Response_Control::1 21032
|
|
||||||
system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers3.percent_links_utilized 5.253535
|
|
||||||
system.ruby.network.routers3.msg_count.Control::0 2952
|
|
||||||
system.ruby.network.routers3.msg_count.Request_Control::2 1041
|
|
||||||
system.ruby.network.routers3.msg_count.Response_Data::1 3229
|
|
||||||
system.ruby.network.routers3.msg_count.Response_Control::1 3966
|
|
||||||
system.ruby.network.routers3.msg_count.Response_Control::2 800
|
|
||||||
system.ruby.network.routers3.msg_count.Writeback_Data::0 145
|
|
||||||
system.ruby.network.routers3.msg_count.Writeback_Data::1 141
|
|
||||||
system.ruby.network.routers3.msg_count.Writeback_Control::0 292
|
|
||||||
system.ruby.network.routers3.msg_bytes.Control::0 23616
|
|
||||||
system.ruby.network.routers3.msg_bytes.Request_Control::2 8328
|
|
||||||
system.ruby.network.routers3.msg_bytes.Response_Data::1 232488
|
|
||||||
system.ruby.network.routers3.msg_bytes.Response_Control::1 31728
|
|
||||||
system.ruby.network.routers3.msg_bytes.Response_Control::2 6400
|
|
||||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::0 10440
|
|
||||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::1 10152
|
|
||||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2336
|
|
||||||
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.msg_count.Control 8856
|
|
||||||
system.ruby.network.msg_count.Request_Control 3123
|
|
||||||
system.ruby.network.msg_count.Response_Data 9687
|
|
||||||
system.ruby.network.msg_count.Response_Control 14298
|
|
||||||
system.ruby.network.msg_count.Writeback_Data 858
|
|
||||||
system.ruby.network.msg_count.Writeback_Control 876
|
|
||||||
system.ruby.network.msg_byte.Control 70848
|
|
||||||
system.ruby.network.msg_byte.Request_Control 24984
|
|
||||||
system.ruby.network.msg_byte.Response_Data 697464
|
|
||||||
system.ruby.network.msg_byte.Response_Control 114384
|
|
||||||
system.ruby.network.msg_byte.Writeback_Data 61776
|
|
||||||
system.ruby.network.msg_byte.Writeback_Control 7008
|
|
||||||
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers0.throttle0.link_utilization 5.770676
|
|
||||||
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041
|
|
||||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1491
|
|
||||||
system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 437
|
|
||||||
system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 8328
|
|
||||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107352
|
|
||||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3496
|
|
||||||
system.ruby.network.routers0.throttle1.link_utilization 2.346310
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Control::0 1491
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 900
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 800
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 145
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 141
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 292
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::0 11928
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 7200
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6400
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 10440
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 10152
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2336
|
|
||||||
system.ruby.network.routers1.throttle0.link_utilization 8.002712
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Control::0 1491
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1461
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2353
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 800
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 145
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 141
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 292
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::0 11928
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 105192
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 18824
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6400
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 10440
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 10152
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2336
|
|
||||||
system.ruby.network.routers1.throttle1.link_utilization 7.757893
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Control::0 1461
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1041
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1768
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 1613
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11688
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 8328
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127296
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12904
|
|
||||||
system.ruby.network.routers2.throttle0.link_utilization 1.987217
|
|
||||||
system.ruby.network.routers2.throttle0.msg_count.Control::0 1461
|
|
||||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 277
|
|
||||||
system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1176
|
|
||||||
system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11688
|
|
||||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 19944
|
|
||||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9408
|
|
||||||
system.ruby.network.routers2.throttle1.link_utilization 5.656401
|
|
||||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1461
|
|
||||||
system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1453
|
|
||||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105192
|
|
||||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11624
|
|
||||||
system.ruby.network.routers3.throttle0.link_utilization 5.770676
|
|
||||||
system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 1041
|
|
||||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1491
|
|
||||||
system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 437
|
|
||||||
system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 8328
|
|
||||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107352
|
|
||||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3496
|
|
||||||
system.ruby.network.routers3.throttle1.link_utilization 8.002712
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Control::0 1491
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1461
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2353
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 800
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 145
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 141
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 292
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Control::0 11928
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 105192
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 18824
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6400
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 10440
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 10152
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2336
|
|
||||||
system.ruby.network.routers3.throttle2.link_utilization 1.987217
|
|
||||||
system.ruby.network.routers3.throttle2.msg_count.Control::0 1461
|
|
||||||
system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 277
|
|
||||||
system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1176
|
|
||||||
system.ruby.network.routers3.throttle2.msg_bytes.Control::0 11688
|
|
||||||
system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 19944
|
|
||||||
system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 9408
|
|
||||||
system.ruby.delayVCHist.vnet_0::bucket_size 1 # delay histogram for vnet_0
|
|
||||||
system.ruby.delayVCHist.vnet_0::max_bucket 9 # delay histogram for vnet_0
|
|
||||||
system.ruby.delayVCHist.vnet_0::samples 2728 # delay histogram for vnet_0
|
|
||||||
system.ruby.delayVCHist.vnet_0::mean 0.425220 # delay histogram for vnet_0
|
|
||||||
system.ruby.delayVCHist.vnet_0::stdev 1.795029 # delay histogram for vnet_0
|
|
||||||
system.ruby.delayVCHist.vnet_0 | 2583 94.68% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 145 5.32% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
|
|
||||||
system.ruby.delayVCHist.vnet_0::total 2728 # delay histogram for vnet_0
|
|
||||||
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
|
|
||||||
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
|
|
||||||
system.ruby.delayVCHist.vnet_1::samples 5883 # delay histogram for vnet_1
|
|
||||||
system.ruby.delayVCHist.vnet_1::mean 0.071392 # delay histogram for vnet_1
|
|
||||||
system.ruby.delayVCHist.vnet_1::stdev 0.371094 # delay histogram for vnet_1
|
|
||||||
system.ruby.delayVCHist.vnet_1 | 5673 96.43% 96.43% | 0 0.00% 96.43% | 210 3.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
|
||||||
system.ruby.delayVCHist.vnet_1::total 5883 # delay histogram for vnet_1
|
|
||||||
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
|
|
||||||
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
|
|
||||||
system.ruby.delayVCHist.vnet_2::samples 1041 # delay histogram for vnet_2
|
|
||||||
system.ruby.delayVCHist.vnet_2 | 1041 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
|
||||||
system.ruby.delayVCHist.vnet_2::total 1041 # delay histogram for vnet_2
|
|
||||||
system.ruby.LD.latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.LD.latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.LD.latency_hist_seqr::samples 1185
|
|
||||||
system.ruby.LD.latency_hist_seqr::mean 36.416034
|
|
||||||
system.ruby.LD.latency_hist_seqr::gmean 7.907367
|
|
||||||
system.ruby.LD.latency_hist_seqr::stdev 46.041898
|
|
||||||
system.ruby.LD.latency_hist_seqr | 802 67.68% 67.68% | 375 31.65% 99.32% | 1 0.08% 99.41% | 0 0.00% 99.41% | 3 0.25% 99.66% | 3 0.25% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00%
|
|
||||||
system.ruby.LD.latency_hist_seqr::total 1185
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::samples 601
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 601 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::total 601
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::samples 584
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::mean 72.863014
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::gmean 66.405671
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::stdev 41.005857
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr | 201 34.42% 34.42% | 375 64.21% 98.63% | 1 0.17% 98.80% | 0 0.00% 98.80% | 3 0.51% 99.32% | 3 0.51% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::total 584
|
|
||||||
system.ruby.ST.latency_hist_seqr::bucket_size 16
|
|
||||||
system.ruby.ST.latency_hist_seqr::max_bucket 159
|
|
||||||
system.ruby.ST.latency_hist_seqr::samples 865
|
|
||||||
system.ruby.ST.latency_hist_seqr::mean 15.646243
|
|
||||||
system.ruby.ST.latency_hist_seqr::gmean 2.719887
|
|
||||||
system.ruby.ST.latency_hist_seqr::stdev 27.764380
|
|
||||||
system.ruby.ST.latency_hist_seqr | 649 75.03% 75.03% | 12 1.39% 76.42% | 101 11.68% 88.09% | 10 1.16% 89.25% | 36 4.16% 93.41% | 52 6.01% 99.42% | 4 0.46% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.latency_hist_seqr::total 865
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::samples 649
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 649 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::total 649
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::bucket_size 16
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::max_bucket 159
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::samples 216
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::mean 59.652778
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::gmean 54.981344
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::stdev 22.464955
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 12 5.56% 5.56% | 101 46.76% 52.31% | 10 4.63% 56.94% | 36 16.67% 73.61% | 52 24.07% 97.69% | 4 1.85% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::total 216
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::samples 6413
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::mean 9.968034
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::gmean 1.606700
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::stdev 27.770381
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr | 5727 89.30% 89.30% | 674 10.51% 99.81% | 2 0.03% 99.84% | 1 0.02% 99.86% | 3 0.05% 99.91% | 6 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::total 6413
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5722
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5722 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::total 5722
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::samples 691
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::mean 84.230101
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 81.513388
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.252511
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr | 5 0.72% 0.72% | 674 97.54% 98.26% | 2 0.29% 98.55% | 1 0.14% 98.70% | 3 0.43% 99.13% | 6 0.87% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::total 691
|
|
||||||
system.ruby.Directory_Controller.Fetch 1461 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Data 277 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Memory_Data 1461 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Memory_Ack 277 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.CleanReplacement 1176 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.I.Fetch 1461 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.M.Data 277 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.M.CleanReplacement 1176 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.IM.Memory_Data 1461 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.MI.Memory_Ack 277 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Inv 1041 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.L1_Replacement 1355 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Data_Exclusive 584 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Data_all_Acks 907 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.WB_Ack 437 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.NP.Load 526 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.NP.Ifetch 646 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.NP.Store 191 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.NP.Inv 356 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.I.Load 58 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.I.Ifetch 45 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.I.Store 25 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.I.L1_Replacement 556 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.S.Ifetch 5722 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.S.Inv 325 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.S.L1_Replacement 362 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.E.Load 453 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.E.Store 71 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.E.Inv 219 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.E.L1_Replacement 292 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Load 148 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Store 578 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Inv 141 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.L1_Replacement 145 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IS.Data_Exclusive 584 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IS.Data_all_Acks 691 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IM.Data_all_Acks 216 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M_I.WB_Ack 437 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L1_GET_INSTR 691 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L1_GETS 584 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L1_GETX 216 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L1_PUTX 437 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L2_Replacement 142 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L2_Replacement_clean 1311 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.Mem_Data 1461 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.Mem_Ack 1453 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.WB_Data 141 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.Ack_all 900 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.Exclusive_Unblock 800 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 686 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.NP.L1_GETS 571 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.NP.L1_GETX 204 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 5 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 681 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.M.L1_GETS 13 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.M.L1_GETX 12 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.M.L2_Replacement 134 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.M.L2_Replacement_clean 278 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.MT.L1_PUTX 437 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.MT.L2_Replacement 8 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 352 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.M_I.Mem_Ack 1453 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.MT_I.WB_Data 6 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.MT_I.Ack_all 2 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.MCT_I.WB_Data 135 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.MCT_I.Ack_all 217 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.I_I.Ack_all 681 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.ISS.Mem_Data 571 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.IS.Mem_Data 686 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.IM.Mem_Data 204 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 800 0.00% 0.00%
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,10 +0,0 @@
|
||||||
warn: rounding error > tolerance
|
|
||||||
1.250000 rounded to 1
|
|
||||||
warn: rounding error > tolerance
|
|
||||||
1.250000 rounded to 1
|
|
||||||
warn: rounding error > tolerance
|
|
||||||
1.250000 rounded to 1
|
|
||||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
|
||||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
|
||||||
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
|
|
||||||
|
|
@ -1,15 +0,0 @@
|
||||||
Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
|
|
||||||
Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
|
|
||||||
gem5 Simulator System. http://gem5.org
|
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
|
||||||
|
|
||||||
gem5 compiled Oct 13 2016 20:30:58
|
|
||||||
gem5 started Oct 13 2016 20:31:25
|
|
||||||
gem5 executing on e108600-lin, pid 17789
|
|
||||||
command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
|
|
||||||
|
|
||||||
Global frequency set at 1000000000 ticks per second
|
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
|
||||||
info: Increasing stack size by one page.
|
|
||||||
Hello world!
|
|
||||||
Exiting @ tick 115948 because target called exit()
|
|
||||||
|
|
@ -1,756 +0,0 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
|
||||||
sim_seconds 0.000116 # Number of seconds simulated
|
|
||||||
sim_ticks 115948 # Number of ticks simulated
|
|
||||||
final_tick 115948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
||||||
sim_freq 1000000000 # Frequency of simulated ticks
|
|
||||||
host_inst_rate 73551 # Simulator instruction rate (inst/s)
|
|
||||||
host_op_rate 73543 # Simulator op (including micro ops) rate (op/s)
|
|
||||||
host_tick_rate 1331606 # Simulator tick rate (ticks/s)
|
|
||||||
host_mem_usage 419184 # Number of bytes of host memory used
|
|
||||||
host_seconds 0.09 # Real time elapsed on the host
|
|
||||||
sim_insts 6403 # Number of instructions simulated
|
|
||||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
||||||
system.clk_domain.clock 1 # Clock period in ticks
|
|
||||||
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75712 # Number of bytes read from this memory
|
|
||||||
system.mem_ctrls.bytes_read::total 75712 # Number of bytes read from this memory
|
|
||||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 12416 # Number of bytes written to this memory
|
|
||||||
system.mem_ctrls.bytes_written::total 12416 # Number of bytes written to this memory
|
|
||||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1183 # Number of read requests responded to by this memory
|
|
||||||
system.mem_ctrls.num_reads::total 1183 # Number of read requests responded to by this memory
|
|
||||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 194 # Number of write requests responded to by this memory
|
|
||||||
system.mem_ctrls.num_writes::total 194 # Number of write requests responded to by this memory
|
|
||||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 652982371 # Total read bandwidth from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_read::total 652982371 # Total read bandwidth from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 107082485 # Write bandwidth from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_write::total 107082485 # Write bandwidth from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 760064857 # Total bandwidth to/from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_total::total 760064857 # Total bandwidth to/from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.readReqs 1183 # Number of read requests accepted
|
|
||||||
system.mem_ctrls.writeReqs 194 # Number of write requests accepted
|
|
||||||
system.mem_ctrls.readBursts 1183 # Number of DRAM read bursts, including those serviced by the write queue
|
|
||||||
system.mem_ctrls.writeBursts 194 # Number of DRAM write bursts, including those merged in the write queue
|
|
||||||
system.mem_ctrls.bytesReadDRAM 65152 # Total number of bytes read from DRAM
|
|
||||||
system.mem_ctrls.bytesReadWrQ 10560 # Total number of bytes read from write queue
|
|
||||||
system.mem_ctrls.bytesWritten 5440 # Total number of bytes written to DRAM
|
|
||||||
system.mem_ctrls.bytesReadSys 75712 # Total read bytes from the system interface side
|
|
||||||
system.mem_ctrls.bytesWrittenSys 12416 # Total written bytes from the system interface side
|
|
||||||
system.mem_ctrls.servicedByWrQ 165 # Number of DRAM read bursts serviced by the write queue
|
|
||||||
system.mem_ctrls.mergedWrBursts 79 # Number of DRAM write bursts merged with an existing one
|
|
||||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
|
||||||
system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::2 81 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::3 75 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::4 99 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::6 2 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::10 56 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::11 51 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::13 367 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::14 69 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::4 19 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::13 20 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
|
||||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
|
||||||
system.mem_ctrls.totGap 115890 # Total gap between requests
|
|
||||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::6 1183 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::6 194 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.rdQLenPdf::0 1018 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.bytesPerActivate::samples 208 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::mean 330.153846 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::gmean 204.681326 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::stdev 325.358480 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::0-127 61 29.33% 29.33% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::128-255 54 25.96% 55.29% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::256-383 30 14.42% 69.71% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::384-511 9 4.33% 74.04% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::512-639 16 7.69% 81.73% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::640-767 5 2.40% 84.13% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::768-895 5 2.40% 86.54% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::896-1023 4 1.92% 88.46% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::1024-1151 24 11.54% 100.00% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::total 208 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::mean 142.600000 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::gmean 108.227176 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::stdev 79.531755 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 40.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::136-143 1 20.00% 60.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 80.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::mean 17 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::gmean 16.976446 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::17 1 20.00% 60.00% # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.totQLat 13845 # Total ticks spent queuing
|
|
||||||
system.mem_ctrls.totMemAccLat 33187 # Total ticks spent from burst creation until serviced by the DRAM
|
|
||||||
system.mem_ctrls.totBusLat 5090 # Total ticks spent in databus transfers
|
|
||||||
system.mem_ctrls.avgQLat 13.60 # Average queueing delay per DRAM burst
|
|
||||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
|
||||||
system.mem_ctrls.avgMemAccLat 32.60 # Average memory access latency per DRAM burst
|
|
||||||
system.mem_ctrls.avgRdBW 561.91 # Average DRAM read bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.avgWrBW 46.92 # Average achieved write bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.avgRdBWSys 652.98 # Average system read bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.avgWrBWSys 107.08 # Average system write bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.busUtil 4.76 # Data bus utilization in percentage
|
|
||||||
system.mem_ctrls.busUtilRead 4.39 # Data bus utilization in percentage for reads
|
|
||||||
system.mem_ctrls.busUtilWrite 0.37 # Data bus utilization in percentage for writes
|
|
||||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
||||||
system.mem_ctrls.avgWrQLen 21.83 # Average write queue length when enqueuing
|
|
||||||
system.mem_ctrls.readRowHits 811 # Number of row buffer hits during reads
|
|
||||||
system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes
|
|
||||||
system.mem_ctrls.readRowHitRate 79.67 # Row buffer hit rate for reads
|
|
||||||
system.mem_ctrls.writeRowHitRate 67.83 # Row buffer hit rate for writes
|
|
||||||
system.mem_ctrls.avgGap 84.16 # Average gap between requests
|
|
||||||
system.mem_ctrls.pageHitRate 78.46 # Row buffer hit rate, read and write combined
|
|
||||||
system.mem_ctrls_0.actEnergy 528360 # Energy for activate commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.preEnergy 278208 # Energy for precharge commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.readEnergy 4706688 # Energy for read commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.writeEnergy 158688 # Energy for write commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.refreshEnergy 9219600.000000 # Energy for refresh commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.actBackEnergy 8177904 # Energy for active background per rank (pJ)
|
|
||||||
system.mem_ctrls_0.preBackEnergy 299520 # Energy for precharge background per rank (pJ)
|
|
||||||
system.mem_ctrls_0.actPowerDownEnergy 33992976 # Energy for active power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_0.prePowerDownEnergy 6547200 # Energy for precharge power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_0.selfRefreshEnergy 1905360 # Energy for self refresh per rank (pJ)
|
|
||||||
system.mem_ctrls_0.totalEnergy 65814504 # Total energy per rank (pJ)
|
|
||||||
system.mem_ctrls_0.averagePower 567.620865 # Core power per rank (mW)
|
|
||||||
system.mem_ctrls_0.totalIdleTime 97183 # Total Idle time Per DRAM Rank
|
|
||||||
system.mem_ctrls_0.memoryStateTime::IDLE 354 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::REF 3906 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::SREF 5638 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 17050 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::ACT 14454 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 74546 # Time in different power states
|
|
||||||
system.mem_ctrls_1.actEnergy 999600 # Energy for activate commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.preEnergy 525504 # Energy for precharge commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.readEnergy 6922944 # Energy for read commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.writeEnergy 551232 # Energy for write commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.actBackEnergy 10734696 # Energy for active background per rank (pJ)
|
|
||||||
system.mem_ctrls_1.preBackEnergy 319488 # Energy for precharge background per rank (pJ)
|
|
||||||
system.mem_ctrls_1.actPowerDownEnergy 40821120 # Energy for active power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_1.prePowerDownEnergy 789120 # Energy for precharge power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
|
||||||
system.mem_ctrls_1.totalEnergy 70268664 # Total energy per rank (pJ)
|
|
||||||
system.mem_ctrls_1.averagePower 606.036016 # Core power per rank (mW)
|
|
||||||
system.mem_ctrls_1.totalIdleTime 91295 # Total Idle time Per DRAM Rank
|
|
||||||
system.mem_ctrls_1.memoryStateTime::IDLE 272 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 2055 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::ACT 20461 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 89520 # Time in different power states
|
|
||||||
system.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
|
||||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
||||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
|
||||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
|
||||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
||||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
|
||||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 10 # DTB misses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
|
||||||
system.cpu.itb.fetch_hits 6414 # ITB hits
|
|
||||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_accesses 6431 # ITB accesses
|
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
||||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
|
||||||
system.cpu.pwrStateResidencyTicks::ON 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.cpu.numCycles 115948 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.committedInsts 6403 # Number of instructions committed
|
|
||||||
system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
|
|
||||||
system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
|
|
||||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
|
||||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
|
||||||
system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_int_insts 6329 # number of integer instructions
|
|
||||||
system.cpu.num_fp_insts 10 # number of float instructions
|
|
||||||
system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
|
|
||||||
system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
|
|
||||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
|
||||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
|
||||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
|
||||||
system.cpu.num_store_insts 868 # Number of store instructions
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_busy_cycles 115948 # Number of busy cycles
|
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
||||||
system.cpu.Branches 1056 # Number of branches fetched
|
|
||||||
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction
|
|
||||||
system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
||||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
||||||
system.cpu.op_class::total 6413 # Class of executed instruction
|
|
||||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
|
||||||
system.ruby.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.outstanding_req_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.outstanding_req_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.outstanding_req_hist_seqr::samples 8464
|
|
||||||
system.ruby.outstanding_req_hist_seqr::mean 1
|
|
||||||
system.ruby.outstanding_req_hist_seqr::gmean 1
|
|
||||||
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.outstanding_req_hist_seqr::total 8464
|
|
||||||
system.ruby.latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.latency_hist_seqr::samples 8463
|
|
||||||
system.ruby.latency_hist_seqr::mean 12.700579
|
|
||||||
system.ruby.latency_hist_seqr::gmean 1.992540
|
|
||||||
system.ruby.latency_hist_seqr::stdev 30.668579
|
|
||||||
system.ruby.latency_hist_seqr | 7444 87.96% 87.96% | 1001 11.83% 99.79% | 3 0.04% 99.82% | 0 0.00% 99.82% | 6 0.07% 99.89% | 8 0.09% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00%
|
|
||||||
system.ruby.latency_hist_seqr::total 8463
|
|
||||||
system.ruby.hit_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.hit_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.hit_latency_hist_seqr::samples 7041
|
|
||||||
system.ruby.hit_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.hit_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 7041 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.hit_latency_hist_seqr::total 7041
|
|
||||||
system.ruby.miss_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.miss_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.miss_latency_hist_seqr::samples 1422
|
|
||||||
system.ruby.miss_latency_hist_seqr::mean 70.635724
|
|
||||||
system.ruby.miss_latency_hist_seqr::gmean 60.522119
|
|
||||||
system.ruby.miss_latency_hist_seqr::stdev 39.545085
|
|
||||||
system.ruby.miss_latency_hist_seqr | 403 28.34% 28.34% | 1001 70.39% 98.73% | 3 0.21% 98.95% | 0 0.00% 98.95% | 6 0.42% 99.37% | 8 0.56% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00%
|
|
||||||
system.ruby.miss_latency_hist_seqr::total 1422
|
|
||||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1274 # Number of cache demand hits
|
|
||||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 776 # Number of cache demand misses
|
|
||||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
|
|
||||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
|
|
||||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
|
|
||||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
|
|
||||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits
|
|
||||||
system.ruby.l2_cntrl0.L2cache.demand_misses 1183 # Number of cache demand misses
|
|
||||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 1422 # Number of cache demand accesses
|
|
||||||
system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
|
||||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers0.percent_links_utilized 6.507012
|
|
||||||
system.ruby.network.routers0.msg_count.Request_Control::0 1422
|
|
||||||
system.ruby.network.routers0.msg_count.Response_Data::2 1183
|
|
||||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 239
|
|
||||||
system.ruby.network.routers0.msg_count.Writeback_Data::2 1309
|
|
||||||
system.ruby.network.routers0.msg_count.Writeback_Control::0 2710
|
|
||||||
system.ruby.network.routers0.msg_count.Unblock_Control::2 1468
|
|
||||||
system.ruby.network.routers0.msg_bytes.Request_Control::0 11376
|
|
||||||
system.ruby.network.routers0.msg_bytes.Response_Data::2 85176
|
|
||||||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208
|
|
||||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94248
|
|
||||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21680
|
|
||||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11744
|
|
||||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers1.percent_links_utilized 9.772915
|
|
||||||
system.ruby.network.routers1.msg_count.Request_Control::0 1422
|
|
||||||
system.ruby.network.routers1.msg_count.Request_Control::1 1183
|
|
||||||
system.ruby.network.routers1.msg_count.Response_Data::2 2366
|
|
||||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 239
|
|
||||||
system.ruby.network.routers1.msg_count.Writeback_Data::2 1503
|
|
||||||
system.ruby.network.routers1.msg_count.Writeback_Control::0 2710
|
|
||||||
system.ruby.network.routers1.msg_count.Writeback_Control::1 388
|
|
||||||
system.ruby.network.routers1.msg_count.Unblock_Control::2 2651
|
|
||||||
system.ruby.network.routers1.msg_bytes.Request_Control::0 11376
|
|
||||||
system.ruby.network.routers1.msg_bytes.Request_Control::1 9464
|
|
||||||
system.ruby.network.routers1.msg_bytes.Response_Data::2 170352
|
|
||||||
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 17208
|
|
||||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108216
|
|
||||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21680
|
|
||||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104
|
|
||||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21208
|
|
||||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers2.percent_links_utilized 3.265904
|
|
||||||
system.ruby.network.routers2.msg_count.Request_Control::1 1183
|
|
||||||
system.ruby.network.routers2.msg_count.Response_Data::2 1183
|
|
||||||
system.ruby.network.routers2.msg_count.Writeback_Data::2 194
|
|
||||||
system.ruby.network.routers2.msg_count.Writeback_Control::1 388
|
|
||||||
system.ruby.network.routers2.msg_count.Unblock_Control::2 1183
|
|
||||||
system.ruby.network.routers2.msg_bytes.Request_Control::1 9464
|
|
||||||
system.ruby.network.routers2.msg_bytes.Response_Data::2 85176
|
|
||||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968
|
|
||||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104
|
|
||||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9464
|
|
||||||
system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers3.percent_links_utilized 6.515277
|
|
||||||
system.ruby.network.routers3.msg_count.Request_Control::0 1422
|
|
||||||
system.ruby.network.routers3.msg_count.Request_Control::1 1183
|
|
||||||
system.ruby.network.routers3.msg_count.Response_Data::2 2366
|
|
||||||
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 239
|
|
||||||
system.ruby.network.routers3.msg_count.Writeback_Data::2 1503
|
|
||||||
system.ruby.network.routers3.msg_count.Writeback_Control::0 2710
|
|
||||||
system.ruby.network.routers3.msg_count.Writeback_Control::1 388
|
|
||||||
system.ruby.network.routers3.msg_count.Unblock_Control::2 2651
|
|
||||||
system.ruby.network.routers3.msg_bytes.Request_Control::0 11376
|
|
||||||
system.ruby.network.routers3.msg_bytes.Request_Control::1 9464
|
|
||||||
system.ruby.network.routers3.msg_bytes.Response_Data::2 170352
|
|
||||||
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 17208
|
|
||||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::2 108216
|
|
||||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21680
|
|
||||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 3104
|
|
||||||
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21208
|
|
||||||
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.msg_count.Request_Control 7815
|
|
||||||
system.ruby.network.msg_count.Response_Data 7098
|
|
||||||
system.ruby.network.msg_count.ResponseL2hit_Data 717
|
|
||||||
system.ruby.network.msg_count.Writeback_Data 4509
|
|
||||||
system.ruby.network.msg_count.Writeback_Control 9294
|
|
||||||
system.ruby.network.msg_count.Unblock_Control 7953
|
|
||||||
system.ruby.network.msg_byte.Request_Control 62520
|
|
||||||
system.ruby.network.msg_byte.Response_Data 511056
|
|
||||||
system.ruby.network.msg_byte.ResponseL2hit_Data 51624
|
|
||||||
system.ruby.network.msg_byte.Writeback_Data 324648
|
|
||||||
system.ruby.network.msg_byte.Writeback_Control 74352
|
|
||||||
system.ruby.network.msg_byte.Unblock_Control 63624
|
|
||||||
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers0.throttle0.link_utilization 6.103167
|
|
||||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1183
|
|
||||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239
|
|
||||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1355
|
|
||||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85176
|
|
||||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 17208
|
|
||||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10840
|
|
||||||
system.ruby.network.routers0.throttle1.link_utilization 6.910857
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1422
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1309
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1355
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 1468
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 11376
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 94248
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 10840
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 11744
|
|
||||||
system.ruby.network.routers1.throttle0.link_utilization 11.585797
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1422
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1183
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1309
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 1355
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 194
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 1468
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 11376
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 85176
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 94248
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 10840
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 1552
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 11744
|
|
||||||
system.ruby.network.routers1.throttle1.link_utilization 7.960034
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 1183
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 1183
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 239
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 194
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 1355
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 194
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 1183
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 9464
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 85176
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 17208
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 13968
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 10840
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 1552
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 9464
|
|
||||||
system.ruby.network.routers2.throttle0.link_utilization 1.856867
|
|
||||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 1183
|
|
||||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 194
|
|
||||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 194
|
|
||||||
system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 1183
|
|
||||||
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 9464
|
|
||||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 13968
|
|
||||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 1552
|
|
||||||
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 9464
|
|
||||||
system.ruby.network.routers2.throttle1.link_utilization 4.674940
|
|
||||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 1183
|
|
||||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 194
|
|
||||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 85176
|
|
||||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 1552
|
|
||||||
system.ruby.network.routers3.throttle0.link_utilization 6.103167
|
|
||||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 1183
|
|
||||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 239
|
|
||||||
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 1355
|
|
||||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 85176
|
|
||||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 17208
|
|
||||||
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 10840
|
|
||||||
system.ruby.network.routers3.throttle1.link_utilization 11.585797
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 1422
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 1183
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 1309
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 1355
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 194
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 1468
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 11376
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 85176
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 94248
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 10840
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 1552
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11744
|
|
||||||
system.ruby.network.routers3.throttle2.link_utilization 1.856867
|
|
||||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1183
|
|
||||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 194
|
|
||||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 194
|
|
||||||
system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 1183
|
|
||||||
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 9464
|
|
||||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 13968
|
|
||||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 1552
|
|
||||||
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9464
|
|
||||||
system.ruby.LD.latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.LD.latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.LD.latency_hist_seqr::samples 1185
|
|
||||||
system.ruby.LD.latency_hist_seqr::mean 29.289451
|
|
||||||
system.ruby.LD.latency_hist_seqr::gmean 5.875383
|
|
||||||
system.ruby.LD.latency_hist_seqr::stdev 39.627102
|
|
||||||
system.ruby.LD.latency_hist_seqr | 857 72.32% 72.32% | 323 27.26% 99.58% | 2 0.17% 99.75% | 0 0.00% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.latency_hist_seqr::total 1185
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::samples 659
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::total 659
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::samples 526
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::mean 64.731939
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::gmean 54.016248
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::stdev 35.753260
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr | 198 37.64% 37.64% | 323 61.41% 99.05% | 2 0.38% 99.43% | 0 0.00% 99.43% | 1 0.19% 99.62% | 2 0.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::total 526
|
|
||||||
system.ruby.ST.latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.ST.latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.ST.latency_hist_seqr::samples 865
|
|
||||||
system.ruby.ST.latency_hist_seqr::mean 17.729480
|
|
||||||
system.ruby.ST.latency_hist_seqr::gmean 3.104775
|
|
||||||
system.ruby.ST.latency_hist_seqr::stdev 31.273004
|
|
||||||
system.ruby.ST.latency_hist_seqr | 749 86.59% 86.59% | 115 13.29% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.latency_hist_seqr::total 865
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::samples 615
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 615 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::total 615
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::samples 250
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::mean 58.884000
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::gmean 50.399294
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::stdev 31.651062
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr | 134 53.60% 53.60% | 115 46.00% 99.60% | 0 0.00% 99.60% | 0 0.00% 99.60% | 0 0.00% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::total 250
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::samples 6413
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::mean 8.956962
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::gmean 1.536905
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::stdev 27.408738
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr | 5838 91.03% 91.03% | 563 8.78% 99.81% | 1 0.02% 99.83% | 0 0.00% 99.83% | 5 0.08% 99.91% | 5 0.08% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00%
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::total 6413
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5767
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::total 5767
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::samples 646
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::mean 79.990712
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 71.267502
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 42.993310
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr | 71 10.99% 10.99% | 563 87.15% 98.14% | 1 0.15% 98.30% | 0 0.00% 98.30% | 5 0.77% 99.07% | 5 0.77% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00%
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::total 646
|
|
||||||
system.ruby.Directory_Controller.GETX 198 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.GETS 985 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.PUTX 194 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Unblock 466 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Memory_Data 1183 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.S.GETS 519 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.SS.Memory_Data 519 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.L1_Replacement 1369 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Data 1126 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Exclusive_Data 296 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Writeback_Ack 46 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Writeback_Ack_Data 1309 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.All_acks 250 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Use_Timeout 296 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.I.Load 526 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.I.Ifetch 646 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.I.Store 191 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.S.Load 300 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.S.Ifetch 5767 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.S.Store 59 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.S.L1_Replacement 1060 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Load 79 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Store 18 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.L1_Replacement 27 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M_W.Load 39 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M_W.Store 1 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M_W.Use_Timeout 45 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM.Load 228 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM.Store 242 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM_W.Load 13 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM_W.Store 354 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 14 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM_W.Use_Timeout 251 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IM.Exclusive_Data 191 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.SM.Exclusive_Data 59 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.OM.All_acks 250 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IS.Data 1126 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IS.Exclusive_Data 46 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.SI.Writeback_Ack 46 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 1014 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 295 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L1_GETS 1172 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L1_GETX 250 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L1_PUTX 295 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L1_PUTS_only 1060 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.All_Acks 198 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.Data 1183 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L1_WBCLEANDATA 1014 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 295 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.Writeback_Ack 194 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.Unblock 1172 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.Exclusive_Unblock 296 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L2_Replacement 1194 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.NP.L1_GETS 985 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.NP.L1_GETX 132 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.ILS.L1_GETX 57 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 1014 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.ILX.L1_PUTX 295 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.S.L1_GETS 141 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.S.L1_GETX 7 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.S.L2_Replacement 907 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.SLS.L1_GETX 2 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 46 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.SLS.L2_Replacement 93 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.M.L1_GETS 46 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.M.L1_GETX 52 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.M.L2_Replacement 194 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 1014 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.SW.Unblock 46 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 295 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.IGS.Data 985 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.IGS.Unblock 985 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.IGM.Data 139 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.IGMLS.Data 59 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.IGMO.All_Acks 198 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 198 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 52 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.SS.Unblock 141 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 46 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.MI.Writeback_Ack 194 0.00% 0.00%
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,10 +0,0 @@
|
||||||
warn: rounding error > tolerance
|
|
||||||
1.250000 rounded to 1
|
|
||||||
warn: rounding error > tolerance
|
|
||||||
1.250000 rounded to 1
|
|
||||||
warn: rounding error > tolerance
|
|
||||||
1.250000 rounded to 1
|
|
||||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
|
||||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
|
||||||
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
|
|
||||||
|
|
@ -1,15 +0,0 @@
|
||||||
Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
|
|
||||||
Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
|
|
||||||
gem5 Simulator System. http://gem5.org
|
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
|
||||||
|
|
||||||
gem5 compiled Oct 13 2016 20:33:48
|
|
||||||
gem5 started Oct 13 2016 20:34:16
|
|
||||||
gem5 executing on e108600-lin, pid 27525
|
|
||||||
command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
|
|
||||||
|
|
||||||
Global frequency set at 1000000000 ticks per second
|
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
|
||||||
info: Increasing stack size by one page.
|
|
||||||
Hello world!
|
|
||||||
Exiting @ tick 113952 because target called exit()
|
|
||||||
|
|
@ -1,853 +0,0 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
|
||||||
sim_seconds 0.000114 # Number of seconds simulated
|
|
||||||
sim_ticks 113952 # Number of ticks simulated
|
|
||||||
final_tick 113952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
||||||
sim_freq 1000000000 # Frequency of simulated ticks
|
|
||||||
host_inst_rate 100852 # Simulator instruction rate (inst/s)
|
|
||||||
host_op_rate 100836 # Simulator op (including micro ops) rate (op/s)
|
|
||||||
host_tick_rate 1794284 # Simulator tick rate (ticks/s)
|
|
||||||
host_mem_usage 414264 # Number of bytes of host memory used
|
|
||||||
host_seconds 0.06 # Real time elapsed on the host
|
|
||||||
sim_insts 6403 # Number of instructions simulated
|
|
||||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
||||||
system.clk_domain.clock 1 # Clock period in ticks
|
|
||||||
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75456 # Number of bytes read from this memory
|
|
||||||
system.mem_ctrls.bytes_read::total 75456 # Number of bytes read from this memory
|
|
||||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14656 # Number of bytes written to this memory
|
|
||||||
system.mem_ctrls.bytes_written::total 14656 # Number of bytes written to this memory
|
|
||||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1179 # Number of read requests responded to by this memory
|
|
||||||
system.mem_ctrls.num_reads::total 1179 # Number of read requests responded to by this memory
|
|
||||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 229 # Number of write requests responded to by this memory
|
|
||||||
system.mem_ctrls.num_writes::total 229 # Number of write requests responded to by this memory
|
|
||||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 662173547 # Total read bandwidth from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_read::total 662173547 # Total read bandwidth from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 128615557 # Write bandwidth from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_write::total 128615557 # Write bandwidth from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 790789104 # Total bandwidth to/from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_total::total 790789104 # Total bandwidth to/from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.readReqs 1179 # Number of read requests accepted
|
|
||||||
system.mem_ctrls.writeReqs 229 # Number of write requests accepted
|
|
||||||
system.mem_ctrls.readBursts 1179 # Number of DRAM read bursts, including those serviced by the write queue
|
|
||||||
system.mem_ctrls.writeBursts 229 # Number of DRAM write bursts, including those merged in the write queue
|
|
||||||
system.mem_ctrls.bytesReadDRAM 64256 # Total number of bytes read from DRAM
|
|
||||||
system.mem_ctrls.bytesReadWrQ 11200 # Total number of bytes read from write queue
|
|
||||||
system.mem_ctrls.bytesWritten 5120 # Total number of bytes written to DRAM
|
|
||||||
system.mem_ctrls.bytesReadSys 75456 # Total read bytes from the system interface side
|
|
||||||
system.mem_ctrls.bytesWrittenSys 14656 # Total written bytes from the system interface side
|
|
||||||
system.mem_ctrls.servicedByWrQ 175 # Number of DRAM read bursts serviced by the write queue
|
|
||||||
system.mem_ctrls.mergedWrBursts 117 # Number of DRAM write bursts merged with an existing one
|
|
||||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
|
||||||
system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::4 92 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::10 51 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::11 53 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::13 360 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::15 45 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::4 20 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::10 2 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::13 15 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::14 37 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
|
||||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
|
||||||
system.mem_ctrls.totGap 113863 # Total gap between requests
|
|
||||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::6 1179 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::6 229 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.rdQLenPdf::0 1004 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.bytesPerActivate::samples 201 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::mean 338.149254 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::gmean 209.301438 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::stdev 329.237418 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::0-127 56 27.86% 27.86% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::128-255 54 26.87% 54.73% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::256-383 27 13.43% 68.16% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::384-511 9 4.48% 72.64% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::512-639 15 7.46% 80.10% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::640-767 6 2.99% 83.08% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::768-895 6 2.99% 86.07% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::896-1023 4 1.99% 88.06% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::1024-1151 24 11.94% 100.00% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::total 201 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::mean 138 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::gmean 99.720637 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::stdev 86.905121 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::80-87 1 20.00% 40.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::160-167 1 20.00% 60.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::208-215 1 20.00% 80.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::16 5 100.00% 100.00% # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.totQLat 13296 # Total ticks spent queuing
|
|
||||||
system.mem_ctrls.totMemAccLat 32372 # Total ticks spent from burst creation until serviced by the DRAM
|
|
||||||
system.mem_ctrls.totBusLat 5020 # Total ticks spent in databus transfers
|
|
||||||
system.mem_ctrls.avgQLat 13.24 # Average queueing delay per DRAM burst
|
|
||||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
|
||||||
system.mem_ctrls.avgMemAccLat 32.24 # Average memory access latency per DRAM burst
|
|
||||||
system.mem_ctrls.avgRdBW 563.89 # Average DRAM read bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.avgWrBW 44.93 # Average achieved write bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.avgRdBWSys 662.17 # Average system read bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.avgWrBWSys 128.62 # Average system write bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.busUtil 4.76 # Data bus utilization in percentage
|
|
||||||
system.mem_ctrls.busUtilRead 4.41 # Data bus utilization in percentage for reads
|
|
||||||
system.mem_ctrls.busUtilWrite 0.35 # Data bus utilization in percentage for writes
|
|
||||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
||||||
system.mem_ctrls.avgWrQLen 22.60 # Average write queue length when enqueuing
|
|
||||||
system.mem_ctrls.readRowHits 806 # Number of row buffer hits during reads
|
|
||||||
system.mem_ctrls.writeRowHits 73 # Number of row buffer hits during writes
|
|
||||||
system.mem_ctrls.readRowHitRate 80.28 # Row buffer hit rate for reads
|
|
||||||
system.mem_ctrls.writeRowHitRate 65.18 # Row buffer hit rate for writes
|
|
||||||
system.mem_ctrls.avgGap 80.87 # Average gap between requests
|
|
||||||
system.mem_ctrls.pageHitRate 78.76 # Row buffer hit rate, read and write combined
|
|
||||||
system.mem_ctrls_0.actEnergy 471240 # Energy for activate commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.preEnergy 255024 # Energy for precharge commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.readEnergy 4695264 # Energy for read commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.writeEnergy 217152 # Energy for write commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.refreshEnergy 9219600.000000 # Energy for refresh commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.actBackEnergy 7578264 # Energy for active background per rank (pJ)
|
|
||||||
system.mem_ctrls_0.preBackEnergy 292992 # Energy for precharge background per rank (pJ)
|
|
||||||
system.mem_ctrls_0.actPowerDownEnergy 33706152 # Energy for active power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_0.prePowerDownEnergy 7106688 # Energy for precharge power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_0.selfRefreshEnergy 1604640 # Energy for self refresh per rank (pJ)
|
|
||||||
system.mem_ctrls_0.totalEnergy 65147016 # Total energy per rank (pJ)
|
|
||||||
system.mem_ctrls_0.averagePower 570.509199 # Core power per rank (mW)
|
|
||||||
system.mem_ctrls_0.totalIdleTime 96809 # Total Idle time Per DRAM Rank
|
|
||||||
system.mem_ctrls_0.memoryStateTime::IDLE 351 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::REF 3653 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::SREF 4385 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 18507 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::ACT 13139 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 73917 # Time in different power states
|
|
||||||
system.mem_ctrls_1.actEnergy 992460 # Energy for activate commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.preEnergy 521640 # Energy for precharge commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.readEnergy 6774432 # Energy for read commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.writeEnergy 451008 # Energy for write commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.actBackEnergy 10831824 # Energy for active background per rank (pJ)
|
|
||||||
system.mem_ctrls_1.preBackEnergy 319872 # Energy for precharge background per rank (pJ)
|
|
||||||
system.mem_ctrls_1.actPowerDownEnergy 39423936 # Energy for active power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_1.prePowerDownEnergy 1117056 # Energy for precharge power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
|
||||||
system.mem_ctrls_1.totalEnergy 69037188 # Total energy per rank (pJ)
|
|
||||||
system.mem_ctrls_1.averagePower 605.844461 # Core power per rank (mW)
|
|
||||||
system.mem_ctrls_1.totalIdleTime 89154 # Total Idle time Per DRAM Rank
|
|
||||||
system.mem_ctrls_1.memoryStateTime::IDLE 259 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 2909 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::ACT 20688 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 86456 # Time in different power states
|
|
||||||
system.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
|
||||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
||||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
|
||||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
|
||||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
||||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
|
||||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 10 # DTB misses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
|
||||||
system.cpu.itb.fetch_hits 6414 # ITB hits
|
|
||||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_accesses 6431 # ITB accesses
|
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
||||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
|
||||||
system.cpu.pwrStateResidencyTicks::ON 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.cpu.numCycles 113952 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.committedInsts 6403 # Number of instructions committed
|
|
||||||
system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
|
|
||||||
system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
|
|
||||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
|
||||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
|
||||||
system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_int_insts 6329 # number of integer instructions
|
|
||||||
system.cpu.num_fp_insts 10 # number of float instructions
|
|
||||||
system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
|
|
||||||
system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
|
|
||||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
|
||||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
|
||||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
|
||||||
system.cpu.num_store_insts 868 # Number of store instructions
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_busy_cycles 113952 # Number of busy cycles
|
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
||||||
system.cpu.Branches 1056 # Number of branches fetched
|
|
||||||
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction
|
|
||||||
system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
||||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
||||||
system.cpu.op_class::total 6413 # Class of executed instruction
|
|
||||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
|
||||||
system.ruby.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.outstanding_req_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.outstanding_req_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.outstanding_req_hist_seqr::samples 8464
|
|
||||||
system.ruby.outstanding_req_hist_seqr::mean 1
|
|
||||||
system.ruby.outstanding_req_hist_seqr::gmean 1
|
|
||||||
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.outstanding_req_hist_seqr::total 8464
|
|
||||||
system.ruby.latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.latency_hist_seqr::samples 8463
|
|
||||||
system.ruby.latency_hist_seqr::mean 12.464729
|
|
||||||
system.ruby.latency_hist_seqr::gmean 1.971984
|
|
||||||
system.ruby.latency_hist_seqr::stdev 29.823065
|
|
||||||
system.ruby.latency_hist_seqr | 7459 88.14% 88.14% | 983 11.62% 99.75% | 7 0.08% 99.83% | 3 0.04% 99.87% | 5 0.06% 99.93% | 5 0.06% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00%
|
|
||||||
system.ruby.latency_hist_seqr::total 8463
|
|
||||||
system.ruby.hit_latency_hist_seqr::bucket_size 8
|
|
||||||
system.ruby.hit_latency_hist_seqr::max_bucket 79
|
|
||||||
system.ruby.hit_latency_hist_seqr::samples 7284
|
|
||||||
system.ruby.hit_latency_hist_seqr::mean 1.636052
|
|
||||||
system.ruby.hit_latency_hist_seqr::gmean 1.092653
|
|
||||||
system.ruby.hit_latency_hist_seqr::stdev 3.757041
|
|
||||||
system.ruby.hit_latency_hist_seqr | 7080 97.20% 97.20% | 0 0.00% 97.20% | 21 0.29% 97.49% | 182 2.50% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.hit_latency_hist_seqr::total 7284
|
|
||||||
system.ruby.miss_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.miss_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.miss_latency_hist_seqr::samples 1179
|
|
||||||
system.ruby.miss_latency_hist_seqr::mean 79.365564
|
|
||||||
system.ruby.miss_latency_hist_seqr::gmean 75.701428
|
|
||||||
system.ruby.miss_latency_hist_seqr::stdev 33.123085
|
|
||||||
system.ruby.miss_latency_hist_seqr | 175 14.84% 14.84% | 983 83.38% 98.22% | 7 0.59% 98.81% | 3 0.25% 99.07% | 5 0.42% 99.49% | 5 0.42% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00%
|
|
||||||
system.ruby.miss_latency_hist_seqr::total 1179
|
|
||||||
system.ruby.Directory.incomplete_times_seqr 1178
|
|
||||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1313 # Number of cache demand hits
|
|
||||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 737 # Number of cache demand misses
|
|
||||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
|
|
||||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
|
|
||||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
|
|
||||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
|
|
||||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.l2_cntrl0.L2cache.demand_hits 187 # Number of cache demand hits
|
|
||||||
system.ruby.l2_cntrl0.L2cache.demand_misses 1196 # Number of cache demand misses
|
|
||||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses
|
|
||||||
system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
|
||||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers0.percent_links_utilized 5.719513
|
|
||||||
system.ruby.network.routers0.msg_count.Request_Control::1 1383
|
|
||||||
system.ruby.network.routers0.msg_count.Response_Data::4 1179
|
|
||||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 204
|
|
||||||
system.ruby.network.routers0.msg_count.Response_Control::4 1
|
|
||||||
system.ruby.network.routers0.msg_count.Writeback_Data::4 1355
|
|
||||||
system.ruby.network.routers0.msg_count.Persistent_Control::3 44
|
|
||||||
system.ruby.network.routers0.msg_bytes.Request_Control::1 11064
|
|
||||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 84888
|
|
||||||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14688
|
|
||||||
system.ruby.network.routers0.msg_bytes.Response_Control::4 8
|
|
||||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97560
|
|
||||||
system.ruby.network.routers0.msg_bytes.Persistent_Control::3 352
|
|
||||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers1.percent_links_utilized 4.313658
|
|
||||||
system.ruby.network.routers1.msg_count.Request_Control::1 1383
|
|
||||||
system.ruby.network.routers1.msg_count.Request_Control::2 1196
|
|
||||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 204
|
|
||||||
system.ruby.network.routers1.msg_count.Response_Control::4 1
|
|
||||||
system.ruby.network.routers1.msg_count.Writeback_Data::4 1584
|
|
||||||
system.ruby.network.routers1.msg_count.Writeback_Control::4 968
|
|
||||||
system.ruby.network.routers1.msg_count.Persistent_Control::3 22
|
|
||||||
system.ruby.network.routers1.msg_bytes.Request_Control::1 11064
|
|
||||||
system.ruby.network.routers1.msg_bytes.Request_Control::2 9568
|
|
||||||
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 14688
|
|
||||||
system.ruby.network.routers1.msg_bytes.Response_Control::4 8
|
|
||||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::4 114048
|
|
||||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7744
|
|
||||||
system.ruby.network.routers1.msg_bytes.Persistent_Control::3 176
|
|
||||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers2.percent_links_utilized 3.259706
|
|
||||||
system.ruby.network.routers2.msg_count.Request_Control::2 1196
|
|
||||||
system.ruby.network.routers2.msg_count.Response_Data::4 1179
|
|
||||||
system.ruby.network.routers2.msg_count.Writeback_Data::4 229
|
|
||||||
system.ruby.network.routers2.msg_count.Writeback_Control::4 968
|
|
||||||
system.ruby.network.routers2.msg_count.Persistent_Control::3 22
|
|
||||||
system.ruby.network.routers2.msg_bytes.Request_Control::2 9568
|
|
||||||
system.ruby.network.routers2.msg_bytes.Response_Data::4 84888
|
|
||||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::4 16488
|
|
||||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7744
|
|
||||||
system.ruby.network.routers2.msg_bytes.Persistent_Control::3 176
|
|
||||||
system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers3.percent_links_utilized 4.430959
|
|
||||||
system.ruby.network.routers3.msg_count.Request_Control::1 1383
|
|
||||||
system.ruby.network.routers3.msg_count.Request_Control::2 1196
|
|
||||||
system.ruby.network.routers3.msg_count.Response_Data::4 1179
|
|
||||||
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 204
|
|
||||||
system.ruby.network.routers3.msg_count.Response_Control::4 1
|
|
||||||
system.ruby.network.routers3.msg_count.Writeback_Data::4 1584
|
|
||||||
system.ruby.network.routers3.msg_count.Writeback_Control::4 968
|
|
||||||
system.ruby.network.routers3.msg_count.Persistent_Control::3 44
|
|
||||||
system.ruby.network.routers3.msg_bytes.Request_Control::1 11064
|
|
||||||
system.ruby.network.routers3.msg_bytes.Request_Control::2 9568
|
|
||||||
system.ruby.network.routers3.msg_bytes.Response_Data::4 84888
|
|
||||||
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 14688
|
|
||||||
system.ruby.network.routers3.msg_bytes.Response_Control::4 8
|
|
||||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::4 114048
|
|
||||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::4 7744
|
|
||||||
system.ruby.network.routers3.msg_bytes.Persistent_Control::3 352
|
|
||||||
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.msg_count.Request_Control 7737
|
|
||||||
system.ruby.network.msg_count.Response_Data 3537
|
|
||||||
system.ruby.network.msg_count.ResponseL2hit_Data 612
|
|
||||||
system.ruby.network.msg_count.Response_Control 3
|
|
||||||
system.ruby.network.msg_count.Writeback_Data 4752
|
|
||||||
system.ruby.network.msg_count.Writeback_Control 2904
|
|
||||||
system.ruby.network.msg_count.Persistent_Control 132
|
|
||||||
system.ruby.network.msg_byte.Request_Control 61896
|
|
||||||
system.ruby.network.msg_byte.Response_Data 254664
|
|
||||||
system.ruby.network.msg_byte.ResponseL2hit_Data 44064
|
|
||||||
system.ruby.network.msg_byte.Response_Control 24
|
|
||||||
system.ruby.network.msg_byte.Writeback_Data 342144
|
|
||||||
system.ruby.network.msg_byte.Writeback_Control 23232
|
|
||||||
system.ruby.network.msg_byte.Persistent_Control 1056
|
|
||||||
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers0.throttle0.link_utilization 5.471602
|
|
||||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1179
|
|
||||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 204
|
|
||||||
system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1
|
|
||||||
system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 22
|
|
||||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 84888
|
|
||||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 14688
|
|
||||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8
|
|
||||||
system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 176
|
|
||||||
system.ruby.network.routers0.throttle1.link_utilization 5.967425
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 1383
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 1355
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 22
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 11064
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 97560
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 176
|
|
||||||
system.ruby.network.routers1.throttle0.link_utilization 5.967425
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 1383
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 1355
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 22
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 11064
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 97560
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 176
|
|
||||||
system.ruby.network.routers1.throttle1.link_utilization 2.659892
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1196
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 204
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 229
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 968
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 9568
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 14688
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 16488
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 7744
|
|
||||||
system.ruby.network.routers2.throttle0.link_utilization 1.863504
|
|
||||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 1196
|
|
||||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 229
|
|
||||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 968
|
|
||||||
system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 22
|
|
||||||
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 9568
|
|
||||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 16488
|
|
||||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 7744
|
|
||||||
system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 176
|
|
||||||
system.ruby.network.routers2.throttle1.link_utilization 4.655908
|
|
||||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1179
|
|
||||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 84888
|
|
||||||
system.ruby.network.routers3.throttle0.link_utilization 5.461949
|
|
||||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 1179
|
|
||||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 204
|
|
||||||
system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1
|
|
||||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 84888
|
|
||||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 14688
|
|
||||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8
|
|
||||||
system.ruby.network.routers3.throttle1.link_utilization 5.967425
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 1383
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 1355
|
|
||||||
system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 22
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 11064
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 97560
|
|
||||||
system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 176
|
|
||||||
system.ruby.network.routers3.throttle2.link_utilization 1.863504
|
|
||||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 1196
|
|
||||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 229
|
|
||||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 968
|
|
||||||
system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 22
|
|
||||||
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 9568
|
|
||||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 16488
|
|
||||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 7744
|
|
||||||
system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 176
|
|
||||||
system.ruby.LD.latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.LD.latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.LD.latency_hist_seqr::samples 1185
|
|
||||||
system.ruby.LD.latency_hist_seqr::mean 29.824473
|
|
||||||
system.ruby.LD.latency_hist_seqr::gmean 6.089961
|
|
||||||
system.ruby.LD.latency_hist_seqr::stdev 38.602832
|
|
||||||
system.ruby.LD.latency_hist_seqr | 854 72.07% 72.07% | 327 27.59% 99.66% | 2 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.latency_hist_seqr::total 1185
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::bucket_size 4
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::max_bucket 39
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::samples 759
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::mean 4.025033
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::gmean 1.519643
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::stdev 7.772026
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr | 659 86.82% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 1 0.13% 86.96% | 99 13.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::total 759
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::samples 426
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::mean 75.791080
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::gmean 72.234894
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::stdev 27.150058
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr | 95 22.30% 22.30% | 327 76.76% 99.06% | 2 0.47% 99.53% | 0 0.00% 99.53% | 0 0.00% 99.53% | 2 0.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::total 426
|
|
||||||
system.ruby.ST.latency_hist_seqr::bucket_size 32
|
|
||||||
system.ruby.ST.latency_hist_seqr::max_bucket 319
|
|
||||||
system.ruby.ST.latency_hist_seqr::samples 865
|
|
||||||
system.ruby.ST.latency_hist_seqr::mean 14.804624
|
|
||||||
system.ruby.ST.latency_hist_seqr::gmean 2.602855
|
|
||||||
system.ruby.ST.latency_hist_seqr::stdev 29.163214
|
|
||||||
system.ruby.ST.latency_hist_seqr | 697 80.58% 80.58% | 80 9.25% 89.83% | 83 9.60% 99.42% | 2 0.23% 99.65% | 0 0.00% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00%
|
|
||||||
system.ruby.ST.latency_hist_seqr::total 865
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::bucket_size 4
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::max_bucket 39
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::samples 697
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::mean 2.317073
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::gmean 1.210984
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::stdev 5.162159
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr | 654 93.83% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 20 2.87% 96.70% | 23 3.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::total 697
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::bucket_size 32
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::max_bucket 319
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::samples 168
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::mean 66.613095
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::gmean 62.251080
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::stdev 30.627944
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 80 47.62% 47.62% | 83 49.40% 97.02% | 2 1.19% 98.21% | 0 0.00% 98.21% | 1 0.60% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 0 0.00% 99.40% | 1 0.60% 100.00%
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::total 168
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::samples 6413
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::mean 8.941369
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::gmean 1.542249
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::stdev 26.742382
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr | 5828 90.88% 90.88% | 571 8.90% 99.78% | 4 0.06% 99.84% | 2 0.03% 99.88% | 4 0.06% 99.94% | 3 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00%
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::total 6413
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 8
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 79
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5828
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.243480
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.033914
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::stdev 2.376718
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr | 5767 98.95% 98.95% | 0 0.00% 98.95% | 0 0.00% 98.95% | 60 1.03% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::total 5828
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::samples 585
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::mean 85.630769
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 82.856413
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 36.234733
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 4 0.68% 98.29% | 2 0.34% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::total 585
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7080
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7080 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7080
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 8
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 79
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 204
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.710784
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.661395
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.615711
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 10.29% 10.29% | 182 89.22% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 204
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1179
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 79.365564
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 75.701428
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.123085
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr | 175 14.84% 14.84% | 983 83.38% 98.22% | 7 0.59% 98.81% | 3 0.25% 99.07% | 5 0.42% 99.49% | 5 0.42% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00%
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1179
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 16
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 159
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 82
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 82.000000
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 659
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 659
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 100
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.960000
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.956283
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 0.400000
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 1.00% 1.00% | 99 99.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 100
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 426
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 75.791080
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 72.234894
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.150058
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 95 22.30% 22.30% | 327 76.76% 99.06% | 2 0.47% 99.53% | 0 0.00% 99.53% | 0 0.00% 99.53% | 2 0.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 426
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 654
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 654
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 43
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.348837
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.264733
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.938135
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 46.51% 46.51% | 23 53.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 43
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 168
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 66.613095
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 62.251080
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 30.627944
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 80 47.62% 47.62% | 83 49.40% 97.02% | 2 1.19% 98.21% | 0 0.00% 98.21% | 1 0.60% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 0 0.00% 99.40% | 1 0.60% 100.00%
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 168
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5767
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5767
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 8
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 79
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 61
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24.262295
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.201824
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 2.048590
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 60 98.36% 98.36% | 0 0.00% 98.36% | 1 1.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 61
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 585
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 85.630769
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 82.856413
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.234733
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 4 0.68% 98.29% | 2 0.34% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 585
|
|
||||||
system.ruby.Directory_Controller.GETX 208 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.GETS 1017 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Lockdown 11 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Unlockdown 11 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Data_All_Tokens 220 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Ack_Owner_All_Tokens 905 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Ack_All_Tokens 34 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Memory_Data 1179 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Memory_Ack 229 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.O.GETS 1011 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.NO.GETX 17 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.NO.Data_All_Tokens 220 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 905 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.L.Unlockdown 11 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.O_W.GETS 6 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.O_W.Memory_Ack 229 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.L_NO_W.Memory_Data 11 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.NO_W.Lockdown 11 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.NO_W.Memory_Data 1168 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.L1_Replacement 1368 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Data_Shared 161 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Data_All_Tokens 1222 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Ack 1 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 22 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Request_Timeout 11 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 1221 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.NP.Load 526 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.NP.Ifetch 646 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.NP.Store 191 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.S.Load 153 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.S.Ifetch 331 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.S.Store 20 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.S.L1_Replacement 141 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Load 181 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Ifetch 3196 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Store 33 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.L1_Replacement 946 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 11 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM.Load 218 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM.Store 265 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M_W.Load 84 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M_W.Ifetch 2240 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M_W.Store 25 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M_W.L1_Replacement 9 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 985 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM_W.Load 23 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM_W.Store 331 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 4 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 236 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IM.Data_All_Tokens 191 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IM.Ack 1 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.SM.Data_All_Tokens 20 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IS.Data_Shared 161 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IS.Data_All_Tokens 1011 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 11 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IS.Request_Timeout 11 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L1_GETS 1123 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L1_GETS_Last_Token 49 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L1_GETX 211 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.L2_Replacement 1266 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.Writeback_Shared_Data 84 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.Writeback_All_Tokens 1271 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.Persistent_GETS 11 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 11 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.NP.L1_GETS 1011 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.NP.L1_GETX 166 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 81 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 1193 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 11 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.I.L1_GETX 1 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.I.L2_Replacement 69 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 3 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 21 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 49 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.S.L2_Replacement 34 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.O.L1_GETX 17 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.O.L2_Replacement 38 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 57 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.M.L1_GETS 112 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.M.L2_Replacement 1125 0.00% 0.00%
|
|
||||||
system.ruby.L2Cache_Controller.I_L.Persistent_GETS 11 0.00% 0.00%
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,10 +0,0 @@
|
||||||
warn: rounding error > tolerance
|
|
||||||
1.250000 rounded to 1
|
|
||||||
warn: rounding error > tolerance
|
|
||||||
1.250000 rounded to 1
|
|
||||||
warn: rounding error > tolerance
|
|
||||||
1.250000 rounded to 1
|
|
||||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
|
||||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
|
||||||
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
|
|
||||||
|
|
@ -1,15 +0,0 @@
|
||||||
Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
|
|
||||||
Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
|
|
||||||
gem5 Simulator System. http://gem5.org
|
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
|
||||||
|
|
||||||
gem5 compiled Oct 13 2016 20:24:36
|
|
||||||
gem5 started Oct 13 2016 20:24:58
|
|
||||||
gem5 executing on e108600-lin, pid 38872
|
|
||||||
command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
|
|
||||||
|
|
||||||
Global frequency set at 1000000000 ticks per second
|
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
|
||||||
info: Increasing stack size by one page.
|
|
||||||
Hello world!
|
|
||||||
Exiting @ tick 93323 because target called exit()
|
|
||||||
|
|
@ -1,782 +0,0 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
|
||||||
sim_seconds 0.000093 # Number of seconds simulated
|
|
||||||
sim_ticks 93323 # Number of ticks simulated
|
|
||||||
final_tick 93323 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
||||||
sim_freq 1000000000 # Frequency of simulated ticks
|
|
||||||
host_inst_rate 111182 # Simulator instruction rate (inst/s)
|
|
||||||
host_op_rate 111161 # Simulator op (including micro ops) rate (op/s)
|
|
||||||
host_tick_rate 1619882 # Simulator tick rate (ticks/s)
|
|
||||||
host_mem_usage 412912 # Number of bytes of host memory used
|
|
||||||
host_seconds 0.06 # Real time elapsed on the host
|
|
||||||
sim_insts 6403 # Number of instructions simulated
|
|
||||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
||||||
system.clk_domain.clock 1 # Clock period in ticks
|
|
||||||
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
|
|
||||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74240 # Number of bytes read from this memory
|
|
||||||
system.mem_ctrls.bytes_read::total 74240 # Number of bytes read from this memory
|
|
||||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14080 # Number of bytes written to this memory
|
|
||||||
system.mem_ctrls.bytes_written::total 14080 # Number of bytes written to this memory
|
|
||||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1160 # Number of read requests responded to by this memory
|
|
||||||
system.mem_ctrls.num_reads::total 1160 # Number of read requests responded to by this memory
|
|
||||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 220 # Number of write requests responded to by this memory
|
|
||||||
system.mem_ctrls.num_writes::total 220 # Number of write requests responded to by this memory
|
|
||||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 795516646 # Total read bandwidth from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_read::total 795516646 # Total read bandwidth from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 150873847 # Write bandwidth from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_write::total 150873847 # Write bandwidth from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 946390493 # Total bandwidth to/from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.bw_total::total 946390493 # Total bandwidth to/from this memory (bytes/s)
|
|
||||||
system.mem_ctrls.readReqs 1160 # Number of read requests accepted
|
|
||||||
system.mem_ctrls.writeReqs 220 # Number of write requests accepted
|
|
||||||
system.mem_ctrls.readBursts 1160 # Number of DRAM read bursts, including those serviced by the write queue
|
|
||||||
system.mem_ctrls.writeBursts 220 # Number of DRAM write bursts, including those merged in the write queue
|
|
||||||
system.mem_ctrls.bytesReadDRAM 63488 # Total number of bytes read from DRAM
|
|
||||||
system.mem_ctrls.bytesReadWrQ 10752 # Total number of bytes read from write queue
|
|
||||||
system.mem_ctrls.bytesWritten 5248 # Total number of bytes written to DRAM
|
|
||||||
system.mem_ctrls.bytesReadSys 74240 # Total read bytes from the system interface side
|
|
||||||
system.mem_ctrls.bytesWrittenSys 14080 # Total written bytes from the system interface side
|
|
||||||
system.mem_ctrls.servicedByWrQ 168 # Number of DRAM read bursts serviced by the write queue
|
|
||||||
system.mem_ctrls.mergedWrBursts 109 # Number of DRAM write bursts merged with an existing one
|
|
||||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
|
||||||
system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::4 90 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::10 54 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::11 47 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::13 358 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::14 60 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::4 17 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::10 2 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::13 15 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::14 42 # Per bank write bursts
|
|
||||||
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
|
|
||||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
|
||||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
|
||||||
system.mem_ctrls.totGap 93245 # Total gap between requests
|
|
||||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.readPktSize::6 1160 # Read request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.writePktSize::6 220 # Write request sizes (log2)
|
|
||||||
system.mem_ctrls.rdQLenPdf::0 992 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
|
||||||
system.mem_ctrls.bytesPerActivate::samples 185 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::mean 364.627027 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::gmean 225.304848 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::stdev 344.102671 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::0-127 47 25.41% 25.41% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::128-255 51 27.57% 52.97% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::256-383 22 11.89% 64.86% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::384-511 11 5.95% 70.81% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::512-639 10 5.41% 76.22% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::640-767 6 3.24% 79.46% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::768-895 6 3.24% 82.70% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::896-1023 9 4.86% 87.57% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::1024-1151 23 12.43% 100.00% # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.bytesPerActivate::total 185 # Bytes accessed per row activation
|
|
||||||
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::mean 135.600000 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::gmean 103.520831 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::stdev 76.774345 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::184-191 1 20.00% 80.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
|
|
||||||
system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::mean 16.400000 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::gmean 16.381380 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::stdev 0.894427 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::16 4 80.00% 80.00% # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::18 1 20.00% 100.00% # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
|
|
||||||
system.mem_ctrls.totQLat 12811 # Total ticks spent queuing
|
|
||||||
system.mem_ctrls.totMemAccLat 31659 # Total ticks spent from burst creation until serviced by the DRAM
|
|
||||||
system.mem_ctrls.totBusLat 4960 # Total ticks spent in databus transfers
|
|
||||||
system.mem_ctrls.avgQLat 12.91 # Average queueing delay per DRAM burst
|
|
||||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
|
||||||
system.mem_ctrls.avgMemAccLat 31.91 # Average memory access latency per DRAM burst
|
|
||||||
system.mem_ctrls.avgRdBW 680.30 # Average DRAM read bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.avgWrBW 56.23 # Average achieved write bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.avgRdBWSys 795.52 # Average system read bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.avgWrBWSys 150.87 # Average system write bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
||||||
system.mem_ctrls.busUtil 5.75 # Data bus utilization in percentage
|
|
||||||
system.mem_ctrls.busUtilRead 5.31 # Data bus utilization in percentage for reads
|
|
||||||
system.mem_ctrls.busUtilWrite 0.44 # Data bus utilization in percentage for writes
|
|
||||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
||||||
system.mem_ctrls.avgWrQLen 22.62 # Average write queue length when enqueuing
|
|
||||||
system.mem_ctrls.readRowHits 805 # Number of row buffer hits during reads
|
|
||||||
system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes
|
|
||||||
system.mem_ctrls.readRowHitRate 81.15 # Row buffer hit rate for reads
|
|
||||||
system.mem_ctrls.writeRowHitRate 70.27 # Row buffer hit rate for writes
|
|
||||||
system.mem_ctrls.avgGap 67.57 # Average gap between requests
|
|
||||||
system.mem_ctrls.pageHitRate 80.05 # Row buffer hit rate, read and write combined
|
|
||||||
system.mem_ctrls_0.actEnergy 449820 # Energy for activate commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.preEnergy 235704 # Energy for precharge commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.readEnergy 4672416 # Energy for read commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.writeEnergy 192096 # Energy for write commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.refreshEnergy 7375680.000000 # Energy for refresh commands per rank (pJ)
|
|
||||||
system.mem_ctrls_0.actBackEnergy 7678128 # Energy for active background per rank (pJ)
|
|
||||||
system.mem_ctrls_0.preBackEnergy 246528 # Energy for precharge background per rank (pJ)
|
|
||||||
system.mem_ctrls_0.actPowerDownEnergy 28111488 # Energy for active power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_0.prePowerDownEnergy 4554240 # Energy for precharge power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_0.selfRefreshEnergy 1112640 # Energy for self refresh per rank (pJ)
|
|
||||||
system.mem_ctrls_0.totalEnergy 54628740 # Total energy per rank (pJ)
|
|
||||||
system.mem_ctrls_0.averagePower 585.372738 # Core power per rank (mW)
|
|
||||||
system.mem_ctrls_0.totalIdleTime 75800 # Total Idle time Per DRAM Rank
|
|
||||||
system.mem_ctrls_0.memoryStateTime::IDLE 328 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::REF 3126 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::SREF 2335 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 11860 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::ACT 14026 # Time in different power states
|
|
||||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 61648 # Time in different power states
|
|
||||||
system.mem_ctrls_1.actEnergy 913920 # Energy for activate commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.preEnergy 479136 # Energy for precharge commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.readEnergy 6660192 # Energy for read commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.writeEnergy 492768 # Energy for write commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ)
|
|
||||||
system.mem_ctrls_1.actBackEnergy 10312440 # Energy for active background per rank (pJ)
|
|
||||||
system.mem_ctrls_1.preBackEnergy 226560 # Energy for precharge background per rank (pJ)
|
|
||||||
system.mem_ctrls_1.actPowerDownEnergy 31424328 # Energy for active power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_1.prePowerDownEnergy 462720 # Energy for precharge power-down per rank (pJ)
|
|
||||||
system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
|
||||||
system.mem_ctrls_1.totalEnergy 57733104 # Total energy per rank (pJ)
|
|
||||||
system.mem_ctrls_1.averagePower 618.637463 # Core power per rank (mW)
|
|
||||||
system.mem_ctrls_1.totalIdleTime 69937 # Total Idle time Per DRAM Rank
|
|
||||||
system.mem_ctrls_1.memoryStateTime::IDLE 212 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 1205 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::ACT 20133 # Time in different power states
|
|
||||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 68913 # Time in different power states
|
|
||||||
system.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
|
|
||||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
|
||||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
||||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
|
||||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
|
||||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
||||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
|
||||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 10 # DTB misses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
|
||||||
system.cpu.itb.fetch_hits 6414 # ITB hits
|
|
||||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_accesses 6431 # ITB accesses
|
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
||||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
|
||||||
system.cpu.pwrStateResidencyTicks::ON 93323 # Cumulative time (in ticks) in various power states
|
|
||||||
system.cpu.numCycles 93323 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.committedInsts 6403 # Number of instructions committed
|
|
||||||
system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
|
|
||||||
system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
|
|
||||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
|
||||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
|
||||||
system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_int_insts 6329 # number of integer instructions
|
|
||||||
system.cpu.num_fp_insts 10 # number of float instructions
|
|
||||||
system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
|
|
||||||
system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
|
|
||||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
|
||||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
|
||||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
|
||||||
system.cpu.num_store_insts 868 # Number of store instructions
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_busy_cycles 93323 # Number of busy cycles
|
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
||||||
system.cpu.Branches 1056 # Number of branches fetched
|
|
||||||
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction
|
|
||||||
system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction
|
|
||||||
system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction
|
|
||||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
||||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
||||||
system.cpu.op_class::total 6413 # Class of executed instruction
|
|
||||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
|
||||||
system.ruby.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.outstanding_req_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.outstanding_req_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.outstanding_req_hist_seqr::samples 8464
|
|
||||||
system.ruby.outstanding_req_hist_seqr::mean 1
|
|
||||||
system.ruby.outstanding_req_hist_seqr::gmean 1
|
|
||||||
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.outstanding_req_hist_seqr::total 8464
|
|
||||||
system.ruby.latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.latency_hist_seqr::samples 8463
|
|
||||||
system.ruby.latency_hist_seqr::mean 10.027177
|
|
||||||
system.ruby.latency_hist_seqr::gmean 1.860537
|
|
||||||
system.ruby.latency_hist_seqr::stdev 25.112208
|
|
||||||
system.ruby.latency_hist_seqr | 8219 97.12% 97.12% | 231 2.73% 99.85% | 1 0.01% 99.86% | 1 0.01% 99.87% | 5 0.06% 99.93% | 5 0.06% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00%
|
|
||||||
system.ruby.latency_hist_seqr::total 8463
|
|
||||||
system.ruby.hit_latency_hist_seqr::bucket_size 2
|
|
||||||
system.ruby.hit_latency_hist_seqr::max_bucket 19
|
|
||||||
system.ruby.hit_latency_hist_seqr::samples 7303
|
|
||||||
system.ruby.hit_latency_hist_seqr::mean 1.277968
|
|
||||||
system.ruby.hit_latency_hist_seqr::gmean 1.068925
|
|
||||||
system.ruby.hit_latency_hist_seqr::stdev 1.644014
|
|
||||||
system.ruby.hit_latency_hist_seqr | 7100 97.22% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 203 2.78% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.hit_latency_hist_seqr::total 7303
|
|
||||||
system.ruby.miss_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.miss_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.miss_latency_hist_seqr::samples 1160
|
|
||||||
system.ruby.miss_latency_hist_seqr::mean 65.109483
|
|
||||||
system.ruby.miss_latency_hist_seqr::gmean 60.947221
|
|
||||||
system.ruby.miss_latency_hist_seqr::stdev 32.683425
|
|
||||||
system.ruby.miss_latency_hist_seqr | 916 78.97% 78.97% | 231 19.91% 98.88% | 1 0.09% 98.97% | 1 0.09% 99.05% | 5 0.43% 99.48% | 5 0.43% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 1 0.09% 100.00%
|
|
||||||
system.ruby.miss_latency_hist_seqr::total 1160
|
|
||||||
system.ruby.Directory.incomplete_times_seqr 1159
|
|
||||||
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
|
|
||||||
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
|
|
||||||
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
|
|
||||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1333 # Number of cache demand hits
|
|
||||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 717 # Number of cache demand misses
|
|
||||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
|
|
||||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
|
|
||||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
|
|
||||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
|
|
||||||
system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits
|
|
||||||
system.ruby.l1_cntrl0.L2cache.demand_misses 1160 # Number of cache demand misses
|
|
||||||
system.ruby.l1_cntrl0.L2cache.demand_accesses 1363 # Number of cache demand accesses
|
|
||||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.l1_cntrl0.fully_busy_cycles 7 # cycles for which number of transistions == max transitions
|
|
||||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
|
||||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers0.percent_links_utilized 4.809104
|
|
||||||
system.ruby.network.routers0.msg_count.Request_Control::2 1160
|
|
||||||
system.ruby.network.routers0.msg_count.Response_Data::4 1160
|
|
||||||
system.ruby.network.routers0.msg_count.Writeback_Data::5 220
|
|
||||||
system.ruby.network.routers0.msg_count.Writeback_Control::2 1144
|
|
||||||
system.ruby.network.routers0.msg_count.Writeback_Control::3 1144
|
|
||||||
system.ruby.network.routers0.msg_count.Writeback_Control::5 924
|
|
||||||
system.ruby.network.routers0.msg_count.Unblock_Control::5 1160
|
|
||||||
system.ruby.network.routers0.msg_bytes.Request_Control::2 9280
|
|
||||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 83520
|
|
||||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::5 15840
|
|
||||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9152
|
|
||||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9152
|
|
||||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7392
|
|
||||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9280
|
|
||||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers1.percent_links_utilized 4.808836
|
|
||||||
system.ruby.network.routers1.msg_count.Request_Control::2 1160
|
|
||||||
system.ruby.network.routers1.msg_count.Response_Data::4 1160
|
|
||||||
system.ruby.network.routers1.msg_count.Writeback_Data::5 220
|
|
||||||
system.ruby.network.routers1.msg_count.Writeback_Control::2 1144
|
|
||||||
system.ruby.network.routers1.msg_count.Writeback_Control::3 1144
|
|
||||||
system.ruby.network.routers1.msg_count.Writeback_Control::5 924
|
|
||||||
system.ruby.network.routers1.msg_count.Unblock_Control::5 1159
|
|
||||||
system.ruby.network.routers1.msg_bytes.Request_Control::2 9280
|
|
||||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 83520
|
|
||||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840
|
|
||||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9152
|
|
||||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9152
|
|
||||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7392
|
|
||||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272
|
|
||||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers2.percent_links_utilized 4.809104
|
|
||||||
system.ruby.network.routers2.msg_count.Request_Control::2 1160
|
|
||||||
system.ruby.network.routers2.msg_count.Response_Data::4 1160
|
|
||||||
system.ruby.network.routers2.msg_count.Writeback_Data::5 220
|
|
||||||
system.ruby.network.routers2.msg_count.Writeback_Control::2 1144
|
|
||||||
system.ruby.network.routers2.msg_count.Writeback_Control::3 1144
|
|
||||||
system.ruby.network.routers2.msg_count.Writeback_Control::5 924
|
|
||||||
system.ruby.network.routers2.msg_count.Unblock_Control::5 1160
|
|
||||||
system.ruby.network.routers2.msg_bytes.Request_Control::2 9280
|
|
||||||
system.ruby.network.routers2.msg_bytes.Response_Data::4 83520
|
|
||||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::5 15840
|
|
||||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9152
|
|
||||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9152
|
|
||||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7392
|
|
||||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9280
|
|
||||||
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.msg_count.Request_Control 3480
|
|
||||||
system.ruby.network.msg_count.Response_Data 3480
|
|
||||||
system.ruby.network.msg_count.Writeback_Data 660
|
|
||||||
system.ruby.network.msg_count.Writeback_Control 9636
|
|
||||||
system.ruby.network.msg_count.Unblock_Control 3479
|
|
||||||
system.ruby.network.msg_byte.Request_Control 27840
|
|
||||||
system.ruby.network.msg_byte.Response_Data 250560
|
|
||||||
system.ruby.network.msg_byte.Writeback_Data 47520
|
|
||||||
system.ruby.network.msg_byte.Writeback_Control 77088
|
|
||||||
system.ruby.network.msg_byte.Unblock_Control 27832
|
|
||||||
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
|
|
||||||
system.ruby.network.routers0.throttle0.link_utilization 6.206401
|
|
||||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1160
|
|
||||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1144
|
|
||||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 83520
|
|
||||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 9152
|
|
||||||
system.ruby.network.routers0.throttle1.link_utilization 3.411806
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 1160
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 220
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 1144
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 924
|
|
||||||
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 1160
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 9280
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 15840
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 9152
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 7392
|
|
||||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 9280
|
|
||||||
system.ruby.network.routers1.throttle0.link_utilization 3.411271
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 1160
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 220
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 1144
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 924
|
|
||||||
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 1159
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 9280
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 15840
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 9152
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 7392
|
|
||||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9272
|
|
||||||
system.ruby.network.routers1.throttle1.link_utilization 6.206401
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1160
|
|
||||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1144
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 83520
|
|
||||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 9152
|
|
||||||
system.ruby.network.routers2.throttle0.link_utilization 6.206401
|
|
||||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1160
|
|
||||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1144
|
|
||||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 83520
|
|
||||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 9152
|
|
||||||
system.ruby.network.routers2.throttle1.link_utilization 3.411806
|
|
||||||
system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 1160
|
|
||||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 220
|
|
||||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 1144
|
|
||||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 924
|
|
||||||
system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 1160
|
|
||||||
system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 9280
|
|
||||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 15840
|
|
||||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9152
|
|
||||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7392
|
|
||||||
system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9280
|
|
||||||
system.ruby.LD.latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.LD.latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.LD.latency_hist_seqr::samples 1185
|
|
||||||
system.ruby.LD.latency_hist_seqr::mean 23.222785
|
|
||||||
system.ruby.LD.latency_hist_seqr::gmean 5.170883
|
|
||||||
system.ruby.LD.latency_hist_seqr::stdev 33.395677
|
|
||||||
system.ruby.LD.latency_hist_seqr | 1100 92.83% 92.83% | 82 6.92% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 3 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.latency_hist_seqr::total 1185
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::bucket_size 2
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::max_bucket 19
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::samples 764
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::mean 2.374346
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::gmean 1.390347
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::stdev 3.445311
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr | 659 86.26% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 105 13.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.hit_latency_hist_seqr::total 764
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::samples 421
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::mean 61.057007
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::gmean 56.073786
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::stdev 29.948950
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr | 336 79.81% 79.81% | 82 19.48% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 3 0.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.miss_latency_hist_seqr::total 421
|
|
||||||
system.ruby.ST.latency_hist_seqr::bucket_size 16
|
|
||||||
system.ruby.ST.latency_hist_seqr::max_bucket 159
|
|
||||||
system.ruby.ST.latency_hist_seqr::samples 865
|
|
||||||
system.ruby.ST.latency_hist_seqr::mean 11.254335
|
|
||||||
system.ruby.ST.latency_hist_seqr::gmean 2.251088
|
|
||||||
system.ruby.ST.latency_hist_seqr::stdev 22.172254
|
|
||||||
system.ruby.ST.latency_hist_seqr | 707 81.73% 81.73% | 44 5.09% 86.82% | 0 0.00% 86.82% | 73 8.44% 95.26% | 36 4.16% 99.42% | 4 0.46% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.latency_hist_seqr::total 865
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::bucket_size 2
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::max_bucket 19
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::samples 707
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::mean 1.466761
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::gmean 1.118428
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::stdev 2.110935
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr | 674 95.33% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 33 4.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.hit_latency_hist_seqr::total 707
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::bucket_size 16
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::max_bucket 159
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::samples 158
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::mean 55.050633
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::gmean 51.490981
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::stdev 17.990372
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 73 46.20% 74.05% | 36 22.78% 96.84% | 4 2.53% 99.37% | 1 0.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.miss_latency_hist_seqr::total 158
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::samples 6413
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::mean 7.423359
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::gmean 1.501230
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::stdev 22.823134
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr | 6295 98.16% 98.16% | 108 1.68% 99.84% | 1 0.02% 99.86% | 1 0.02% 99.88% | 5 0.08% 99.95% | 2 0.03% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00%
|
|
||||||
system.ruby.IFETCH.latency_hist_seqr::total 6413
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5832
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.111454
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.027086
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::stdev 1.049908
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr | 5767 98.89% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 65 1.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.IFETCH.hit_latency_hist_seqr::total 5832
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::samples 581
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::mean 70.781411
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 67.778682
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 36.410761
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr | 463 79.69% 79.69% | 108 18.59% 98.28% | 1 0.17% 98.45% | 1 0.17% 98.62% | 5 0.86% 99.48% | 2 0.34% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
|
|
||||||
system.ruby.IFETCH.miss_latency_hist_seqr::total 581
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7100
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7100 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7100
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 2
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 19
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 203
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 11
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 11.000000
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 203 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 203
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1160
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 65.109483
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 60.947221
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.683425
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr | 916 78.97% 78.97% | 231 19.91% 98.88% | 1 0.09% 98.97% | 1 0.09% 99.05% | 5 0.43% 99.48% | 5 0.43% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 1 0.09% 100.00%
|
|
||||||
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1160
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 8
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 79
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::mean 75
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::gmean 75.000000
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 9
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 659
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 659
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 105
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 11
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 105
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 421
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 61.057007
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 56.073786
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 29.948950
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 336 79.81% 79.81% | 82 19.48% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 3 0.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 421
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 674
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 674 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 674
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 33
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 11
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 33 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 33
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 158
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 55.050633
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 51.490981
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 17.990372
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 73 46.20% 74.05% | 36 22.78% 96.84% | 4 2.53% 99.37% | 1 0.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 158
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5767
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5767
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 65
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 11
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 65 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
||||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 65
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 581
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 70.781411
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 67.778682
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.410761
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 463 79.69% 79.69% | 108 18.59% 98.28% | 1 0.17% 98.45% | 1 0.17% 98.62% | 5 0.86% 99.48% | 2 0.34% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
|
|
||||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 581
|
|
||||||
system.ruby.Directory_Controller.GETX 185 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.GETS 1021 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.PUT 1144 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Writeback_Exclusive_Clean 924 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Memory_Data 1160 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.NO.PUT 1144 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.E.GETS 1002 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.NO_B_W.Memory_Data 1160 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 924 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00%
|
|
||||||
system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Load 1193 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Ifetch 6424 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Store 892 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.L2_Replacement 1144 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.L1_to_L2 1355 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 138 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 65 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Complete_L2_to_L1 203 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Exclusive_Data 1160 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.Writeback_Ack 1144 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.All_acks_no_sharers 1160 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.I.Load 421 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.I.Ifetch 581 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.I.Store 158 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Load 305 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Ifetch 5767 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Store 60 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.L2_Replacement 924 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.L1_to_L2 1062 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 68 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1I 65 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM.Load 354 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM.Store 614 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM.L2_Replacement 220 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM.L1_to_L2 293 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 70 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MR.Load 62 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MR.Ifetch 65 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MR.Store 6 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MMR.Load 43 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MMR.Store 27 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IM.Exclusive_Data 158 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 1002 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 158 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.IS.Exclusive_Data 1002 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MI.Load 8 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MI.Ifetch 11 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MI.Store 27 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1144 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 133 0.00% 0.00%
|
|
||||||
system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 70 0.00% 0.00%
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
|
||||||
|
|
@ -40,12 +40,13 @@ add_option = optparser.add_option
|
||||||
add_option('-v', '--verbose', action='store_true', default=False,
|
add_option('-v', '--verbose', action='store_true', default=False,
|
||||||
help='echo commands before executing')
|
help='echo commands before executing')
|
||||||
add_option('--builds',
|
add_option('--builds',
|
||||||
default='ALPHA,ALPHA_MOESI_hammer,' \
|
default='ALPHA,' \
|
||||||
'ALPHA_MESI_Two_Level,' \
|
|
||||||
'ALPHA_MOESI_CMP_directory,' \
|
|
||||||
'ALPHA_MOESI_CMP_token,' \
|
|
||||||
'MIPS,' \
|
'MIPS,' \
|
||||||
'NULL,' \
|
'NULL,' \
|
||||||
|
'NULL_MOESI_hammer,' \
|
||||||
|
'NULL_MESI_Two_Level,' \
|
||||||
|
'NULL_MOESI_CMP_directory,' \
|
||||||
|
'NULL_MOESI_CMP_token,' \
|
||||||
'POWER,' \
|
'POWER,' \
|
||||||
'SPARC,' \
|
'SPARC,' \
|
||||||
'X86,X86_MESI_Two_Level,' \
|
'X86,X86_MESI_Two_Level,' \
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue