arm: enable EL2 support
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
This commit is contained in:
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4fbf40daab
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49538a7118
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@ -1,4 +1,4 @@
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# Copyright (c) 2012-2013, 2015 ARM Limited
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# Copyright (c) 2012-2013, 2015-2016 ARM Limited
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# All rights reserved.
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# All rights reserved.
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#
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#
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# The license below extends only to copyright in the software and shall
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# The license below extends only to copyright in the software and shall
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@ -117,8 +117,7 @@ class ArmISA(SimObject):
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"AArch64 Memory Model Feature Register 1")
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"AArch64 Memory Model Feature Register 1")
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# !GICv3 CP15 | AdvSIMD | FP | !EL3 | !EL2 | EL1 (AArch64) | EL0 (AArch64)
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# !GICv3 CP15 | AdvSIMD | FP | !EL3 | !EL2 | EL1 (AArch64) | EL0 (AArch64)
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# (no AArch32/64 interprocessing support for now)
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id_aa64pfr0_el1 = Param.UInt64(0x0000000000000022,
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id_aa64pfr0_el1 = Param.UInt64(0x0000000000000011,
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"AArch64 Processor Feature Register 0")
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"AArch64 Processor Feature Register 0")
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# Reserved for future expansion
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# Reserved for future expansion
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id_aa64pfr1_el1 = Param.UInt64(0x0000000000000000,
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id_aa64pfr1_el1 = Param.UInt64(0x0000000000000000,
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@ -338,11 +338,10 @@ ArmFault::getVector64(ThreadContext *tc)
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assert(ArmSystem::haveSecurity(tc));
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assert(ArmSystem::haveSecurity(tc));
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vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
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vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
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break;
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break;
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// @todo: uncomment this to enable Virtualization
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case EL2:
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// case EL2:
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assert(ArmSystem::haveVirtualization(tc));
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// assert(ArmSystem::haveVirtualization(tc));
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vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
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// vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
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break;
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// break;
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case EL1:
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case EL1:
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vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
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vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
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break;
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break;
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@ -596,12 +595,11 @@ ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
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elr_idx = MISCREG_ELR_EL1;
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elr_idx = MISCREG_ELR_EL1;
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spsr_idx = MISCREG_SPSR_EL1;
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spsr_idx = MISCREG_SPSR_EL1;
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break;
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break;
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// @todo: uncomment this to enable Virtualization
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case EL2:
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// case EL2:
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assert(ArmSystem::haveVirtualization(tc));
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// assert(ArmSystem::haveVirtualization());
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elr_idx = MISCREG_ELR_EL2;
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// elr_idx = MISCREG_ELR_EL2;
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spsr_idx = MISCREG_SPSR_EL2;
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// spsr_idx = MISCREG_SPSR_EL2;
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break;
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// break;
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case EL3:
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case EL3:
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assert(ArmSystem::haveSecurity(tc));
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assert(ArmSystem::haveSecurity(tc));
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elr_idx = MISCREG_ELR_EL3;
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elr_idx = MISCREG_ELR_EL3;
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@ -359,9 +359,8 @@ ISA::clear64(const ArmISAParams *p)
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if (haveSecurity) {
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if (haveSecurity) {
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miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870;
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miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870;
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miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
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miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
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// @todo: uncomment this to enable Virtualization
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} else if (haveVirtualization) {
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// } else if (haveVirtualization) {
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miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
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// miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
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} else {
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} else {
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miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870;
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miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870;
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// Always non-secure
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// Always non-secure
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@ -391,15 +390,13 @@ ISA::clear64(const ArmISAParams *p)
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// Enforce consistency with system-level settings...
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// Enforce consistency with system-level settings...
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// EL3
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// EL3
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// (no AArch32/64 interprocessing support for now)
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miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
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miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
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miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
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miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
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haveSecurity ? 0x1 : 0x0);
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haveSecurity ? 0x2 : 0x0);
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// EL2
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// EL2
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// (no AArch32/64 interprocessing support for now)
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miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
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miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
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miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
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miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
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haveVirtualization ? 0x1 : 0x0);
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haveVirtualization ? 0x2 : 0x0);
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// Large ASID support
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// Large ASID support
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miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
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miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
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miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
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miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2010, 2012-2015 ARM Limited
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* Copyright (c) 2010, 2012-2016 ARM Limited
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* All rights reserved
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* All rights reserved
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*
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*
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* The license below extends only to copyright in the software and shall
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* The license below extends only to copyright in the software and shall
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@ -261,9 +261,8 @@ namespace ArmISA
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switch (el) {
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switch (el) {
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case EL3:
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case EL3:
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return INTREG_SP3;
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return INTREG_SP3;
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// @todo: uncomment this to enable Virtualization
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case EL2:
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// case EL2:
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return INTREG_SP2;
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// return INTREG_SP2;
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case EL1:
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case EL1:
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return INTREG_SP1;
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return INTREG_SP1;
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case EL0:
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case EL0:
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2010-2013, 2015 ARM Limited
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* Copyright (c) 2010-2013, 2015-2016 ARM Limited
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* All rights reserved
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* All rights reserved
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*
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*
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* The license below extends only to copyright in the software and shall
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* The license below extends only to copyright in the software and shall
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@ -2118,9 +2118,8 @@ canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
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case EL1:
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case EL1:
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return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
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return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
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miscRegInfo[reg][MISCREG_PRI_NS_RD];
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miscRegInfo[reg][MISCREG_PRI_NS_RD];
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// @todo: uncomment this to enable Virtualization
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case EL2:
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// case EL2:
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return miscRegInfo[reg][MISCREG_HYP_RD];
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// return miscRegInfo[reg][MISCREG_HYP_RD];
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case EL3:
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case EL3:
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return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
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return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
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miscRegInfo[reg][MISCREG_MON_NS1_RD];
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miscRegInfo[reg][MISCREG_MON_NS1_RD];
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@ -2163,9 +2162,8 @@ canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
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case EL1:
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case EL1:
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return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
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return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
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miscRegInfo[reg][MISCREG_PRI_NS_WR];
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miscRegInfo[reg][MISCREG_PRI_NS_WR];
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// @todo: uncomment this to enable Virtualization
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case EL2:
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// case EL2:
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return miscRegInfo[reg][MISCREG_HYP_WR];
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// return miscRegInfo[reg][MISCREG_HYP_WR];
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case EL3:
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case EL3:
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return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
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return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
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miscRegInfo[reg][MISCREG_MON_NS1_WR];
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miscRegInfo[reg][MISCREG_MON_NS1_WR];
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2010, 2012-2013, 2015 ARM Limited
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* Copyright (c) 2010, 2012-2013, 2015-2016 ARM Limited
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* All rights reserved
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* All rights reserved
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*
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*
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* The license below extends only to copyright in the software and shall
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* The license below extends only to copyright in the software and shall
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@ -184,9 +184,8 @@ class ArmSystem : public System
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{
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{
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if (_haveSecurity)
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if (_haveSecurity)
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return EL3;
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return EL3;
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// @todo: uncomment this to enable Virtualization
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if (_haveVirtualization)
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// if (_haveVirtualization)
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return EL2;
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// return EL2;
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return EL1;
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return EL1;
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}
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}
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2010, 2012-2015 ARM Limited
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* Copyright (c) 2010, 2012-2016 ARM Limited
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* All rights reserved
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* All rights reserved
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*
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*
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* The license below extends only to copyright in the software and shall
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* The license below extends only to copyright in the software and shall
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@ -223,7 +223,7 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid,
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// ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672
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// ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672
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// aarch32/translation/translation/AArch32.TranslateAddress dictates
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// aarch32/translation/translation/AArch32.TranslateAddress dictates
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// even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64.
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// even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64.
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currState->aarch64 = opModeIs64(currOpMode(_tc)) ||
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currState->aarch64 = isStage2 || opModeIs64(currOpMode(_tc)) ||
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((currEL(_tc) == EL0) && ELIs64(_tc, EL1));
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((currEL(_tc) == EL0) && ELIs64(_tc, EL1));
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currState->el = currEL(_tc);
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currState->el = currEL(_tc);
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currState->transState = _trans;
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currState->transState = _trans;
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@ -255,12 +255,11 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid,
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currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
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currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
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currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1);
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currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1);
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break;
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break;
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// @todo: uncomment this to enable Virtualization
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case EL2:
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// case EL2:
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assert(_haveVirtualization);
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// assert(haveVirtualization);
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currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
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// currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
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currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2);
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// currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2);
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break;
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// break;
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case EL3:
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case EL3:
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assert(haveSecurity);
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assert(haveSecurity);
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currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3);
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currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3);
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2009-2014 ARM Limited
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* Copyright (c) 2009-2014, 2016 ARM Limited
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* All rights reserved.
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* All rights reserved.
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*
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*
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* The license below extends only to copyright in the software and shall
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* The license below extends only to copyright in the software and shall
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@ -235,14 +235,14 @@ ELIs64(ThreadContext *tc, ExceptionLevel el)
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return opModeIs64(currOpMode(tc));
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return opModeIs64(currOpMode(tc));
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case EL1:
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case EL1:
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{
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{
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// @todo: uncomment this to enable Virtualization
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if (ArmSystem::haveVirtualization(tc)) {
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// if (ArmSystem::haveVirtualization(tc)) {
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HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
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// HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
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return hcr.rw;
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// return hcr.rw;
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} else if (ArmSystem::haveSecurity(tc)) {
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// }
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SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
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assert(ArmSystem::haveSecurity(tc));
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return scr.rw;
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SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
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}
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return scr.rw;
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panic("must haveSecurity(tc)");
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}
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}
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case EL2:
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case EL2:
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{
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{
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@ -286,13 +286,12 @@ purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
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else if (!bits(addr, 55, 48) && tcr.tbi0)
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else if (!bits(addr, 55, 48) && tcr.tbi0)
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return bits(addr,55, 0);
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return bits(addr,55, 0);
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break;
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break;
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// @todo: uncomment this to enable Virtualization
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case EL2:
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// case EL2:
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assert(ArmSystem::haveVirtualization(tc));
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// assert(ArmSystem::haveVirtualization());
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tcr = tc->readMiscReg(MISCREG_TCR_EL2);
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// tcr = tc->readMiscReg(MISCREG_TCR_EL2);
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if (tcr.tbi)
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// if (tcr.tbi)
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return addr & mask(56);
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// return addr & mask(56);
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break;
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// break;
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case EL3:
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case EL3:
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assert(ArmSystem::haveSecurity(tc));
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assert(ArmSystem::haveSecurity(tc));
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if (tcr.tbi)
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if (tcr.tbi)
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@ -320,13 +319,12 @@ purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
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else if (!bits(addr, 55, 48) && tcr.tbi0)
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else if (!bits(addr, 55, 48) && tcr.tbi0)
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return bits(addr,55, 0);
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return bits(addr,55, 0);
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break;
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break;
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// @todo: uncomment this to enable Virtualization
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case EL2:
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// case EL2:
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assert(ArmSystem::haveVirtualization(tc));
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// assert(ArmSystem::haveVirtualization());
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tcr = tc->readMiscReg(MISCREG_TCR_EL2);
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// tcr = tc->readMiscReg(MISCREG_TCR_EL2);
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if (tcr.tbi)
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// if (tcr.tbi)
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return addr & mask(56);
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// return addr & mask(56);
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break;
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// break;
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case EL3:
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case EL3:
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assert(ArmSystem::haveSecurity(tc));
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assert(ArmSystem::haveSecurity(tc));
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tcr = tc->readMiscReg(MISCREG_TCR_EL3);
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tcr = tc->readMiscReg(MISCREG_TCR_EL3);
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