49538a7118
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
284 lines
8.5 KiB
C++
284 lines
8.5 KiB
C++
/*
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* Copyright (c) 2010, 2012-2013, 2015-2016 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __ARCH_ARM_SYSTEM_HH__
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#define __ARCH_ARM_SYSTEM_HH__
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#include <memory>
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#include <string>
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#include <vector>
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#include "kern/linux/events.hh"
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#include "params/ArmSystem.hh"
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#include "params/GenericArmSystem.hh"
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#include "sim/sim_object.hh"
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#include "sim/system.hh"
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class GenericTimer;
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class ThreadContext;
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class ArmSystem : public System
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{
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protected:
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/**
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* PC based event to skip the dprink() call and emulate its
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* functionality
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*/
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Linux::DebugPrintkEvent *debugPrintkEvent;
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/** Bootloaders */
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std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
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/**
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* Pointer to the bootloader object
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*/
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ObjectFile *bootldr;
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/**
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* True if this system implements the Security Extensions
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*/
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const bool _haveSecurity;
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/**
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* True if this system implements the Large Physical Address Extension
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*/
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const bool _haveLPAE;
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/**
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* True if this system implements the virtualization Extensions
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*/
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const bool _haveVirtualization;
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/**
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* Pointer to the Generic Timer wrapper.
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*/
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GenericTimer *_genericTimer;
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/**
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* True if the register width of the highest implemented exception level is
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* 64 bits (ARMv8)
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*/
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bool _highestELIs64;
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/**
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* Reset address if the highest implemented exception level is 64 bits
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* (ARMv8)
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*/
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const Addr _resetAddr64;
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/**
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* Supported physical address range in bits if the highest implemented
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* exception level is 64 bits (ARMv8)
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*/
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const uint8_t _physAddrRange64;
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/**
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* True if ASID is 16 bits in AArch64 (ARMv8)
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*/
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const bool _haveLargeAsid64;
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protected:
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/**
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* Get a boot loader that matches the kernel.
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*
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* @param obj Kernel binary
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* @return Pointer to boot loader ObjectFile or nullptr if there
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* is no matching boot loader.
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*/
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ObjectFile *getBootLoader(ObjectFile *const obj);
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public:
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typedef ArmSystemParams Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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ArmSystem(Params *p);
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~ArmSystem();
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/**
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* Initialise the system
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*/
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virtual void initState();
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virtual Addr fixFuncEventAddr(Addr addr)
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{
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// Remove the low bit that thumb symbols have set
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// but that aren't actually odd aligned
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if (addr & 0x1)
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return addr & ~1;
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return addr;
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}
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/** true if this a multiprocessor system */
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bool multiProc;
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/** Returns true if this system implements the Security Extensions */
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bool haveSecurity() const { return _haveSecurity; }
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/** Returns true if this system implements the Large Physical Address
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* Extension */
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bool haveLPAE() const { return _haveLPAE; }
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/** Returns true if this system implements the virtualization
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* Extensions
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*/
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bool haveVirtualization() const { return _haveVirtualization; }
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/** Sets the pointer to the Generic Timer. */
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void setGenericTimer(GenericTimer *generic_timer)
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{
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_genericTimer = generic_timer;
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}
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/** Get a pointer to the system's generic timer model */
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GenericTimer *getGenericTimer() const { return _genericTimer; }
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/** Returns true if the register width of the highest implemented exception
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* level is 64 bits (ARMv8) */
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bool highestELIs64() const { return _highestELIs64; }
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/** Returns the highest implemented exception level */
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ExceptionLevel highestEL() const
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{
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if (_haveSecurity)
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return EL3;
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if (_haveVirtualization)
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return EL2;
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return EL1;
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}
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/** Returns the reset address if the highest implemented exception level is
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* 64 bits (ARMv8) */
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Addr resetAddr64() const { return _resetAddr64; }
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/** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
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bool haveLargeAsid64() const { return _haveLargeAsid64; }
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/** Returns the supported physical address range in bits if the highest
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* implemented exception level is 64 bits (ARMv8) */
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uint8_t physAddrRange64() const { return _physAddrRange64; }
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/** Returns the supported physical address range in bits */
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uint8_t physAddrRange() const
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{
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if (_highestELIs64)
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return _physAddrRange64;
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if (_haveLPAE)
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return 40;
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return 32;
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}
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/** Returns the physical address mask */
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Addr physAddrMask() const
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{
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return mask(physAddrRange());
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}
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/** Returns true if the system of a specific thread context implements the
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* Security Extensions
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*/
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static bool haveSecurity(ThreadContext *tc);
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/** Returns true if the system of a specific thread context implements the
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* virtualization Extensions
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*/
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static bool haveVirtualization(ThreadContext *tc);
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/** Returns true if the system of a specific thread context implements the
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* Large Physical Address Extension
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*/
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static bool haveLPAE(ThreadContext *tc);
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/** Returns true if the register width of the highest implemented exception
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* level for the system of a specific thread context is 64 bits (ARMv8)
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*/
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static bool highestELIs64(ThreadContext *tc);
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/** Returns the highest implemented exception level for the system of a
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* specific thread context
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*/
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static ExceptionLevel highestEL(ThreadContext *tc);
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/** Returns the reset address if the highest implemented exception level for
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* the system of a specific thread context is 64 bits (ARMv8)
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*/
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static Addr resetAddr64(ThreadContext *tc);
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/** Returns the supported physical address range in bits for the system of a
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* specific thread context
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*/
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static uint8_t physAddrRange(ThreadContext *tc);
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/** Returns the physical address mask for the system of a specific thread
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* context
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*/
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static Addr physAddrMask(ThreadContext *tc);
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/** Returns true if ASID is 16 bits for the system of a specific thread
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* context while in AArch64 (ARMv8) */
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static bool haveLargeAsid64(ThreadContext *tc);
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};
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class GenericArmSystem : public ArmSystem
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{
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public:
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typedef GenericArmSystemParams Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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GenericArmSystem(Params *p) : ArmSystem(p) {};
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virtual ~GenericArmSystem() {};
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/**
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* Initialise the system
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*/
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virtual void initState();
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};
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#endif
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