changed sendresult -> bool,tick,void as appropriate
first crack at io devices code made CpuRequest that derives from Request dev/io_device.cc: dev/io_device.hh: first crack at the classes for Pio and Dma devices dev/platform.hh: We are going to a system pointer to get info about the memory system mem/bus.hh: changed sendresult -> bool,tick,void as appropriate mem/port.hh: changed sendresult -> bool,tick,void as appropriate; removed the sendTiming(pkt,t) call since it is not really implementable in a generic fashion mem/request.hh: pulled items from Request into CpuRequest --HG-- extra : convert_revision : 6213cf2b66417fa023b80884d9e623e78f5aa891
This commit is contained in:
parent
a1033448ea
commit
4875b33467
6 changed files with 283 additions and 66 deletions
110
dev/io_device.cc
110
dev/io_device.cc
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@ -27,25 +27,118 @@
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*/
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*/
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#include "dev/io_device.hh"
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#include "dev/io_device.hh"
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#include "mem/bus/base_interface.hh"
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#include "mem/bus/dma_interface.hh"
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#include "sim/builder.hh"
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#include "sim/builder.hh"
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void
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PioPort::SendEvent::process()
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{
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if (port->sendTiming(packet) == Success)
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return;
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port->transmitList.push_back(&packet);
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}
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PioDevice::PioDevice(const std::string &name, Platform *p)
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PioDevice::PioDevice(const std::string &name, Platform *p)
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: FunctionalMemory(name), platform(p), pioInterface(NULL), pioLatency(0)
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: SimObject(name), platform(p)
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{}
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{
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pioPort = new PioPort(this);
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}
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bool
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PioDevice::recvTiming(Packet &pkt)
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{
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device->recvAtomic(pkt);
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sendTiming(pkt, pkt.responseTime-pkt.requestTime);
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return Success;
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}
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PioDevice::~PioDevice()
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PioDevice::~PioDevice()
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{
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{
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if (pioInterface)
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if (pioPort)
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delete pioInterface;
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delete pioInterface;
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}
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}
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DEFINE_SIM_OBJECT_CLASS_NAME("PioDevice", PioDevice)
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void
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DmaPort::sendDma(Packet &pkt)
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{
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device->platform->system->memoryMode()
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{
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case MemAtomic:
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}
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}
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DmaDevice::DmaDevice(const std::string &name, Platform *p)
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DmaDevice::DmaDevice(const std::string &name, Platform *p)
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: PioDevice(name, p), dmaInterface(NULL)
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: PioDevice(name, p)
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{}
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{
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dmaPort = new dmaPort(this);
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}
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void
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DmaPort::dmaAction(Memory::Command cmd, DmaPort port, Addr addr, int size,
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Event *event, uint8_t *data = NULL)
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{
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assert(event);
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int prevSize = 0;
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Packet basePkt;
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Request baseReq;
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basePkt.flags = 0;
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basePkt.coherence = NULL;
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basePkt.senderState = NULL;
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basePkt.src = 0;
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basePkt.dest = 0;
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basePkt.cmd = cmd;
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basePkt.result = Unknown;
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basePkt.request = NULL;
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baseReq.nicReq = true;
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baseReq.time = curTick;
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completionEvent = event;
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for (ChunkGenerator gen(addr, size, sendBlockSizeQuery()); !gen.done(); gen.next()) {
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Packet *pkt = new Packet(basePkt);
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Request *req = new Request(baseReq);
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pkt->addr = gen.addr();
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pkt->size = gen.size();
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pkt->req = req;
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pkt->req->paddr = pkt->addr;
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pkt->req->size = pkt->size;
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// Increment the data pointer on a write
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pkt->data = data ? data + prevSize : NULL ;
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prevSize = pkt->size;
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sendDma(*pkt);
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}
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}
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void
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DmaPort::sendDma(Packet &pkt)
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{
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// some kind of selction between access methods
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// more work is going to have to be done to make
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// switching actually work
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MemState state = device->platform->system->memState;
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if (state == Timing) {
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if (sendTiming(pkt) == Failure)
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transmitList.push_back(&packet);
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} else if (state == Atomic) {
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sendAtomic(pkt);
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completionEvent->schedule(pkt.responseTime - pkt.requestTime);
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completionEvent == NULL;
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} else if (state == Functional) {
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sendFunctional(pkt);
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// Is this correct???
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completionEvent->schedule(pkt.responseTime - pkt.requestTime);
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completionEvent == NULL;
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} else
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panic("Unknown memory command state.");
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}
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DmaDevice::~DmaDevice()
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DmaDevice::~DmaDevice()
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{
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{
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@ -53,5 +146,4 @@ DmaDevice::~DmaDevice()
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delete dmaInterface;
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delete dmaInterface;
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}
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}
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DEFINE_SIM_OBJECT_CLASS_NAME("DmaDevice", DmaDevice)
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150
dev/io_device.hh
150
dev/io_device.hh
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@ -29,34 +29,168 @@
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#ifndef __DEV_IO_DEVICE_HH__
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#ifndef __DEV_IO_DEVICE_HH__
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#define __DEV_IO_DEVICE_HH__
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#define __DEV_IO_DEVICE_HH__
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#include "mem/functional/functional.hh"
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#include "base/chunk_generator.hh"
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#include "mem/port.hh"
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#include "sim/eventq.hh"
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class BaseInterface;
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class Bus;
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class Bus;
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class HierParams;
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class Platform;
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class Platform;
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template <class BusType> class DMAInterface;
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class PioDevice;
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class PioDevice : public FunctionalMemory
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class PioPort : public Port
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{
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{
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protected:
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protected:
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PioDevice *device;
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virtual bool recvTiming(Packet &pkt);
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virtual Tick recvAtomic(Packet &pkt)
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{ return device->recvAtomic(pkt) };
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virtual void recvFunctional(Packet &pkt)
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{ device->recvAtomic(pkt) };
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virtual void recvAddressRangeQuery(std::list<Range<Addr> > &range_list,
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bool &owner)
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{ device->addressRanges(range_list, owner); }
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void sendTiming(Packet &pkt, Tick time)
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{ new SendEvent(this, pkt, time); }
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class SendEvent : public Event
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{
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PioPort *port;
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Packet packet;
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SendEvent(PioPort *p, Packet &pkt, Tick t)
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: Event(&mainEventQueue), packet(pkt)
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{ schedule(curTick + t); }
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virtual void process();
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virtual const char *description()
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{ return "Future scheduled sendTiming event"; }
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friend class PioPort;
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}
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public:
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PioPort(PioDevice *dev)
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: device(dev)
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{ }
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};
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class DmaPort : public Port
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{
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protected:
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PioDevice *device;
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std::list<Packet*> transmitList;
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virtual bool recvTiming(Packet &pkt)
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{ completionEvent->schedule(curTick+1); completionEvent = NULL; }
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virtual Tick recvAtomic(Packet &pkt)
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{ panic("dma port shouldn't be used for pio access."); }
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virtual void recvFunctional(Packet &pkt)
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{ panic("dma port shouldn't be used for pio access."); }
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virtual void recvStatusChange(Status status)
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{ ; }
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virtual Packet *recvRetry()
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{ return transmitList.pop_front(); }
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virtual void recvAddressRangeQuery(std::list<Range<Addr> > &range_list,
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bool &owner)
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{ range_list.clear(); owner = true; }
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void dmaAction(Memory::Command cmd, DmaPort port, Addr addr, int size,
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Event *event, uint8_t *data = NULL);
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void sendDma(Packet &pkt);
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virtual Packet *recvRetry()
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{ return transmitList.pop_front(); }
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class SendEvent : public Event
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{
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PioPort *port;
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Packet packet;
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SendEvent(PioPort *p, Packet &pkt, Tick t)
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: Event(&mainEventQueue), packet(pkt)
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{ schedule(curTick + t); }
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virtual void process();
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virtual const char *description()
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{ return "Future scheduled sendTiming event"; }
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friend class PioPort;
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}
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public:
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DmaPort(DmaDevice *dev)
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: device(dev)
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{ }
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};
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class PioDevice : public SimObject
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{
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protected:
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Platform *platform;
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Platform *platform;
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BaseInterface *pioInterface;
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Tick pioLatency;
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PioPort *pioPort;
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virtual void addressRanges(std::list<Range<Addr> > &range_list,
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bool &owner) = 0;
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virtual read(Packet &pkt) = 0;
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virtual write(Packet &pkt) = 0;
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Tick recvAtomic(Packet &pkt)
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{ return pkt->cmd == Read ? this->read(pkt) : this->write(pkt); }
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public:
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public:
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PioDevice(const std::string &name, Platform *p);
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PioDevice(const std::string &name, Platform *p);
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virtual ~PioDevice();
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virtual ~PioDevice();
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virtual Port *getPort(std::string if_name)
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{
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if (if_name == "pio")
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return pioPort;
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else
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return NULL;
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}
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};
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};
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class DmaDevice : public PioDevice
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class DmaDevice : public PioDevice
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{
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{
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protected:
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protected:
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DMAInterface<Bus> *dmaInterface;
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DmaPort *dmaPort;
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public:
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public:
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DmaDevice(const std::string &name, Platform *p);
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DmaDevice(const std::string &name, Platform *p);
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virtual ~DmaDevice();
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virtual ~DmaDevice();
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virtual Port *getPort(std::string if_name)
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{
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if (if_name == "pio")
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return pioPort;
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else if (if_name = "dma")
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return dmaPort;
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else
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return NULL;
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|
}
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};
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};
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#endif // __DEV_IO_DEVICE_HH__
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#endif // __DEV_IO_DEVICE_HH__
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|
@ -41,6 +41,7 @@ class PciConfigAll;
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class IntrControl;
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class IntrControl;
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class SimConsole;
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class SimConsole;
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class Uart;
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class Uart;
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class System;
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class Platform : public SimObject
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class Platform : public SimObject
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{
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{
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@ -54,6 +55,9 @@ class Platform : public SimObject
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/** Pointer to the UART, set by the uart */
|
/** Pointer to the UART, set by the uart */
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Uart *uart;
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Uart *uart;
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/** Pointer to the system for info about the memory system. */
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System *system;
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|
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public:
|
public:
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Platform(const std::string &name, IntrControl *intctrl, PciConfigAll *pci);
|
Platform(const std::string &name, IntrControl *intctrl, PciConfigAll *pci);
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virtual ~Platform();
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virtual ~Platform();
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|
12
mem/bus.hh
12
mem/bus.hh
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@ -45,15 +45,15 @@ class Bus : public MemObject
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{
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{
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/** Function called by the port when the bus is recieving a Timing
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/** Function called by the port when the bus is recieving a Timing
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transaction.*/
|
transaction.*/
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SendResult recvTiming(Packet &pkt, int id);
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bool recvTiming(Packet &pkt, int id);
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|
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/** Function called by the port when the bus is recieving a Atomic
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/** Function called by the port when the bus is recieving a Atomic
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transaction.*/
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transaction.*/
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SendResult recvAtomic(Packet &pkt, int id);
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Tick recvAtomic(Packet &pkt, int id);
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|
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/** Function called by the port when the bus is recieving a Functional
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/** Function called by the port when the bus is recieving a Functional
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transaction.*/
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transaction.*/
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SendResult recvFunctional(Packet &pkt, int id);
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void recvFunctional(Packet &pkt, int id);
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/** Function called by the port when the bus is recieving a status change.*/
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/** Function called by the port when the bus is recieving a status change.*/
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void recvStatusChange(Port::Status status, int id);
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void recvStatusChange(Port::Status status, int id);
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@ -79,17 +79,17 @@ class Bus : public MemObject
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|
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/** When reciving a timing request from the peer port (at id),
|
/** When reciving a timing request from the peer port (at id),
|
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pass it to the bus. */
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pass it to the bus. */
|
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virtual SendResult recvTiming(Packet &pkt)
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virtual bool recvTiming(Packet &pkt)
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{ return bus->recvTiming(pkt, id); }
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{ return bus->recvTiming(pkt, id); }
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|
|
||||||
/** When reciving a Atomic requestfrom the peer port (at id),
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/** When reciving a Atomic requestfrom the peer port (at id),
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pass it to the bus. */
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pass it to the bus. */
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virtual SendResult recvAtomic(Packet &pkt)
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virtual Tick recvAtomic(Packet &pkt)
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{ return bus->recvAtomic(pkt, id); }
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{ return bus->recvAtomic(pkt, id); }
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|
|
||||||
/** When reciving a Functional requestfrom the peer port (at id),
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/** When reciving a Functional requestfrom the peer port (at id),
|
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pass it to the bus. */
|
pass it to the bus. */
|
||||||
virtual SendResult recvFunctional(Packet &pkt)
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virtual void recvFunctional(Packet &pkt)
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{ return bus->recvFunctional(pkt, id); }
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{ return bus->recvFunctional(pkt, id); }
|
||||||
|
|
||||||
/** When reciving a status changefrom the peer port (at id),
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/** When reciving a status changefrom the peer port (at id),
|
||||||
|
|
32
mem/port.hh
32
mem/port.hh
|
@ -87,25 +87,13 @@ class Port
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protected:
|
protected:
|
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|
|
||||||
/** Called to recive a timing call from the peer port. */
|
/** Called to recive a timing call from the peer port. */
|
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virtual SendResult recvTiming(Packet &pkt) = 0;
|
virtual bool recvTiming(Packet &pkt) = 0;
|
||||||
|
|
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/** Virtual function that can be used to handle scheduling an event
|
|
||||||
to send the recvTiming at a given time. This is for direct
|
|
||||||
connection without a interconnect. The bus will override
|
|
||||||
this in it's port class because the bus does the timing.
|
|
||||||
This is used to insert timing when an interconnect doesn't
|
|
||||||
have it's own event queue.
|
|
||||||
*/
|
|
||||||
virtual SendResult recvTiming(Packet &pkt, Tick t)
|
|
||||||
{
|
|
||||||
// schedule event to call recvTiming(pkt) @ tick t
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Called to recive a atomic call from the peer port. */
|
/** Called to recive a atomic call from the peer port. */
|
||||||
virtual SendResult recvAtomic(Packet &pkt) = 0;
|
virtual Tick recvAtomic(Packet &pkt) = 0;
|
||||||
|
|
||||||
/** Called to recive a functional call from the peer port. */
|
/** Called to recive a functional call from the peer port. */
|
||||||
virtual SendResult recvFunctional(Packet &pkt) = 0;
|
virtual void recvFunctional(Packet &pkt) = 0;
|
||||||
|
|
||||||
/** Called to recieve a status change from the peer port. */
|
/** Called to recieve a status change from the peer port. */
|
||||||
virtual void recvStatusChange(Status status) = 0;
|
virtual void recvStatusChange(Status status) = 0;
|
||||||
|
@ -146,21 +134,13 @@ class Port
|
||||||
case a cache has a higher priority request come in while waiting for
|
case a cache has a higher priority request come in while waiting for
|
||||||
the bus to arbitrate.
|
the bus to arbitrate.
|
||||||
*/
|
*/
|
||||||
SendResult sendTiming(Packet &pkt) { return peer->recvTiming(pkt); }
|
bool sendTiming(Packet &pkt) { return peer->recvTiming(pkt); }
|
||||||
|
|
||||||
/** This function is identical to the sendTiming function, accept it
|
|
||||||
provides a time when the recvTiming should be called. The
|
|
||||||
peer->recvTimimng will schedule the event, if it's device handles the
|
|
||||||
timing (bus) it will be overloaded by the bus type port to handle it
|
|
||||||
properly.
|
|
||||||
*/
|
|
||||||
SendResult sendTiming(Packet &pkt, Tick t) { return peer->recvTiming(pkt, t); }
|
|
||||||
|
|
||||||
/** Function called by the associated device to send an atomic access,
|
/** Function called by the associated device to send an atomic access,
|
||||||
an access in which the data is moved and the state is updated in one
|
an access in which the data is moved and the state is updated in one
|
||||||
cycle, without interleaving with other memory accesses.
|
cycle, without interleaving with other memory accesses.
|
||||||
*/
|
*/
|
||||||
SendResult sendAtomic(Packet &pkt)
|
Tick sendAtomic(Packet &pkt)
|
||||||
{ return peer->recvAtomic(pkt); }
|
{ return peer->recvAtomic(pkt); }
|
||||||
|
|
||||||
/** Function called by the associated device to send a functional access,
|
/** Function called by the associated device to send a functional access,
|
||||||
|
@ -168,7 +148,7 @@ class Port
|
||||||
memory system, without affecting the current state of any block
|
memory system, without affecting the current state of any block
|
||||||
or moving the block.
|
or moving the block.
|
||||||
*/
|
*/
|
||||||
SendResult sendFunctional(Packet &pkt)
|
void sendFunctional(Packet &pkt)
|
||||||
{ return peer->recvFunctional(pkt); }
|
{ return peer->recvFunctional(pkt); }
|
||||||
|
|
||||||
/** Called by the associated device to send a status change to the device
|
/** Called by the associated device to send a status change to the device
|
||||||
|
|
|
@ -37,34 +37,41 @@
|
||||||
class Request
|
class Request
|
||||||
{
|
{
|
||||||
|
|
||||||
/** The virtual address of the request. */
|
|
||||||
Addr vaddr;
|
|
||||||
/** The physical address of the request. */
|
/** The physical address of the request. */
|
||||||
Addr paddr;
|
Addr paddr;
|
||||||
|
|
||||||
/** whether this req came from the CPU or not */
|
/** whether this req came from the CPU or not **DO we need this??***/
|
||||||
bool nic_req;
|
bool nicReq;
|
||||||
|
|
||||||
/** The address space ID. */
|
|
||||||
int asid;
|
|
||||||
/** The related execution context. */
|
|
||||||
ExecContext *xc;
|
|
||||||
|
|
||||||
/** The size of the request. */
|
/** The size of the request. */
|
||||||
int size;
|
int size;
|
||||||
|
|
||||||
/** The return value of store conditional. */
|
|
||||||
uint64_t result;
|
|
||||||
|
|
||||||
/** The cpu number for statistics. */
|
|
||||||
int cpu_num;
|
|
||||||
/** The requesting thread id. */
|
|
||||||
int thread_num;
|
|
||||||
/** The time this request was started. Used to calculate latencies. */
|
/** The time this request was started. Used to calculate latencies. */
|
||||||
Tick time;
|
Tick time;
|
||||||
|
|
||||||
|
/** Destination address if this is a block copy. */
|
||||||
|
Addr copyDest;
|
||||||
|
};
|
||||||
|
|
||||||
|
class CpuRequest : public Request
|
||||||
|
{
|
||||||
|
/** The virtual address of the request. */
|
||||||
|
Addr vaddr;
|
||||||
|
|
||||||
|
/** The address space ID. */
|
||||||
|
int asid;
|
||||||
|
|
||||||
|
/** The return value of store conditional. */
|
||||||
|
uint64_t scResult;
|
||||||
|
|
||||||
|
/** The cpu number for statistics. */
|
||||||
|
int cpuNum;
|
||||||
|
|
||||||
|
/** The requesting thread id. */
|
||||||
|
int threadNum;
|
||||||
|
|
||||||
/** program counter of initiating access; for tracing/debugging */
|
/** program counter of initiating access; for tracing/debugging */
|
||||||
Addr pc;
|
Addr pc;
|
||||||
}
|
};
|
||||||
|
|
||||||
#endif // __MEM_REQUEST_HH__
|
#endif // __MEM_REQUEST_HH__
|
||||||
|
|
Loading…
Reference in a new issue