Support for recent port changes.
src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/python/m5/objects/OzoneCPU.py: Support Ron's recent port changes. src/cpu/ozone/lw_back_end_impl.hh: Support Ron's recent port changes. Also support handling faults in SE. --HG-- extra : convert_revision : aa1ba5111b70199c052da3e13bae605525a69891
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9 changed files with 38 additions and 33 deletions
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@ -372,6 +372,8 @@ class OzoneCPU : public BaseCPU
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PhysicalMemory *physmem;
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#endif
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virtual Port *getPort(const std::string &name, int idx);
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MemObject *mem;
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FrontEnd *frontEnd;
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@ -418,6 +418,18 @@ OzoneCPU<Impl>::init()
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thread.inSyscall = false;
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}
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template <class Impl>
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Port *
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OzoneCPU<Impl>::getPort(const std::string &if_name, int idx)
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{
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if (if_name == "dcache_port")
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return backEnd->getDcachePort();
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else if (if_name == "icache_port")
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return frontEnd->getIcachePort();
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else
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panic("No Such Port\n");
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::serialize(std::ostream &os)
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@ -119,6 +119,8 @@ class FrontEnd
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void regStats();
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Port *getIcachePort() { return &icachePort; }
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void tick();
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Fault fetchCacheLine();
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void processInst(DynInstPtr &inst);
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@ -36,6 +36,7 @@
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#include "cpu/thread_context.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/ozone/front_end.hh"
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "mem/request.hh"
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@ -138,10 +139,6 @@ FrontEnd<Impl>::setCPU(CPUType *cpu_ptr)
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icachePort.setName(this->name() + "-iport");
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Port *mem_dport = mem->getPort("");
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icachePort.setPeer(mem_dport);
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mem_dport->setPeer(&icachePort);
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#if USE_CHECKER
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if (cpu->checker) {
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cpu->checker->setIcachePort(&icachePort);
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@ -114,6 +114,8 @@ class LWBackEnd
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void setCommBuffer(TimeBuffer<CommStruct> *_comm);
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Port *getDcachePort() { return LSQ.getDcachePort(); }
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void tick();
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void squash();
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void generateTCEvent() { tcSquash = true; }
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@ -142,7 +142,7 @@ LWBackEnd<Impl>::replayMemInst(DynInstPtr &inst)
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template <class Impl>
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LWBackEnd<Impl>::LWBackEnd(Params *params)
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: d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(5, 5),
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trapSquash(false), tcSquash(false), LSQ(params),
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trapSquash(false), tcSquash(false),
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width(params->backEndWidth), exactFullStall(true)
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{
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numROBEntries = params->numROBEntries;
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@ -557,6 +557,7 @@ LWBackEnd<Impl>::checkInterrupts()
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}
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}
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}
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#endif
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template <class Impl>
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void
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@ -580,7 +581,6 @@ LWBackEnd<Impl>::handleFault(Fault &fault, Tick latency)
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// Generate trap squash event.
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generateTrapEvent(latency);
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}
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#endif
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template <class Impl>
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void
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@ -602,6 +602,7 @@ LWBackEnd<Impl>::tick()
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#if FULL_SYSTEM
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checkInterrupts();
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#endif
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if (trapSquash) {
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assert(!tcSquash);
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@ -609,7 +610,6 @@ LWBackEnd<Impl>::tick()
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} else if (tcSquash) {
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squashFromTC();
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}
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#endif
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if (dispatchStatus != Blocked) {
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dispatchInsts();
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@ -1137,13 +1137,9 @@ LWBackEnd<Impl>::commitInst(int inst_num)
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thread->setInst(
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static_cast<TheISA::MachInst>(inst->staticInst->machInst));
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#if FULL_SYSTEM
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handleFault(inst_fault);
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return false;
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#else // !FULL_SYSTEM
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panic("fault (%d) detected @ PC %08p", inst_fault,
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inst->PC);
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#endif // FULL_SYSTEM
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}
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int freed_regs = 0;
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@ -91,8 +91,7 @@ class OzoneLWLSQ {
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void setBE(BackEnd *be_ptr)
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{ be = be_ptr; }
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/** Sets the page table pointer. */
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// void setPageTable(PageTable *pt_ptr);
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Port *getDcachePort() { return &dcachePort; }
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/** Ticks the LSQ unit, which in this case only resets the number of
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* used cache ports.
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@ -241,13 +240,11 @@ class OzoneLWLSQ {
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class DcachePort : public Port
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{
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protected:
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OzoneCPU *cpu;
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OzoneLWLSQ *lsq;
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public:
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DcachePort(OzoneCPU *_cpu, OzoneLWLSQ *_lsq)
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: Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq)
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DcachePort(OzoneLWLSQ *_lsq)
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: lsq(_lsq)
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{ }
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protected:
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@ -266,11 +263,8 @@ class OzoneLWLSQ {
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virtual void recvRetry();
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};
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/** Pointer to the D-cache. */
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DcachePort *dcachePort;
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/** Pointer to the page table. */
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// PageTable *pTable;
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/** D-cache port. */
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DcachePort dcachePort;
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public:
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struct SQEntry {
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@ -639,7 +633,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
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data_pkt->senderState = state;
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// if we have a cache, do cache access too
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if (!dcachePort->sendTiming(data_pkt)) {
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if (!dcachePort.sendTiming(data_pkt)) {
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// There's an older load that's already going to squash.
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if (isLoadBlocked && blockedLoadSeqNum < inst->seqNum)
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return NoFault;
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@ -131,8 +131,9 @@ OzoneLWLSQ<Impl>::completeDataAccess(PacketPtr pkt)
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template <class Impl>
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OzoneLWLSQ<Impl>::OzoneLWLSQ()
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: switchedOut(false), loads(0), stores(0), storesToWB(0), stalled(false),
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isStoreBlocked(false), isLoadBlocked(false), loadBlockedHandled(false)
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: switchedOut(false), dcachePort(this), loads(0), stores(0),
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storesToWB(0), stalled(false), isStoreBlocked(false),
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isLoadBlocked(false), loadBlockedHandled(false)
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{
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}
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@ -175,15 +176,11 @@ void
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OzoneLWLSQ<Impl>::setCPU(OzoneCPU *cpu_ptr)
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{
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cpu = cpu_ptr;
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dcachePort = new DcachePort(cpu, this);
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Port *mem_dport = mem->getPort("");
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dcachePort->setPeer(mem_dport);
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mem_dport->setPeer(dcachePort);
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dcachePort.setName(this->name() + "-dport");
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#if USE_CHECKER
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if (cpu->checker) {
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cpu->checker->setDcachePort(dcachePort);
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cpu->checker->setDcachePort(&dcachePort);
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}
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#endif
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}
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@ -614,7 +611,7 @@ OzoneLWLSQ<Impl>::writebackStores()
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state->noWB = true;
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}
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if (!dcachePort->sendTiming(data_pkt)) {
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if (!dcachePort.sendTiming(data_pkt)) {
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// Need to handle becoming blocked on a store.
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isStoreBlocked = true;
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assert(retryPkt == NULL);
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@ -9,6 +9,9 @@ class DerivOzoneCPU(BaseCPU):
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checker = Param.BaseCPU("Checker CPU")
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icache_port = Port("Instruction Port")
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dcache_port = Port("Data Port")
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width = Param.Unsigned("Width")
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frontEndWidth = Param.Unsigned("Front end width")
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backEndWidth = Param.Unsigned("Back end width")
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