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O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).

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The store queue doesn't need to be ISA specific and architectures can
frequently store more than an int registers worth of data. A 128 bits seems
more common, but even 256 bits may be appropriate. Pretty much anything less
than a cache line size is buildable.
This commit is contained in:
Ali Saidi 2010-12-07 16:19:57 -08:00
parent 1cfe2c8820
commit 42ba158479
1 changed files with 1 additions and 3 deletions
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4
src/cpu/o3/lsq_unit.hh
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@ -63,8 +63,6 @@ class DerivO3CPUParams;
*/ */
template <class Impl> template <class Impl>
class LSQUnit { class LSQUnit {
protected:
typedef TheISA::IntReg IntReg;
public: public:
typedef typename Impl::O3CPU O3CPU; typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::DynInstPtr DynInstPtr;
@ -338,7 +336,7 @@ class LSQUnit {
/** The size of the store. */ /** The size of the store. */
int size; int size;
/** The store data. */ /** The store data. */
char data[sizeof(IntReg)]; char data[16];
/** Whether or not the store is split into two requests. */ /** Whether or not the store is split into two requests. */
bool isSplit; bool isSplit;
/** Whether or not the store can writeback. */ /** Whether or not the store can writeback. */