From 42ba158479c3feed12335958684200de8b6d2ece Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Tue, 7 Dec 2010 16:19:57 -0800
Subject: [PATCH] O3: Allow a store entry to store up to 16 bytes (instead of
 TheISA::IntReg).

The store queue doesn't need to be ISA specific and architectures can
frequently store more than an int registers worth of data. A 128 bits seems
more common, but even 256 bits may be appropriate. Pretty much anything less
than a cache line size is buildable.
---
 src/cpu/o3/lsq_unit.hh | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 372e76b71..e9e3fea96 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -63,8 +63,6 @@ class DerivO3CPUParams;
  */
 template <class Impl>
 class LSQUnit {
-  protected:
-    typedef TheISA::IntReg IntReg;
   public:
     typedef typename Impl::O3CPU O3CPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
@@ -338,7 +336,7 @@ class LSQUnit {
         /** The size of the store. */
         int size;
         /** The store data. */
-        char data[sizeof(IntReg)];
+        char data[16];
         /** Whether or not the store is split into two requests. */
         bool isSplit;
         /** Whether or not the store can writeback. */