arm: Add helper methods to setup architected PMU events
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@ -78,6 +78,59 @@ class ArmPMU(SimObject):
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for name in args:
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self._deferred_event_types.append((event_id, obj, name))
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def addArchEvents(self,
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cpu=None,
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itb=None, dtb=None,
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icache=None, dcache=None,
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l2cache=None):
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"""Add architected events to the PMU.
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This method can be called multiple times with only a subset of
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the keyword arguments set. This enables event registration in
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configuration scripts to happen closer to the instantiation of
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the instrumented objects (e.g., the memory system) instead of
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a central point.
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CPU events should also be registered once per CPU that is
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sharing the PMU (e.g., when switching between CPU models).
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"""
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bpred = cpu.branchPred if cpu and not isNullPointer(cpu.branchPred) \
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else None
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# 0x01: L1I_CACHE_REFILL
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self.addEventProbe(0x02, itb, "Refills")
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# 0x03: L2D_CACHE_REFILL
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# 0x04: L1D_CACHE
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self.addEventProbe(0x05, dtb, "Refills")
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self.addEventProbe(0x06, cpu, "RetiredLoads")
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self.addEventProbe(0x07, cpu, "RetiredStores")
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self.addEventProbe(0x08, cpu, "RetiredInsts")
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# 0x09: EXC_TAKEN
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# 0x0A: EXC_RETURN
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# 0x0B: CID_WRITE_RETIRED
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self.addEventProbe(0x0C, cpu, "RetiredBranches")
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# 0x0D: BR_IMMED_RETIRED
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# 0x0E: BR_RETURN_RETIRED
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# 0x0F: UNALIGEND_LDST_RETIRED
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self.addEventProbe(0x10, bpred, "Misses")
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self.addEventProbe(0x11, cpu, "Cycles")
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self.addEventProbe(0x12, bpred, "Branches")
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self.addEventProbe(0x13, cpu, "RetiredLoads", "RetiredStores")
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# 0x14: L1I_CACHE
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# 0x15: L1D_CACHE_WB
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# 0x16: L2D_CACHE
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# 0x17: L2D_CACHE_REFILL
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# 0x18: L2D_CACHE_WB
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# 0x19: BUS_ACCESS
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# 0x1A: MEMORY_ERROR
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# 0x1B: INST_SPEC
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# 0x1C: TTBR_WRITE_RETIRED
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# 0x1D: BUS_CYCLES
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# 0x1E: CHAIN
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# 0x1F: L1D_CACHE_ALLOCATE
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# 0x20: L2D_CACHE_ALLOCATE
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platform = Param.Platform(Parent.any, "Platform this device is part of.")
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eventCounters = Param.Int(31, "Number of supported PMU counters")
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pmuInterrupt = Param.Int(68, "PMU GIC interrupt number")
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