CPU: Get rid of two more duplicated CPU params.
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2 changed files with 0 additions and 4 deletions
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@ -35,8 +35,6 @@ class AtomicSimpleCPU(BaseSimpleCPU):
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width = Param.Int(1, "CPU width")
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width = Param.Int(1, "CPU width")
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simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
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simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
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simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
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simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace_start = Param.Tick(0, "Cycle to start function trace")
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icache_port = Port("Instruction Port")
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icache_port = Port("Instruction Port")
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dcache_port = Port("Data Port")
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dcache_port = Port("Data Port")
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physmem_port = Port("Physical Memory Port")
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physmem_port = Port("Physical Memory Port")
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@ -32,8 +32,6 @@ from BaseSimpleCPU import BaseSimpleCPU
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class TimingSimpleCPU(BaseSimpleCPU):
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class TimingSimpleCPU(BaseSimpleCPU):
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type = 'TimingSimpleCPU'
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type = 'TimingSimpleCPU'
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace_start = Param.Tick(0, "Cycle to start function trace")
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icache_port = Port("Instruction Port")
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icache_port = Port("Instruction Port")
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dcache_port = Port("Data Port")
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dcache_port = Port("Data Port")
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_mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
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_mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
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