inorder-fetch: update model to use predecoder
This commit is contained in:
Korey Sewell
parent
c9a03f549b
commit
3603dd25ef
7 changed files with 50 additions and 51 deletions
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@ -137,6 +137,7 @@ FirstStage::processInsts(unsigned tid)
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inst = new InOrderDynInst(cpu,
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cpu->thread[tid],
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cpu->nextInstSeqNum(tid),
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tid,
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tid);
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#if TRACING_ON
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@ -145,6 +146,8 @@ FirstStage::processInsts(unsigned tid)
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cpu->stageTracing,
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cpu->thread[tid]->getTC());
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#else
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inst->traceData = NULL;
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#endif // TRACING_ON
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DPRINTF(RefCount, "creation: [tid:%i]: [sn:%i]: Refcount = %i.\n",
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@ -66,12 +66,14 @@ InOrderDynInst::InOrderDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
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InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
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InOrderThreadState *state,
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InstSeqNum seq_num,
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unsigned tid)
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unsigned tid,
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unsigned _asid)
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: traceData(NULL), cpu(cpu)
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{
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seqNum = seq_num;
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thread = state;
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threadNumber = tid;
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asid = _asid;
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initVars();
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}
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@ -113,7 +113,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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* NOTE: Must set Binary Instrution through Member Function
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*/
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InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state, InstSeqNum seq_num,
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unsigned tid);
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unsigned tid, unsigned asid = 0);
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/** BaseDynInst constructor given a StaticInst pointer.
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* @param _staticInst The StaticInst for this BaseDynInst.
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@ -111,7 +111,7 @@ PipelineStage::setCPU(InOrderCPU *cpu_ptr)
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{
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cpu = cpu_ptr;
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dummyBufferInst = new InOrderDynInst(cpu_ptr, NULL, 0, 0);
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dummyBufferInst = new InOrderDynInst(cpu_ptr, NULL, 0, 0, 0);
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DPRINTF(InOrderStage, "Set CPU pointer.\n");
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@ -281,7 +281,7 @@ Resource::deactivateThread(unsigned tid)
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{
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// In the most basic case, deactivation means squashing everything
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// from a particular thread
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DynInstPtr dummy_inst = new InOrderDynInst(cpu, NULL, 0, tid);
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DynInstPtr dummy_inst = new InOrderDynInst(cpu, NULL, 0, tid, tid);
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squash(dummy_inst, 0, 0, tid);
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}
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@ -34,6 +34,7 @@
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#include "arch/isa_traits.hh"
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#include "arch/locked_mem.hh"
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#include "arch/utility.hh"
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#include "arch/predecoder.hh"
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#include "cpu/inorder/resources/cache_unit.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/cpu.hh"
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@ -81,7 +82,8 @@ CacheUnit::CachePort::recvRetry()
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CacheUnit::CacheUnit(string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
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: Resource(res_name, res_id, res_width, res_latency, _cpu),
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retryPkt(NULL), retrySlot(-1), cacheBlocked(false)
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retryPkt(NULL), retrySlot(-1), cacheBlocked(false),
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predecoder(NULL)
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{
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cachePort = new CachePort(this);
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}
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@ -259,35 +261,11 @@ CacheUnit::execute(int slot_num)
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"[tid:%i]: Completing Fetch Access for [sn:%i]\n",
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tid, inst->seqNum);
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MachInst mach_inst = cache_req->dataPkt->get<MachInst>();
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/**
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* @TODO: May Need This Function for Endianness-Compatibility
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* mach_inst =
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* gtoh(*reinterpret_cast<MachInst *>(&cacheData[tid][offset]));
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*/
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DPRINTF(InOrderCachePort,
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"[tid:%i]: Fetched instruction is %08p\n",
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tid, mach_inst);
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// ExtMachInst ext_inst = makeExtMI(mach_inst, cpu->tcBase(tid));
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inst->setMachInst(mach_inst);
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inst->setASID(tid);
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inst->setThreadState(cpu->thread[tid]);
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DPRINTF(InOrderStage, "[tid:%i]: Instruction [sn:%i] is: %s\n",
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DPRINTF(InOrderCachePort, "[tid:%i]: Instruction [sn:%i] is: %s\n",
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tid, seq_num, inst->staticInst->disassemble(inst->PC));
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// Set Up More TraceData info
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if (inst->traceData) {
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inst->traceData->setStaticInst(inst->staticInst);
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inst->traceData->setPC(inst->readPC());
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}
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delete cache_req->dataPkt;
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cache_req->done();
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} else {
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DPRINTF(InOrderCachePort,
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@ -396,7 +374,6 @@ CacheUnit::doDataAccess(DynInstPtr inst)
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cache_req->dataPkt->dataStatic(cache_req->reqData);
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} else if (cache_req->dataPkt->isWrite()) {
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cache_req->dataPkt->dataStatic(&cache_req->inst->storeData);
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}
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cache_req->dataPkt->time = curTick;
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@ -514,6 +491,33 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
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DPRINTF(InOrderCachePort,
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"[tid:%u]: [sn:%i]: Processing fetch access\n",
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tid, inst->seqNum);
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// NOTE: This is only allowing a thread to fetch one line
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// at a time. Re-examine when/if prefetching
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// gets implemented.
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//memcpy(fetchData[tid], cache_pkt->getPtr<uint8_t>(),
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// cache_pkt->getSize());
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// Get the instruction from the array of the cache line.
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// @todo: update thsi
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ExtMachInst ext_inst;
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StaticInstPtr staticInst = NULL;
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Addr inst_pc = inst->readPC();
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MachInst mach_inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
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(cache_pkt->getPtr<uint8_t>()));
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predecoder.setTC(cpu->thread[tid]->getTC());
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predecoder.moreBytes(inst_pc, inst_pc, mach_inst);
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ext_inst = predecoder.getExtMachInst();
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inst->setMachInst(ext_inst);
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// Set Up More TraceData info
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if (inst->traceData) {
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inst->traceData->setStaticInst(inst->staticInst);
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inst->traceData->setPC(inst->readPC());
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}
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} else if (inst->staticInst && inst->isMemRef()) {
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DPRINTF(InOrderCachePort,
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"[tid:%u]: [sn:%i]: Processing cache access\n",
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@ -546,7 +550,6 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
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"[tid:%u]: [sn:%i]: Data stored was: %08p\n",
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tid, inst->seqNum,
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getMemData(cache_pkt));
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}
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delete cache_pkt;
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@ -36,8 +36,7 @@
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#include <list>
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#include <string>
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//#include "cpu/inorder/params.hh"
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#include "arch/predecoder.hh"
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#include "cpu/inorder/resource.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "mem/packet.hh"
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@ -154,19 +153,12 @@ class CacheUnit : public Resource
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/** Align a PC to the start of an I-cache block. */
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Addr cacheBlockAlignPC(Addr addr)
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{
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//addr = TheISA::realPCToFetchPC(addr);
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return (addr & ~(cacheBlkMask));
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}
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/** Returns a specific port. */
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Port *getPort(const std::string &if_name, int idx);
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/** Fetch on behalf of an instruction. Will check to see
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* if instruction is actually in resource before
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* trying to fetch.
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*/
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//Fault doFetchAccess(DynInstPtr inst);
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/** Read/Write on behalf of an instruction.
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* curResSlot needs to be a valid value in instruction.
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*/
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@ -207,17 +199,16 @@ class CacheUnit : public Resource
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return (addr & ~(cacheBlkMask));
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}
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/** THINGS USED FOR FETCH */
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// NO LONGER USED BY COMMENT OUT UNTIL FULL VERIFICATION
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/** The mem line being fetched. */
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//uint8_t *cacheData[ThePipeline::MaxThreads];
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uint8_t *fetchData[ThePipeline::MaxThreads];
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/** @TODO: Move functionaly of fetching more than
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one instruction to 'fetch unit'*/
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/** The Addr of the cacheline that has been loaded. */
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//Addr cacheBlockAddr[ThePipeline::MaxThreads];
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//unsigned fetchOffset[ThePipeline::MaxThreads];
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/** @todo: Add Resource Stats Here */
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TheISA::Predecoder predecoder;
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};
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struct CacheSchedEntry : public ThePipeline::ScheduleEntry
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