ARM: Add VExpress_E support with PCIe to gem5

This commit is contained in:
Ali Saidi 2011-08-19 15:08:08 -05:00
parent d2a0a2ec22
commit 2fd2b44b86
7 changed files with 53 additions and 17 deletions

View file

@ -210,8 +210,8 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
self.realview = RealViewPBX()
elif machine_type == "RealView_EB":
self.realview = RealViewEB()
elif machine_type == "VersatileExpress":
self.realview = VExpress()
elif machine_type == "VExpress_ELT":
self.realview = VExpress_ELT()
else:
print "Unknown Machine Type"
sys.exit(1)
@ -221,8 +221,12 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
use_cf = True
self.cf0 = CowIdeDisk(driveID='master')
self.cf0.childImage(mdesc.disk())
self.realview.cf_ctrl.disks = [self.cf0]
# default to an IDE controller rather than a CF one
# assuming we've got one
try:
self.realview.ide.disks = [self.cf0]
except:
self.realview.cf_ctrl.disks = [self.cf0]
if bare_metal:
# EOT character on UART will end the simulation
self.realview.uart.end_on_eot = True
@ -261,7 +265,6 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
self.physmem.port = self.membus.port
self.realview.attachOnChipIO(self.membus)
self.realview.attachIO(self.iobus)
self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()

View file

@ -42,7 +42,8 @@ from System import System
class ArmMachineType(Enum):
map = {'RealView_EB' : 827,
'RealView_PBX' : 1901,
'VersatileExpress' : 2272}
'VExpress_ELT' : 2272,
'VExpress_CA9' : 2272}
class ArmSystem(System):
type = 'ArmSystem'

View file

@ -43,6 +43,8 @@
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
from Pci import PciConfigAll
from Ethernet import NSGigE, IGbE_e1000, IGbE_igb
from Ide import *
from Platform import Platform
from Terminal import Terminal
@ -132,6 +134,7 @@ class Pl111(AmbaDmaDevice):
class RealView(Platform):
type = 'RealView'
system = Param.System(Parent.any, "system")
pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
# Reference for memory map and interrupt number
# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
@ -147,7 +150,7 @@ class RealViewPBX(RealView):
kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
a9scu = A9SCU(pio_addr=0x1f000000)
cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=0,
cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
io_shift = 1, ctrl_offset = 2, Command = 0x1,
BAR0 = 0x18000000, BAR0Size = '16B',
BAR1 = 0x18000100, BAR1Size = '1B',
@ -279,7 +282,8 @@ class RealViewEB(RealView):
self.flash_fake.pio = bus.port
self.smcreg_fake.pio = bus.port
class VExpress(RealView):
class VExpress_ELT(RealView):
pci_cfg_base = 0xD0000000
elba_uart = Pl011(pio_addr=0xE0009000, int_num=42)
uart = Pl011(pio_addr=0xFF009000, int_num=121)
realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000)
@ -295,12 +299,19 @@ class VExpress(RealView):
elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52)
elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53)
a9scu = A9SCU(pio_addr=0xE0200000)
cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=0,
cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
io_shift = 2, ctrl_offset = 2, Command = 0x1,
BAR0 = 0xFF01A000, BAR0Size = '256B',
BAR1 = 0xFF01A100, BAR1Size = '4096B',
BAR0LegacyIO = True, BAR1LegacyIO = True)
pciconfig = PciConfigAll()
ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
InterruptLine=1, InterruptPin=1)
ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
InterruptLine=2, InterruptPin=2)
l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff)
dmac_fake = AmbaFake(pio_addr=0xE0020000)
uart1_fake = AmbaFake(pio_addr=0xE000A000)
@ -341,6 +352,11 @@ class VExpress(RealView):
self.elba_kmi0.pio = bus.port
self.elba_kmi1.pio = bus.port
self.cf_ctrl.pio = bus.port
self.ide.pio = bus.port
self.ethernet.pio = bus.port
self.pciconfig.pio = bus.default
bus.use_default_range = True
self.l2x0_fake.pio = bus.port
self.dmac_fake.pio = bus.port
self.uart1_fake.pio = bus.port

View file

@ -46,6 +46,7 @@
#include "debug/GIC.hh"
#include "debug/IPI.hh"
#include "dev/arm/gic.hh"
#include "dev/arm/realview.hh"
#include "dev/terminal.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
@ -98,6 +99,10 @@ Gic::Gic(const Params *p)
}
}
RealView *rv = dynamic_cast<RealView*>(p->platform);
assert(rv);
rv->setGic(this);
}
Tick

View file

@ -50,6 +50,7 @@
#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
#include "dev/arm/gic.hh"
#include "dev/arm/realview.hh"
#include "dev/terminal.hh"
#include "sim/system.hh"
@ -88,27 +89,28 @@ RealView::clearConsoleInt()
void
RealView::postPciInt(int line)
{
panic("Need implementation\n");
gic->sendInt(line);
}
void
RealView::clearPciInt(int line)
{
panic("Need implementation\n");
gic->clearInt(line);
}
Addr
RealView::pciToDma(Addr pciAddr) const
{
panic("Need implementation\n");
M5_DUMMY_RETURN
return pciAddr;
}
Addr
RealView::calcPciConfigAddr(int bus, int dev, int func)
{
return ULL(-1);
if (bus != 0)
return ULL(-1);
return params()->pci_cfg_base | ((func & 7) << 16) | ((dev & 0x1f) << 19);
}
Addr
@ -120,8 +122,7 @@ RealView::calcPciIOAddr(Addr addr)
Addr
RealView::calcPciMemAddr(Addr addr)
{
panic("Need implementation\n");
M5_DUMMY_RETURN
return addr;
}
RealView *

View file

@ -61,8 +61,15 @@ class RealView : public Platform
/** Pointer to the system */
System *system;
Gic *gic;
public:
typedef RealViewParams Params;
const Params *
params() const {
return dynamic_cast<const Params *>(_params);
}
/**
* Constructor for the Tsunami Class.
* @param name name of the object
@ -71,6 +78,9 @@ class RealView : public Platform
*/
RealView(const Params *p);
/** Give platform a pointer to interrupt controller */
void setGic(Gic *_gic) { gic = _gic; }
/**
* Return the interrupting frequency to AlphaAccess
* @return frequency of RTC interrupts

View file

@ -143,7 +143,7 @@ PciDev::PciDev(const Params *p)
}
}
plat->registerPciDevice(0, p->pci_dev, p->pci_func,
plat->registerPciDevice(p->pci_bus, p->pci_dev, p->pci_func,
letoh(config.interruptLine));
}