ARM: Add VExpress_E support with PCIe to gem5
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parent
d2a0a2ec22
commit
2fd2b44b86
7 changed files with 53 additions and 17 deletions
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@ -210,8 +210,8 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
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self.realview = RealViewPBX()
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elif machine_type == "RealView_EB":
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self.realview = RealViewEB()
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elif machine_type == "VersatileExpress":
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self.realview = VExpress()
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elif machine_type == "VExpress_ELT":
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self.realview = VExpress_ELT()
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else:
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print "Unknown Machine Type"
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sys.exit(1)
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@ -221,8 +221,12 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
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use_cf = True
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self.cf0 = CowIdeDisk(driveID='master')
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self.cf0.childImage(mdesc.disk())
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# default to an IDE controller rather than a CF one
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# assuming we've got one
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try:
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self.realview.ide.disks = [self.cf0]
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except:
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self.realview.cf_ctrl.disks = [self.cf0]
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if bare_metal:
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# EOT character on UART will end the simulation
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self.realview.uart.end_on_eot = True
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@ -261,7 +265,6 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
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self.physmem.port = self.membus.port
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self.realview.attachOnChipIO(self.membus)
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self.realview.attachIO(self.iobus)
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self.intrctrl = IntrControl()
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self.terminal = Terminal()
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self.vncserver = VncServer()
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@ -42,7 +42,8 @@ from System import System
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class ArmMachineType(Enum):
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map = {'RealView_EB' : 827,
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'RealView_PBX' : 1901,
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'VersatileExpress' : 2272}
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'VExpress_ELT' : 2272,
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'VExpress_CA9' : 2272}
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class ArmSystem(System):
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type = 'ArmSystem'
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@ -43,6 +43,8 @@
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from m5.params import *
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from m5.proxy import *
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from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
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from Pci import PciConfigAll
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from Ethernet import NSGigE, IGbE_e1000, IGbE_igb
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from Ide import *
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from Platform import Platform
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from Terminal import Terminal
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@ -132,6 +134,7 @@ class Pl111(AmbaDmaDevice):
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class RealView(Platform):
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type = 'RealView'
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system = Param.System(Parent.any, "system")
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pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
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# Reference for memory map and interrupt number
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# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
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@ -147,7 +150,7 @@ class RealViewPBX(RealView):
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kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
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kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
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a9scu = A9SCU(pio_addr=0x1f000000)
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cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=0,
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cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
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io_shift = 1, ctrl_offset = 2, Command = 0x1,
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BAR0 = 0x18000000, BAR0Size = '16B',
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BAR1 = 0x18000100, BAR1Size = '1B',
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@ -279,7 +282,8 @@ class RealViewEB(RealView):
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self.flash_fake.pio = bus.port
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self.smcreg_fake.pio = bus.port
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class VExpress(RealView):
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class VExpress_ELT(RealView):
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pci_cfg_base = 0xD0000000
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elba_uart = Pl011(pio_addr=0xE0009000, int_num=42)
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uart = Pl011(pio_addr=0xFF009000, int_num=121)
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realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000)
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@ -295,12 +299,19 @@ class VExpress(RealView):
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elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52)
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elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53)
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a9scu = A9SCU(pio_addr=0xE0200000)
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cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=0,
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cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
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io_shift = 2, ctrl_offset = 2, Command = 0x1,
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BAR0 = 0xFF01A000, BAR0Size = '256B',
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BAR1 = 0xFF01A100, BAR1Size = '4096B',
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BAR0LegacyIO = True, BAR1LegacyIO = True)
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pciconfig = PciConfigAll()
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ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
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InterruptLine=1, InterruptPin=1)
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ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
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InterruptLine=2, InterruptPin=2)
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l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff)
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dmac_fake = AmbaFake(pio_addr=0xE0020000)
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uart1_fake = AmbaFake(pio_addr=0xE000A000)
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@ -341,6 +352,11 @@ class VExpress(RealView):
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self.elba_kmi0.pio = bus.port
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self.elba_kmi1.pio = bus.port
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self.cf_ctrl.pio = bus.port
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self.ide.pio = bus.port
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self.ethernet.pio = bus.port
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self.pciconfig.pio = bus.default
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bus.use_default_range = True
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self.l2x0_fake.pio = bus.port
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self.dmac_fake.pio = bus.port
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self.uart1_fake.pio = bus.port
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@ -46,6 +46,7 @@
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#include "debug/GIC.hh"
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#include "debug/IPI.hh"
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#include "dev/arm/gic.hh"
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#include "dev/arm/realview.hh"
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#include "dev/terminal.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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@ -98,6 +99,10 @@ Gic::Gic(const Params *p)
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}
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}
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RealView *rv = dynamic_cast<RealView*>(p->platform);
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assert(rv);
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rv->setGic(this);
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}
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Tick
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@ -50,6 +50,7 @@
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#include "config/the_isa.hh"
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#include "cpu/intr_control.hh"
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#include "dev/arm/gic.hh"
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#include "dev/arm/realview.hh"
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#include "dev/terminal.hh"
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#include "sim/system.hh"
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@ -88,27 +89,28 @@ RealView::clearConsoleInt()
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void
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RealView::postPciInt(int line)
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{
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panic("Need implementation\n");
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gic->sendInt(line);
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}
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void
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RealView::clearPciInt(int line)
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{
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panic("Need implementation\n");
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gic->clearInt(line);
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}
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Addr
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RealView::pciToDma(Addr pciAddr) const
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{
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panic("Need implementation\n");
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M5_DUMMY_RETURN
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return pciAddr;
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}
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Addr
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RealView::calcPciConfigAddr(int bus, int dev, int func)
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{
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if (bus != 0)
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return ULL(-1);
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return params()->pci_cfg_base | ((func & 7) << 16) | ((dev & 0x1f) << 19);
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}
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Addr
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@ -120,8 +122,7 @@ RealView::calcPciIOAddr(Addr addr)
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Addr
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RealView::calcPciMemAddr(Addr addr)
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{
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panic("Need implementation\n");
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M5_DUMMY_RETURN
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return addr;
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}
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RealView *
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@ -61,8 +61,15 @@ class RealView : public Platform
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/** Pointer to the system */
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System *system;
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Gic *gic;
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public:
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typedef RealViewParams Params;
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const Params *
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params() const {
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return dynamic_cast<const Params *>(_params);
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}
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/**
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* Constructor for the Tsunami Class.
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* @param name name of the object
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@ -71,6 +78,9 @@ class RealView : public Platform
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*/
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RealView(const Params *p);
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/** Give platform a pointer to interrupt controller */
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void setGic(Gic *_gic) { gic = _gic; }
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/**
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* Return the interrupting frequency to AlphaAccess
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* @return frequency of RTC interrupts
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@ -143,7 +143,7 @@ PciDev::PciDev(const Params *p)
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}
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}
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plat->registerPciDevice(0, p->pci_dev, p->pci_func,
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plat->registerPciDevice(p->pci_bus, p->pci_dev, p->pci_func,
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letoh(config.interruptLine));
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}
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