cpu: Rename defer_registration->switched_out

The defer_registration parameter is used to prevent a CPU from
initializing at startup, leaving it in the "switched out" mode. The
name of this parameter (and the help string) is confusing. This patch
renames it to switched_out, which should be more descriptive.
This commit is contained in:
Andreas Sandberg 2013-01-07 13:05:45 -05:00
parent f7da0fddd1
commit 2cfe62adc4
13 changed files with 29 additions and 36 deletions

View file

@ -141,7 +141,7 @@ class O3_ARM_v7a_3(DerivO3CPU):
numIQEntries = 32 numIQEntries = 32
numROBEntries = 40 numROBEntries = 40
defer_registration= False switched_out = False
# Instruction Cache # Instruction Cache
class O3_ARM_v7a_ICache(BaseCache): class O3_ARM_v7a_ICache(BaseCache):

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@ -296,7 +296,7 @@ def run(options, root, testsys, cpu_class):
testsys.cpu[i].max_insts_any_thread = options.maxinsts testsys.cpu[i].max_insts_any_thread = options.maxinsts
if cpu_class: if cpu_class:
switch_cpus = [cpu_class(defer_registration=True, cpu_id=(i)) switch_cpus = [cpu_class(switched_out=True, cpu_id=(i))
for i in xrange(np)] for i in xrange(np)]
for i in xrange(np): for i in xrange(np):
@ -321,23 +321,23 @@ def run(options, root, testsys, cpu_class):
print "O3 CPU must be used with caches" print "O3 CPU must be used with caches"
sys.exit(1) sys.exit(1)
repeat_switch_cpus = [O3_ARM_v7a_3(defer_registration=True, \ repeat_switch_cpus = [O3_ARM_v7a_3(switched_out=True, \
cpu_id=(i)) for i in xrange(np)] cpu_id=(i)) for i in xrange(np)]
elif options.cpu_type == "detailed": elif options.cpu_type == "detailed":
if not options.caches: if not options.caches:
print "O3 CPU must be used with caches" print "O3 CPU must be used with caches"
sys.exit(1) sys.exit(1)
repeat_switch_cpus = [DerivO3CPU(defer_registration=True, \ repeat_switch_cpus = [DerivO3CPU(switched_out=True, \
cpu_id=(i)) for i in xrange(np)] cpu_id=(i)) for i in xrange(np)]
elif options.cpu_type == "inorder": elif options.cpu_type == "inorder":
print "inorder CPU switching not supported" print "inorder CPU switching not supported"
sys.exit(1) sys.exit(1)
elif options.cpu_type == "timing": elif options.cpu_type == "timing":
repeat_switch_cpus = [TimingSimpleCPU(defer_registration=True, \ repeat_switch_cpus = [TimingSimpleCPU(switched_out=True, \
cpu_id=(i)) for i in xrange(np)] cpu_id=(i)) for i in xrange(np)]
else: else:
repeat_switch_cpus = [AtomicSimpleCPU(defer_registration=True, \ repeat_switch_cpus = [AtomicSimpleCPU(switched_out=True, \
cpu_id=(i)) for i in xrange(np)] cpu_id=(i)) for i in xrange(np)]
for i in xrange(np): for i in xrange(np):
@ -361,9 +361,9 @@ def run(options, root, testsys, cpu_class):
for i in xrange(np)] for i in xrange(np)]
if options.standard_switch: if options.standard_switch:
switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(i)) switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i))
for i in xrange(np)] for i in xrange(np)]
switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(i)) switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i))
for i in xrange(np)] for i in xrange(np)]
for i in xrange(np): for i in xrange(np):

View file

@ -173,8 +173,9 @@ class BaseCPU(MemObject):
progress_interval = Param.Frequency('0Hz', progress_interval = Param.Frequency('0Hz',
"frequency to print out the progress message") "frequency to print out the progress message")
defer_registration = Param.Bool(False, switched_out = Param.Bool(False,
"defer registration with system (for sampling)") "Leave the CPU switched out after startup (used when switching " \
"between CPU models)")
tracer = Param.InstTracer(default_tracer, "Instruction tracer") tracer = Param.InstTracer(default_tracer, "Instruction tracer")

View file

@ -119,7 +119,7 @@ BaseCPU::BaseCPU(Params *p, bool is_checker)
_instMasterId(p->system->getMasterId(name() + ".inst")), _instMasterId(p->system->getMasterId(name() + ".inst")),
_dataMasterId(p->system->getMasterId(name() + ".data")), _dataMasterId(p->system->getMasterId(name() + ".data")),
_taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid), _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid),
_switchedOut(p->defer_registration), _switchedOut(p->switched_out),
interrupts(p->interrupts), profileEvent(NULL), interrupts(p->interrupts), profileEvent(NULL),
numThreads(p->numThreads), system(p->system) numThreads(p->numThreads), system(p->system)
{ {
@ -217,7 +217,7 @@ BaseCPU::BaseCPU(Params *p, bool is_checker)
// The interrupts should always be present unless this CPU is // The interrupts should always be present unless this CPU is
// switched in later or in case it is a checker CPU // switched in later or in case it is a checker CPU
if (!params()->defer_registration && !is_checker) { if (!params()->switched_out && !is_checker) {
if (interrupts) { if (interrupts) {
interrupts->setCPU(this); interrupts->setCPU(this);
} else { } else {
@ -254,7 +254,7 @@ BaseCPU::~BaseCPU()
void void
BaseCPU::init() BaseCPU::init()
{ {
if (!params()->defer_registration) if (!params()->switched_out)
registerThreadContexts(); registerThreadContexts();
} }
@ -262,7 +262,7 @@ void
BaseCPU::startup() BaseCPU::startup()
{ {
if (FullSystem) { if (FullSystem) {
if (!params()->defer_registration && profileEvent) if (!params()->switched_out && profileEvent)
schedule(profileEvent, curTick()); schedule(profileEvent, curTick());
} }

View file

@ -242,7 +242,6 @@ InOrderCPU::InOrderCPU(Params *params)
resReqCount(0), resReqCount(0),
#endif // DEBUG #endif // DEBUG
drainCount(0), drainCount(0),
deferRegistration(false/*params->deferRegistration*/),
stageTracing(params->stageTracing), stageTracing(params->stageTracing),
lastRunningCycle(0), lastRunningCycle(0),
instsPerSwitch(0) instsPerSwitch(0)
@ -386,7 +385,7 @@ InOrderCPU::InOrderCPU(Params *params)
} }
// InOrderCPU always requires an interrupt controller. // InOrderCPU always requires an interrupt controller.
if (!params->defer_registration && !interrupts) { if (!params->switched_out && !interrupts) {
fatal("InOrderCPU %s has no interrupt controller.\n" fatal("InOrderCPU %s has no interrupt controller.\n"
"Ensure createInterruptController() is called.\n", name()); "Ensure createInterruptController() is called.\n", name());
} }
@ -787,7 +786,7 @@ InOrderCPU::init()
{ {
BaseCPU::init(); BaseCPU::init();
if (!params()->defer_registration && if (!params()->switched_out &&
system->getMemoryMode() != Enums::timing) { system->getMemoryMode() != Enums::timing) {
fatal("The in-order CPU requires the memory system to be in " fatal("The in-order CPU requires the memory system to be in "
"'timing' mode.\n"); "'timing' mode.\n");
@ -801,7 +800,7 @@ InOrderCPU::init()
thread[tid]->initMemProxies(thread[tid]->getTC()); thread[tid]->initMemProxies(thread[tid]->getTC());
} }
if (FullSystem && !params()->defer_registration) { if (FullSystem && !params()->switched_out) {
for (ThreadID tid = 0; tid < numThreads; tid++) { for (ThreadID tid = 0; tid < numThreads; tid++) {
ThreadContext *src_tc = threadContexts[tid]; ThreadContext *src_tc = threadContexts[tid];
TheISA::initCPU(src_tc, src_tc->contextId()); TheISA::initCPU(src_tc, src_tc->contextId());

View file

@ -856,9 +856,6 @@ class InOrderCPU : public BaseCPU
/** Pointers to all of the threads in the CPU. */ /** Pointers to all of the threads in the CPU. */
std::vector<Thread *> thread; std::vector<Thread *> thread;
/** Whether or not the CPU should defer its registration. */
bool deferRegistration;
/** Per-Stage Instruction Tracing */ /** Per-Stage Instruction Tracing */
bool stageTracing; bool stageTracing;

View file

@ -258,10 +258,9 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
globalSeqNum(1), globalSeqNum(1),
system(params->system), system(params->system),
drainCount(0), drainCount(0),
deferRegistration(params->defer_registration),
lastRunningCycle(curCycle()) lastRunningCycle(curCycle())
{ {
if (!deferRegistration) { if (!params->switched_out) {
_status = Running; _status = Running;
} else { } else {
_status = SwitchedOut; _status = SwitchedOut;
@ -461,7 +460,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
} }
// FullO3CPU always requires an interrupt controller. // FullO3CPU always requires an interrupt controller.
if (!params->defer_registration && !interrupts) { if (!params->switched_out && !interrupts) {
fatal("FullO3CPU %s has no interrupt controller.\n" fatal("FullO3CPU %s has no interrupt controller.\n"
"Ensure createInterruptController() is called.\n", name()); "Ensure createInterruptController() is called.\n", name());
} }
@ -647,7 +646,7 @@ FullO3CPU<Impl>::init()
{ {
BaseCPU::init(); BaseCPU::init();
if (!params()->defer_registration && if (!params()->switched_out &&
system->getMemoryMode() != Enums::timing) { system->getMemoryMode() != Enums::timing) {
fatal("The O3 CPU requires the memory system to be in " fatal("The O3 CPU requires the memory system to be in "
"'timing' mode.\n"); "'timing' mode.\n");
@ -668,7 +667,7 @@ FullO3CPU<Impl>::init()
if (icachePort.isConnected()) if (icachePort.isConnected())
fetch.setIcache(); fetch.setIcache();
if (FullSystem && !params()->defer_registration) { if (FullSystem && !params()->switched_out) {
for (ThreadID tid = 0; tid < numThreads; tid++) { for (ThreadID tid = 0; tid < numThreads; tid++) {
ThreadContext *src_tc = threadContexts[tid]; ThreadContext *src_tc = threadContexts[tid];
TheISA::initCPU(src_tc, src_tc->contextId()); TheISA::initCPU(src_tc, src_tc->contextId());

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@ -741,9 +741,6 @@ class FullO3CPU : public BaseO3CPU
/** Pointers to all of the threads in the CPU. */ /** Pointers to all of the threads in the CPU. */
std::vector<Thread *> thread; std::vector<Thread *> thread;
/** Whether or not the CPU should defer its registration. */
bool deferRegistration;
/** Is there a context switch pending? */ /** Is there a context switch pending? */
bool contextSwitch; bool contextSwitch;

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@ -72,7 +72,7 @@ OzoneCheckerParams::create()
params->exitOnError = exitOnError; params->exitOnError = exitOnError;
params->updateOnError = updateOnError; params->updateOnError = updateOnError;
params->warnOnlyOnLoadError = warnOnlyOnLoadError; params->warnOnlyOnLoadError = warnOnlyOnLoadError;
params->deferRegistration = defer_registration; params->switched_out = switched_out;
params->functionTrace = function_trace; params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start; params->functionTraceStart = function_trace_start;
params->clock = clock; params->clock = clock;

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@ -189,7 +189,7 @@ DerivOzoneCPUParams::create()
params->instShiftAmt = 2; params->instShiftAmt = 2;
params->deferRegistration = defer_registration; params->switched_out = switched_out;
params->functionTrace = function_trace; params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start; params->functionTraceStart = function_trace_start;

View file

@ -185,7 +185,7 @@ SimpleOzoneCPUParams::create()
params->instShiftAmt = 2; params->instShiftAmt = 2;
params->deferRegistration = defer_registration; params->switchedOut = switched_out;
params->functionTrace = function_trace; params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start; params->functionTraceStart = function_trace_start;

View file

@ -83,7 +83,7 @@ AtomicSimpleCPU::init()
{ {
BaseCPU::init(); BaseCPU::init();
if (!params()->defer_registration && if (!params()->switched_out &&
system->getMemoryMode() != Enums::atomic) { system->getMemoryMode() != Enums::atomic) {
fatal("The atomic CPU requires the memory system to be in " fatal("The atomic CPU requires the memory system to be in "
"'atomic' mode.\n"); "'atomic' mode.\n");
@ -92,7 +92,7 @@ AtomicSimpleCPU::init()
// Initialise the ThreadContext's memory proxies // Initialise the ThreadContext's memory proxies
tcBase()->initMemProxies(tcBase()); tcBase()->initMemProxies(tcBase());
if (FullSystem && !params()->defer_registration) { if (FullSystem && !params()->switched_out) {
ThreadID size = threadContexts.size(); ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) { for (ThreadID i = 0; i < size; ++i) {
ThreadContext *tc = threadContexts[i]; ThreadContext *tc = threadContexts[i];

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@ -66,7 +66,7 @@ TimingSimpleCPU::init()
{ {
BaseCPU::init(); BaseCPU::init();
if (!params()->defer_registration && if (!params()->switched_out &&
system->getMemoryMode() != Enums::timing) { system->getMemoryMode() != Enums::timing) {
fatal("The timing CPU requires the memory system to be in " fatal("The timing CPU requires the memory system to be in "
"'timing' mode.\n"); "'timing' mode.\n");
@ -75,7 +75,7 @@ TimingSimpleCPU::init()
// Initialise the ThreadContext's memory proxies // Initialise the ThreadContext's memory proxies
tcBase()->initMemProxies(tcBase()); tcBase()->initMemProxies(tcBase());
if (FullSystem && !params()->defer_registration) { if (FullSystem && !params()->switched_out) {
for (int i = 0; i < threadContexts.size(); ++i) { for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i]; ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC // initialize CPU, including PC