From 2cfe62adc4f9206f616669a103133b906f705e8b Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Mon, 7 Jan 2013 13:05:45 -0500 Subject: [PATCH] cpu: Rename defer_registration->switched_out The defer_registration parameter is used to prevent a CPU from initializing at startup, leaving it in the "switched out" mode. The name of this parameter (and the help string) is confusing. This patch renames it to switched_out, which should be more descriptive. --- configs/common/O3_ARM_v7a.py | 2 +- configs/common/Simulation.py | 14 +++++++------- src/cpu/BaseCPU.py | 5 +++-- src/cpu/base.cc | 8 ++++---- src/cpu/inorder/cpu.cc | 7 +++---- src/cpu/inorder/cpu.hh | 3 --- src/cpu/o3/cpu.cc | 9 ++++----- src/cpu/o3/cpu.hh | 3 --- src/cpu/ozone/checker_builder.cc | 2 +- src/cpu/ozone/cpu_builder.cc | 2 +- src/cpu/ozone/simple_cpu_builder.cc | 2 +- src/cpu/simple/atomic.cc | 4 ++-- src/cpu/simple/timing.cc | 4 ++-- 13 files changed, 29 insertions(+), 36 deletions(-) diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py index 2c640badb..f76128ae6 100644 --- a/configs/common/O3_ARM_v7a.py +++ b/configs/common/O3_ARM_v7a.py @@ -141,7 +141,7 @@ class O3_ARM_v7a_3(DerivO3CPU): numIQEntries = 32 numROBEntries = 40 - defer_registration= False + switched_out = False # Instruction Cache class O3_ARM_v7a_ICache(BaseCache): diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 53ccf0a14..ea5949efc 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -296,7 +296,7 @@ def run(options, root, testsys, cpu_class): testsys.cpu[i].max_insts_any_thread = options.maxinsts if cpu_class: - switch_cpus = [cpu_class(defer_registration=True, cpu_id=(i)) + switch_cpus = [cpu_class(switched_out=True, cpu_id=(i)) for i in xrange(np)] for i in xrange(np): @@ -321,23 +321,23 @@ def run(options, root, testsys, cpu_class): print "O3 CPU must be used with caches" sys.exit(1) - repeat_switch_cpus = [O3_ARM_v7a_3(defer_registration=True, \ + repeat_switch_cpus = [O3_ARM_v7a_3(switched_out=True, \ cpu_id=(i)) for i in xrange(np)] elif options.cpu_type == "detailed": if not options.caches: print "O3 CPU must be used with caches" sys.exit(1) - repeat_switch_cpus = [DerivO3CPU(defer_registration=True, \ + repeat_switch_cpus = [DerivO3CPU(switched_out=True, \ cpu_id=(i)) for i in xrange(np)] elif options.cpu_type == "inorder": print "inorder CPU switching not supported" sys.exit(1) elif options.cpu_type == "timing": - repeat_switch_cpus = [TimingSimpleCPU(defer_registration=True, \ + repeat_switch_cpus = [TimingSimpleCPU(switched_out=True, \ cpu_id=(i)) for i in xrange(np)] else: - repeat_switch_cpus = [AtomicSimpleCPU(defer_registration=True, \ + repeat_switch_cpus = [AtomicSimpleCPU(switched_out=True, \ cpu_id=(i)) for i in xrange(np)] for i in xrange(np): @@ -361,9 +361,9 @@ def run(options, root, testsys, cpu_class): for i in xrange(np)] if options.standard_switch: - switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(i)) + switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i)) for i in xrange(np)] - switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(i)) + switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i)) for i in xrange(np)] for i in xrange(np): diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 957203150..6673b9d41 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -173,8 +173,9 @@ class BaseCPU(MemObject): progress_interval = Param.Frequency('0Hz', "frequency to print out the progress message") - defer_registration = Param.Bool(False, - "defer registration with system (for sampling)") + switched_out = Param.Bool(False, + "Leave the CPU switched out after startup (used when switching " \ + "between CPU models)") tracer = Param.InstTracer(default_tracer, "Instruction tracer") diff --git a/src/cpu/base.cc b/src/cpu/base.cc index b8cd60f63..202dc476a 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -119,7 +119,7 @@ BaseCPU::BaseCPU(Params *p, bool is_checker) _instMasterId(p->system->getMasterId(name() + ".inst")), _dataMasterId(p->system->getMasterId(name() + ".data")), _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid), - _switchedOut(p->defer_registration), + _switchedOut(p->switched_out), interrupts(p->interrupts), profileEvent(NULL), numThreads(p->numThreads), system(p->system) { @@ -217,7 +217,7 @@ BaseCPU::BaseCPU(Params *p, bool is_checker) // The interrupts should always be present unless this CPU is // switched in later or in case it is a checker CPU - if (!params()->defer_registration && !is_checker) { + if (!params()->switched_out && !is_checker) { if (interrupts) { interrupts->setCPU(this); } else { @@ -254,7 +254,7 @@ BaseCPU::~BaseCPU() void BaseCPU::init() { - if (!params()->defer_registration) + if (!params()->switched_out) registerThreadContexts(); } @@ -262,7 +262,7 @@ void BaseCPU::startup() { if (FullSystem) { - if (!params()->defer_registration && profileEvent) + if (!params()->switched_out && profileEvent) schedule(profileEvent, curTick()); } diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 3582e55ca..87272da7f 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -242,7 +242,6 @@ InOrderCPU::InOrderCPU(Params *params) resReqCount(0), #endif // DEBUG drainCount(0), - deferRegistration(false/*params->deferRegistration*/), stageTracing(params->stageTracing), lastRunningCycle(0), instsPerSwitch(0) @@ -386,7 +385,7 @@ InOrderCPU::InOrderCPU(Params *params) } // InOrderCPU always requires an interrupt controller. - if (!params->defer_registration && !interrupts) { + if (!params->switched_out && !interrupts) { fatal("InOrderCPU %s has no interrupt controller.\n" "Ensure createInterruptController() is called.\n", name()); } @@ -787,7 +786,7 @@ InOrderCPU::init() { BaseCPU::init(); - if (!params()->defer_registration && + if (!params()->switched_out && system->getMemoryMode() != Enums::timing) { fatal("The in-order CPU requires the memory system to be in " "'timing' mode.\n"); @@ -801,7 +800,7 @@ InOrderCPU::init() thread[tid]->initMemProxies(thread[tid]->getTC()); } - if (FullSystem && !params()->defer_registration) { + if (FullSystem && !params()->switched_out) { for (ThreadID tid = 0; tid < numThreads; tid++) { ThreadContext *src_tc = threadContexts[tid]; TheISA::initCPU(src_tc, src_tc->contextId()); diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index acdac11d9..1037ea2e6 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -856,9 +856,6 @@ class InOrderCPU : public BaseCPU /** Pointers to all of the threads in the CPU. */ std::vector thread; - /** Whether or not the CPU should defer its registration. */ - bool deferRegistration; - /** Per-Stage Instruction Tracing */ bool stageTracing; diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 78fbd6694..54c55f8c7 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -258,10 +258,9 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) globalSeqNum(1), system(params->system), drainCount(0), - deferRegistration(params->defer_registration), lastRunningCycle(curCycle()) { - if (!deferRegistration) { + if (!params->switched_out) { _status = Running; } else { _status = SwitchedOut; @@ -461,7 +460,7 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) } // FullO3CPU always requires an interrupt controller. - if (!params->defer_registration && !interrupts) { + if (!params->switched_out && !interrupts) { fatal("FullO3CPU %s has no interrupt controller.\n" "Ensure createInterruptController() is called.\n", name()); } @@ -647,7 +646,7 @@ FullO3CPU::init() { BaseCPU::init(); - if (!params()->defer_registration && + if (!params()->switched_out && system->getMemoryMode() != Enums::timing) { fatal("The O3 CPU requires the memory system to be in " "'timing' mode.\n"); @@ -668,7 +667,7 @@ FullO3CPU::init() if (icachePort.isConnected()) fetch.setIcache(); - if (FullSystem && !params()->defer_registration) { + if (FullSystem && !params()->switched_out) { for (ThreadID tid = 0; tid < numThreads; tid++) { ThreadContext *src_tc = threadContexts[tid]; TheISA::initCPU(src_tc, src_tc->contextId()); diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index eda9d9e91..c6083d8d5 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -741,9 +741,6 @@ class FullO3CPU : public BaseO3CPU /** Pointers to all of the threads in the CPU. */ std::vector thread; - /** Whether or not the CPU should defer its registration. */ - bool deferRegistration; - /** Is there a context switch pending? */ bool contextSwitch; diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc index 970591d33..a47225760 100644 --- a/src/cpu/ozone/checker_builder.cc +++ b/src/cpu/ozone/checker_builder.cc @@ -72,7 +72,7 @@ OzoneCheckerParams::create() params->exitOnError = exitOnError; params->updateOnError = updateOnError; params->warnOnlyOnLoadError = warnOnlyOnLoadError; - params->deferRegistration = defer_registration; + params->switched_out = switched_out; params->functionTrace = function_trace; params->functionTraceStart = function_trace_start; params->clock = clock; diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc index ffd05375b..b5466a869 100644 --- a/src/cpu/ozone/cpu_builder.cc +++ b/src/cpu/ozone/cpu_builder.cc @@ -189,7 +189,7 @@ DerivOzoneCPUParams::create() params->instShiftAmt = 2; - params->deferRegistration = defer_registration; + params->switched_out = switched_out; params->functionTrace = function_trace; params->functionTraceStart = function_trace_start; diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc index 1fd9d3b79..eb26338d4 100644 --- a/src/cpu/ozone/simple_cpu_builder.cc +++ b/src/cpu/ozone/simple_cpu_builder.cc @@ -185,7 +185,7 @@ SimpleOzoneCPUParams::create() params->instShiftAmt = 2; - params->deferRegistration = defer_registration; + params->switchedOut = switched_out; params->functionTrace = function_trace; params->functionTraceStart = function_trace_start; diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 2d026e733..5348d24d8 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -83,7 +83,7 @@ AtomicSimpleCPU::init() { BaseCPU::init(); - if (!params()->defer_registration && + if (!params()->switched_out && system->getMemoryMode() != Enums::atomic) { fatal("The atomic CPU requires the memory system to be in " "'atomic' mode.\n"); @@ -92,7 +92,7 @@ AtomicSimpleCPU::init() // Initialise the ThreadContext's memory proxies tcBase()->initMemProxies(tcBase()); - if (FullSystem && !params()->defer_registration) { + if (FullSystem && !params()->switched_out) { ThreadID size = threadContexts.size(); for (ThreadID i = 0; i < size; ++i) { ThreadContext *tc = threadContexts[i]; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 121db090b..621f99f29 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -66,7 +66,7 @@ TimingSimpleCPU::init() { BaseCPU::init(); - if (!params()->defer_registration && + if (!params()->switched_out && system->getMemoryMode() != Enums::timing) { fatal("The timing CPU requires the memory system to be in " "'timing' mode.\n"); @@ -75,7 +75,7 @@ TimingSimpleCPU::init() // Initialise the ThreadContext's memory proxies tcBase()->initMemProxies(tcBase()); - if (FullSystem && !params()->defer_registration) { + if (FullSystem && !params()->switched_out) { for (int i = 0; i < threadContexts.size(); ++i) { ThreadContext *tc = threadContexts[i]; // initialize CPU, including PC