sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Clean up more memory leaks

Browse source 
--HG--
extra : convert_revision : 32d1b23200752fe5fcdcbafb586f50bbe6db3bf3
This commit is contained in:
Ron Dreslinski 2007-03-12 15:59:54 -05:00
parent ca8e95b480
commit 2a02087eb5
1 changed files with 4 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
src/mem/cache/cache_impl.hh vendored
View file

@ -583,12 +583,7 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
// Hit // Hit
hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
// clear dirty bit if write through // clear dirty bit if write through
if (pkt->needsResponse()) respond(pkt, curTick+lat);
respond(pkt, curTick+lat);
if (pkt->cmd == MemCmd::Writeback) {
//Signal that you can kill the pkt/req
pkt->flags |= SATISFIED;
}
return true; return true;
} }
@ -606,14 +601,14 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
if (pkt->flags & SATISFIED) { if (pkt->flags & SATISFIED) {
// happens when a store conditional fails because it missed // happens when a store conditional fails because it missed
// the cache completely // the cache completely
if (pkt->needsResponse()) respond(pkt, curTick+lat);
respond(pkt, curTick+lat);
} else { } else {
missQueue->handleMiss(pkt, size, curTick + hitLatency); missQueue->handleMiss(pkt, size, curTick + hitLatency);
} }
if (pkt->cmd == MemCmd::Writeback) { if (!pkt->needsResponse()) {
//Need to clean up the packet on a writeback miss, but leave the request //Need to clean up the packet on a writeback miss, but leave the request
//for the next level.
delete pkt; delete pkt;
} }