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Merge zizzer:/bk/newmem

Browse source 
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head

--HG--
extra : convert_revision : 8651b2878853c5a6cb15f60ab92cf39d3bc30a07
This commit is contained in:
Ron Dreslinski 2007-03-12 13:42:49 -05:00
commit ca8e95b480
2 changed files with 11 additions and 5 deletions
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2
src/cpu/memtest/memtest.cc
View file

@ -369,7 +369,7 @@ MemTest::tick()
//This means we assume CPU does write forwarding to reads that alias something
//in the cpu store buffer.
if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
delete result;
delete [] result;
delete req;
return;
}

14
src/mem/cache/cache_impl.hh vendored
View file

@ -570,8 +570,10 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
}
}
while (!writebacks.empty()) {
missQueue->doWriteback(writebacks.front());
PacketPtr wbPkt = writebacks.front();
missQueue->doWriteback(wbPkt);
writebacks.pop_front();
delete wbPkt;
}
DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), pkt->getAddr(),
@ -721,8 +723,10 @@ Cache<TagStore,Coherence>::handleResponse(PacketPtr &pkt)
blk = handleFill(blk, (MSHR*)pkt->senderState,
new_state, writebacks, pkt);
while (!writebacks.empty()) {
missQueue->doWriteback(writebacks.front());
writebacks.pop_front();
PacketPtr wbPkt = writebacks.front();
missQueue->doWriteback(wbPkt);
writebacks.pop_front();
delete wbPkt;
}
}
missQueue->handleResponse(pkt, curTick + hitLatency);
@ -1040,8 +1044,10 @@ return 0;
// There was a cache hit.
// Handle writebacks if needed
while (!writebacks.empty()){
memSidePort->sendAtomic(writebacks.front());
PacketPtr wbPkt = writebacks.front();
memSidePort->sendAtomic(wbPkt);
writebacks.pop_front();
delete wbPkt;
}
hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;