Regressions: Update stats due to O3 CPU changes
This commit is contained in:
parent
6a7a6263e1
commit
26ca8b8747
55 changed files with 8489 additions and 8138 deletions
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@ -1,6 +1,7 @@
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[root]
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[root]
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type=Root
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type=Root
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children=system
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children=system
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full_system=true
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time_sync_enable=false
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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time_sync_spin_threshold=100000000
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@ -10,14 +11,14 @@ type=LinuxAlphaSystem
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children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
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children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
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boot_cpu_frequency=500
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boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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boot_osflags=root=/dev/hda1 console=ttyS0
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console=/dist/m5/system/binaries/console
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console=/scratch/nilay/GEM5/system/binaries/console
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init_param=0
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init_param=0
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kernel=/dist/m5/system/binaries/vmlinux
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kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
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load_addr_mask=1099511627775
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load_addr_mask=1099511627775
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mem_mode=timing
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mem_mode=timing
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memories=system.physmem
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memories=system.physmem
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num_work_ids=16
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num_work_ids=16
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pal=/dist/m5/system/binaries/ts_osfpal
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pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
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physmem=system.physmem
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physmem=system.physmem
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readfile=tests/halt.sh
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readfile=tests/halt.sh
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symbolfile=
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symbolfile=
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@ -104,6 +105,7 @@ max_insts_all_threads=0
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max_insts_any_thread=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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max_loads_any_thread=0
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needsTSO=false
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numIQEntries=64
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numIQEntries=64
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numPhysFloatRegs=256
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numPhysFloatRegs=256
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numPhysIntRegs=256
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numPhysIntRegs=256
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@ -135,6 +137,7 @@ tracer=system.cpu0.tracer
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trapLatency=13
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trapLatency=13
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wbDepth=1
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wbDepth=1
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wbWidth=8
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wbWidth=8
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workload=
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dcache_port=system.cpu0.dcache.cpu_side
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dcache_port=system.cpu0.dcache.cpu_side
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icache_port=system.cpu0.icache.cpu_side
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icache_port=system.cpu0.icache.cpu_side
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@ -540,6 +543,7 @@ max_insts_all_threads=0
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max_insts_any_thread=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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max_loads_any_thread=0
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needsTSO=false
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numIQEntries=64
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numIQEntries=64
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numPhysFloatRegs=256
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numPhysFloatRegs=256
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numPhysIntRegs=256
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numPhysIntRegs=256
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@ -571,6 +575,7 @@ tracer=system.cpu1.tracer
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trapLatency=13
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trapLatency=13
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wbDepth=1
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wbDepth=1
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wbWidth=8
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wbWidth=8
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workload=
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dcache_port=system.cpu1.dcache.cpu_side
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dcache_port=system.cpu1.dcache.cpu_side
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icache_port=system.cpu1.icache.cpu_side
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icache_port=system.cpu1.icache.cpu_side
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@ -932,7 +937,7 @@ table_size=65536
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[system.disk0.image.child]
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[system.disk0.image.child]
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type=RawDiskImage
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type=RawDiskImage
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image_file=/dist/m5/system/disks/linux-latest.img
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image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
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read_only=true
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read_only=true
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[system.disk2]
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[system.disk2]
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@ -952,7 +957,7 @@ table_size=65536
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[system.disk2.image.child]
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[system.disk2.image.child]
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type=RawDiskImage
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type=RawDiskImage
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image_file=/dist/m5/system/disks/linux-bigswap2.img
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image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
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read_only=true
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read_only=true
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[system.intrctrl]
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[system.intrctrl]
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@ -1052,7 +1057,6 @@ fake_mem=false
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pio_addr=0
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pio_addr=0
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=true
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ret_bad_addr=true
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1081,7 +1085,7 @@ system=system
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[system.simple_disk.disk]
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[system.simple_disk.disk]
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type=RawDiskImage
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type=RawDiskImage
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image_file=/dist/m5/system/disks/linux-latest.img
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image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
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read_only=true
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read_only=true
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[system.terminal]
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[system.terminal]
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@ -1122,7 +1126,6 @@ pio=system.iobus.port[25]
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type=TsunamiCChip
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type=TsunamiCChip
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pio_addr=8803072344064
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pio_addr=8803072344064
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pio_latency=1000
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pio_latency=1000
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platform=system.tsunami
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system=system
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system=system
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tsunami=system.tsunami
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tsunami=system.tsunami
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pio=system.iobus.port[1]
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pio=system.iobus.port[1]
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@ -1204,7 +1207,6 @@ fake_mem=false
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pio_addr=8796093677568
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pio_addr=8796093677568
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pio_latency=1000
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pio_latency=1000
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pio_size=393216
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pio_size=393216
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1221,7 +1223,6 @@ fake_mem=false
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pio_addr=8804615848432
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pio_addr=8804615848432
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1238,7 +1239,6 @@ fake_mem=false
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pio_addr=8804615848304
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pio_addr=8804615848304
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1255,7 +1255,6 @@ fake_mem=false
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pio_addr=8804615848569
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pio_addr=8804615848569
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1272,7 +1271,6 @@ fake_mem=false
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pio_addr=8804615848451
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pio_addr=8804615848451
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1289,7 +1287,6 @@ fake_mem=false
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pio_addr=8804615848515
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pio_addr=8804615848515
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1306,7 +1303,6 @@ fake_mem=false
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pio_addr=8804615848579
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pio_addr=8804615848579
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1323,7 +1319,6 @@ fake_mem=false
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pio_addr=8804615848643
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pio_addr=8804615848643
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1340,7 +1335,6 @@ fake_mem=false
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pio_addr=8804615848707
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pio_addr=8804615848707
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1357,7 +1351,6 @@ fake_mem=false
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pio_addr=8804615848771
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pio_addr=8804615848771
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1374,7 +1367,6 @@ fake_mem=false
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pio_addr=8804615848835
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pio_addr=8804615848835
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1391,7 +1383,6 @@ fake_mem=false
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pio_addr=8804615848899
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pio_addr=8804615848899
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1408,7 +1399,6 @@ fake_mem=false
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pio_addr=8804615850617
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pio_addr=8804615850617
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1425,7 +1415,6 @@ fake_mem=false
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pio_addr=8804615848891
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pio_addr=8804615848891
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1442,7 +1431,6 @@ fake_mem=false
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pio_addr=8804615848816
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pio_addr=8804615848816
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1459,7 +1447,6 @@ fake_mem=false
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pio_addr=8804615848696
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pio_addr=8804615848696
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1476,7 +1463,6 @@ fake_mem=false
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pio_addr=8804615848936
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pio_addr=8804615848936
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1493,7 +1479,6 @@ fake_mem=false
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pio_addr=8804615848680
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pio_addr=8804615848680
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1510,7 +1495,6 @@ fake_mem=false
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pio_addr=8804615848944
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pio_addr=8804615848944
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pio_latency=1000
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pio_latency=1000
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pio_size=8
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pio_size=8
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platform=system.tsunami
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ret_bad_addr=false
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ret_bad_addr=false
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ret_data16=65535
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ret_data16=65535
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ret_data32=4294967295
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ret_data32=4294967295
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@ -1526,7 +1510,6 @@ type=BadDevice
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devicename=FrameBuffer
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devicename=FrameBuffer
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pio_addr=8804615848912
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pio_addr=8804615848912
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pio_latency=1000
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pio_latency=1000
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platform=system.tsunami
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system=system
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system=system
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pio=system.iobus.port[22]
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pio=system.iobus.port[22]
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@ -1591,7 +1574,6 @@ type=TsunamiIO
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frequency=976562500
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frequency=976562500
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pio_addr=8804615847936
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pio_addr=8804615847936
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pio_latency=1000
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pio_latency=1000
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platform=system.tsunami
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system=system
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system=system
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time=Thu Jan 1 00:00:00 2009
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time=Thu Jan 1 00:00:00 2009
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tsunami=system.tsunami
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tsunami=system.tsunami
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@ -1602,7 +1584,6 @@ pio=system.iobus.port[23]
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type=TsunamiPChip
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type=TsunamiPChip
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pio_addr=8802535473152
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pio_addr=8802535473152
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pio_latency=1000
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pio_latency=1000
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platform=system.tsunami
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system=system
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system=system
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tsunami=system.tsunami
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tsunami=system.tsunami
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pio=system.iobus.port[2]
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pio=system.iobus.port[2]
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@ -1,13 +1,15 @@
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Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
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Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
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gem5 Simulator System. http://gem5.org
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gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 23 2012 03:53:29
|
gem5 compiled Feb 3 2012 13:46:22
|
||||||
gem5 started Jan 23 2012 06:11:48
|
gem5 started Feb 3 2012 13:46:34
|
||||||
gem5 executing on zizzer
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
|
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Launching CPU 1 @ 106949500
|
info: Launching CPU 1 @ 106949500
|
||||||
Exiting @ tick 1897465263500 because m5_exit instruction encountered
|
Exiting @ tick 1897464893500 because m5_exit instruction encountered
|
||||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=true
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -10,14 +11,14 @@ type=LinuxAlphaSystem
|
||||||
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||||
boot_cpu_frequency=500
|
boot_cpu_frequency=500
|
||||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||||
console=/dist/m5/system/binaries/console
|
console=/scratch/nilay/GEM5/system/binaries/console
|
||||||
init_param=0
|
init_param=0
|
||||||
kernel=/dist/m5/system/binaries/vmlinux
|
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
|
||||||
load_addr_mask=1099511627775
|
load_addr_mask=1099511627775
|
||||||
mem_mode=timing
|
mem_mode=timing
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
pal=/dist/m5/system/binaries/ts_osfpal
|
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
readfile=tests/halt.sh
|
readfile=tests/halt.sh
|
||||||
symbolfile=
|
symbolfile=
|
||||||
|
@ -104,6 +105,7 @@ max_insts_all_threads=0
|
||||||
max_insts_any_thread=0
|
max_insts_any_thread=0
|
||||||
max_loads_all_threads=0
|
max_loads_all_threads=0
|
||||||
max_loads_any_thread=0
|
max_loads_any_thread=0
|
||||||
|
needsTSO=false
|
||||||
numIQEntries=64
|
numIQEntries=64
|
||||||
numPhysFloatRegs=256
|
numPhysFloatRegs=256
|
||||||
numPhysIntRegs=256
|
numPhysIntRegs=256
|
||||||
|
@ -135,6 +137,7 @@ tracer=system.cpu.tracer
|
||||||
trapLatency=13
|
trapLatency=13
|
||||||
wbDepth=1
|
wbDepth=1
|
||||||
wbWidth=8
|
wbWidth=8
|
||||||
|
workload=
|
||||||
dcache_port=system.cpu.dcache.cpu_side
|
dcache_port=system.cpu.dcache.cpu_side
|
||||||
icache_port=system.cpu.icache.cpu_side
|
icache_port=system.cpu.icache.cpu_side
|
||||||
|
|
||||||
|
@ -496,7 +499,7 @@ table_size=65536
|
||||||
|
|
||||||
[system.disk0.image.child]
|
[system.disk0.image.child]
|
||||||
type=RawDiskImage
|
type=RawDiskImage
|
||||||
image_file=/dist/m5/system/disks/linux-latest.img
|
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||||
read_only=true
|
read_only=true
|
||||||
|
|
||||||
[system.disk2]
|
[system.disk2]
|
||||||
|
@ -516,7 +519,7 @@ table_size=65536
|
||||||
|
|
||||||
[system.disk2.image.child]
|
[system.disk2.image.child]
|
||||||
type=RawDiskImage
|
type=RawDiskImage
|
||||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||||
read_only=true
|
read_only=true
|
||||||
|
|
||||||
[system.intrctrl]
|
[system.intrctrl]
|
||||||
|
@ -616,7 +619,6 @@ fake_mem=false
|
||||||
pio_addr=0
|
pio_addr=0
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=true
|
ret_bad_addr=true
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -645,7 +647,7 @@ system=system
|
||||||
|
|
||||||
[system.simple_disk.disk]
|
[system.simple_disk.disk]
|
||||||
type=RawDiskImage
|
type=RawDiskImage
|
||||||
image_file=/dist/m5/system/disks/linux-latest.img
|
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||||
read_only=true
|
read_only=true
|
||||||
|
|
||||||
[system.terminal]
|
[system.terminal]
|
||||||
|
@ -686,7 +688,6 @@ pio=system.iobus.port[25]
|
||||||
type=TsunamiCChip
|
type=TsunamiCChip
|
||||||
pio_addr=8803072344064
|
pio_addr=8803072344064
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.tsunami
|
|
||||||
system=system
|
system=system
|
||||||
tsunami=system.tsunami
|
tsunami=system.tsunami
|
||||||
pio=system.iobus.port[1]
|
pio=system.iobus.port[1]
|
||||||
|
@ -768,7 +769,6 @@ fake_mem=false
|
||||||
pio_addr=8796093677568
|
pio_addr=8796093677568
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=393216
|
pio_size=393216
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -785,7 +785,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848432
|
pio_addr=8804615848432
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -802,7 +801,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848304
|
pio_addr=8804615848304
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -819,7 +817,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848569
|
pio_addr=8804615848569
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -836,7 +833,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848451
|
pio_addr=8804615848451
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -853,7 +849,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848515
|
pio_addr=8804615848515
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -870,7 +865,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848579
|
pio_addr=8804615848579
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -887,7 +881,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848643
|
pio_addr=8804615848643
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -904,7 +897,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848707
|
pio_addr=8804615848707
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -921,7 +913,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848771
|
pio_addr=8804615848771
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -938,7 +929,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848835
|
pio_addr=8804615848835
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -955,7 +945,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848899
|
pio_addr=8804615848899
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -972,7 +961,6 @@ fake_mem=false
|
||||||
pio_addr=8804615850617
|
pio_addr=8804615850617
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -989,7 +977,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848891
|
pio_addr=8804615848891
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1006,7 +993,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848816
|
pio_addr=8804615848816
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1023,7 +1009,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848696
|
pio_addr=8804615848696
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1040,7 +1025,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848936
|
pio_addr=8804615848936
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1057,7 +1041,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848680
|
pio_addr=8804615848680
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1074,7 +1057,6 @@ fake_mem=false
|
||||||
pio_addr=8804615848944
|
pio_addr=8804615848944
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.tsunami
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1090,7 +1072,6 @@ type=BadDevice
|
||||||
devicename=FrameBuffer
|
devicename=FrameBuffer
|
||||||
pio_addr=8804615848912
|
pio_addr=8804615848912
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.tsunami
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[22]
|
pio=system.iobus.port[22]
|
||||||
|
|
||||||
|
@ -1155,7 +1136,6 @@ type=TsunamiIO
|
||||||
frequency=976562500
|
frequency=976562500
|
||||||
pio_addr=8804615847936
|
pio_addr=8804615847936
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.tsunami
|
|
||||||
system=system
|
system=system
|
||||||
time=Thu Jan 1 00:00:00 2009
|
time=Thu Jan 1 00:00:00 2009
|
||||||
tsunami=system.tsunami
|
tsunami=system.tsunami
|
||||||
|
@ -1166,7 +1146,6 @@ pio=system.iobus.port[23]
|
||||||
type=TsunamiPChip
|
type=TsunamiPChip
|
||||||
pio_addr=8802535473152
|
pio_addr=8802535473152
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.tsunami
|
|
||||||
system=system
|
system=system
|
||||||
tsunami=system.tsunami
|
tsunami=system.tsunami
|
||||||
pio=system.iobus.port[2]
|
pio=system.iobus.port[2]
|
||||||
|
|
|
@ -1,12 +1,14 @@
|
||||||
|
Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
|
||||||
|
Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 23 2012 03:53:29
|
gem5 compiled Feb 3 2012 13:46:22
|
||||||
gem5 started Jan 23 2012 06:11:15
|
gem5 started Feb 3 2012 13:46:34
|
||||||
gem5 executing on zizzer
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3
|
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
Exiting @ tick 1858873594500 because m5_exit instruction encountered
|
Exiting @ tick 1859850554500 because m5_exit instruction encountered
|
||||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=true
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,14 +9,13 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=LinuxArmSystem
|
type=LinuxArmSystem
|
||||||
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
|
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
|
||||||
boot_cpu_frequency=500
|
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
|
||||||
boot_loader_mem=system.nvmem
|
boot_loader_mem=system.nvmem
|
||||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||||
flags_addr=268435504
|
flags_addr=268435504
|
||||||
gic_cpu_addr=520093952
|
gic_cpu_addr=520093952
|
||||||
init_param=0
|
init_param=0
|
||||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||||
load_addr_mask=268435455
|
load_addr_mask=268435455
|
||||||
machine_type=RealView_PBX
|
machine_type=RealView_PBX
|
||||||
mem_mode=timing
|
mem_mode=timing
|
||||||
|
@ -62,7 +62,7 @@ table_size=65536
|
||||||
|
|
||||||
[system.cf0.image.child]
|
[system.cf0.image.child]
|
||||||
type=RawDiskImage
|
type=RawDiskImage
|
||||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||||
read_only=true
|
read_only=true
|
||||||
|
|
||||||
[system.cpu0]
|
[system.cpu0]
|
||||||
|
@ -126,6 +126,7 @@ max_insts_all_threads=0
|
||||||
max_insts_any_thread=0
|
max_insts_any_thread=0
|
||||||
max_loads_all_threads=0
|
max_loads_all_threads=0
|
||||||
max_loads_any_thread=0
|
max_loads_any_thread=0
|
||||||
|
needsTSO=false
|
||||||
numIQEntries=64
|
numIQEntries=64
|
||||||
numPhysFloatRegs=256
|
numPhysFloatRegs=256
|
||||||
numPhysIntRegs=256
|
numPhysIntRegs=256
|
||||||
|
@ -157,6 +158,7 @@ tracer=system.cpu0.tracer
|
||||||
trapLatency=13
|
trapLatency=13
|
||||||
wbDepth=1
|
wbDepth=1
|
||||||
wbWidth=8
|
wbWidth=8
|
||||||
|
workload=
|
||||||
dcache_port=system.cpu0.dcache.cpu_side
|
dcache_port=system.cpu0.dcache.cpu_side
|
||||||
icache_port=system.cpu0.icache.cpu_side
|
icache_port=system.cpu0.icache.cpu_side
|
||||||
|
|
||||||
|
@ -580,6 +582,7 @@ max_insts_all_threads=0
|
||||||
max_insts_any_thread=0
|
max_insts_any_thread=0
|
||||||
max_loads_all_threads=0
|
max_loads_all_threads=0
|
||||||
max_loads_any_thread=0
|
max_loads_any_thread=0
|
||||||
|
needsTSO=false
|
||||||
numIQEntries=64
|
numIQEntries=64
|
||||||
numPhysFloatRegs=256
|
numPhysFloatRegs=256
|
||||||
numPhysIntRegs=256
|
numPhysIntRegs=256
|
||||||
|
@ -611,6 +614,7 @@ tracer=system.cpu1.tracer
|
||||||
trapLatency=13
|
trapLatency=13
|
||||||
wbDepth=1
|
wbDepth=1
|
||||||
wbWidth=8
|
wbWidth=8
|
||||||
|
workload=
|
||||||
dcache_port=system.cpu1.dcache.cpu_side
|
dcache_port=system.cpu1.dcache.cpu_side
|
||||||
icache_port=system.cpu1.icache.cpu_side
|
icache_port=system.cpu1.icache.cpu_side
|
||||||
|
|
||||||
|
@ -1069,7 +1073,6 @@ fake_mem=false
|
||||||
pio_addr=0
|
pio_addr=0
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.realview
|
|
||||||
ret_bad_addr=true
|
ret_bad_addr=true
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1111,7 +1114,6 @@ system=system
|
||||||
type=A9SCU
|
type=A9SCU
|
||||||
pio_addr=520093696
|
pio_addr=520093696
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.membus.port[5]
|
pio=system.membus.port[5]
|
||||||
|
|
||||||
|
@ -1121,7 +1123,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268451840
|
pio_addr=268451840
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[24]
|
pio=system.iobus.port[24]
|
||||||
|
|
||||||
|
@ -1191,7 +1192,6 @@ max_backoff_delay=10000000
|
||||||
min_backoff_delay=4000
|
min_backoff_delay=4000
|
||||||
pio_addr=268566528
|
pio_addr=268566528
|
||||||
pio_latency=10000
|
pio_latency=10000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
vnc=system.vncserver
|
vnc=system.vncserver
|
||||||
dma=system.iobus.port[6]
|
dma=system.iobus.port[6]
|
||||||
|
@ -1203,7 +1203,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268632064
|
pio_addr=268632064
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[12]
|
pio=system.iobus.port[12]
|
||||||
|
|
||||||
|
@ -1213,7 +1212,6 @@ fake_mem=true
|
||||||
pio_addr=1073741824
|
pio_addr=1073741824
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=536870912
|
pio_size=536870912
|
||||||
platform=system.realview
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1242,7 +1240,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268513280
|
pio_addr=268513280
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[19]
|
pio=system.iobus.port[19]
|
||||||
|
|
||||||
|
@ -1252,7 +1249,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268517376
|
pio_addr=268517376
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[20]
|
pio=system.iobus.port[20]
|
||||||
|
|
||||||
|
@ -1262,7 +1258,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268521472
|
pio_addr=268521472
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[21]
|
pio=system.iobus.port[21]
|
||||||
|
|
||||||
|
@ -1275,7 +1270,6 @@ int_num=52
|
||||||
is_mouse=false
|
is_mouse=false
|
||||||
pio_addr=268460032
|
pio_addr=268460032
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
vnc=system.vncserver
|
vnc=system.vncserver
|
||||||
pio=system.iobus.port[7]
|
pio=system.iobus.port[7]
|
||||||
|
@ -1289,7 +1283,6 @@ int_num=53
|
||||||
is_mouse=true
|
is_mouse=true
|
||||||
pio_addr=268464128
|
pio_addr=268464128
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
vnc=system.vncserver
|
vnc=system.vncserver
|
||||||
pio=system.iobus.port[8]
|
pio=system.iobus.port[8]
|
||||||
|
@ -1300,7 +1293,6 @@ fake_mem=false
|
||||||
pio_addr=520101888
|
pio_addr=520101888
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=4095
|
pio_size=4095
|
||||||
platform=system.realview
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1319,7 +1311,6 @@ int_num_timer=29
|
||||||
int_num_watchdog=30
|
int_num_watchdog=30
|
||||||
pio_addr=520095232
|
pio_addr=520095232
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.membus.port[6]
|
pio=system.membus.port[6]
|
||||||
|
|
||||||
|
@ -1329,7 +1320,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268455936
|
pio_addr=268455936
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[25]
|
pio=system.iobus.port[25]
|
||||||
|
|
||||||
|
@ -1338,7 +1328,6 @@ type=RealViewCtrl
|
||||||
idreg=0
|
idreg=0
|
||||||
pio_addr=268435456
|
pio_addr=268435456
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
proc_id0=201326592
|
proc_id0=201326592
|
||||||
proc_id1=201327138
|
proc_id1=201327138
|
||||||
system=system
|
system=system
|
||||||
|
@ -1350,7 +1339,6 @@ amba_id=266289
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268529664
|
pio_addr=268529664
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[26]
|
pio=system.iobus.port[26]
|
||||||
|
|
||||||
|
@ -1360,7 +1348,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268492800
|
pio_addr=268492800
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[23]
|
pio=system.iobus.port[23]
|
||||||
|
|
||||||
|
@ -1370,7 +1357,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=269357056
|
pio_addr=269357056
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[16]
|
pio=system.iobus.port[16]
|
||||||
|
|
||||||
|
@ -1380,7 +1366,6 @@ amba_id=0
|
||||||
ignore_access=true
|
ignore_access=true
|
||||||
pio_addr=268439552
|
pio_addr=268439552
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[17]
|
pio=system.iobus.port[17]
|
||||||
|
|
||||||
|
@ -1390,7 +1375,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268488704
|
pio_addr=268488704
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[22]
|
pio=system.iobus.port[22]
|
||||||
|
|
||||||
|
@ -1404,7 +1388,6 @@ int_num0=36
|
||||||
int_num1=36
|
int_num1=36
|
||||||
pio_addr=268505088
|
pio_addr=268505088
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[3]
|
pio=system.iobus.port[3]
|
||||||
|
|
||||||
|
@ -1418,7 +1401,6 @@ int_num0=37
|
||||||
int_num1=37
|
int_num1=37
|
||||||
pio_addr=268509184
|
pio_addr=268509184
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[4]
|
pio=system.iobus.port[4]
|
||||||
|
|
||||||
|
@ -1441,7 +1423,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268476416
|
pio_addr=268476416
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[13]
|
pio=system.iobus.port[13]
|
||||||
|
|
||||||
|
@ -1451,7 +1432,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268480512
|
pio_addr=268480512
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[14]
|
pio=system.iobus.port[14]
|
||||||
|
|
||||||
|
@ -1461,7 +1441,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268484608
|
pio_addr=268484608
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[15]
|
pio=system.iobus.port[15]
|
||||||
|
|
||||||
|
@ -1471,7 +1450,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268500992
|
pio_addr=268500992
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[18]
|
pio=system.iobus.port[18]
|
||||||
|
|
||||||
|
|
|
@ -13,6 +13,7 @@ warn: instruction 'mcr icimvau' unimplemented
|
||||||
warn: instruction 'mcr bpiallis' unimplemented
|
warn: instruction 'mcr bpiallis' unimplemented
|
||||||
warn: LCD dual screen mode not supported
|
warn: LCD dual screen mode not supported
|
||||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||||
|
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||||
warn: instruction 'mcr icialluis' unimplemented
|
warn: instruction 'mcr icialluis' unimplemented
|
||||||
warn: instruction 'mcr icialluis' unimplemented
|
warn: instruction 'mcr icialluis' unimplemented
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
@ -1,12 +1,14 @@
|
||||||
|
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
|
||||||
|
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 23 2012 04:21:22
|
gem5 compiled Feb 3 2012 14:00:40
|
||||||
gem5 started Jan 23 2012 09:54:17
|
gem5 started Feb 3 2012 14:01:00
|
||||||
gem5 executing on zizzer
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual
|
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||||
info: Using bootloader at address 0x80000000
|
info: Using bootloader at address 0x80000000
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
Exiting @ tick 2582494395500 because m5_exit instruction encountered
|
Exiting @ tick 2582494330500 because m5_exit instruction encountered
|
||||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=true
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,14 +9,13 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=LinuxArmSystem
|
type=LinuxArmSystem
|
||||||
children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
|
children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
|
||||||
boot_cpu_frequency=500
|
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
|
||||||
boot_loader_mem=system.nvmem
|
boot_loader_mem=system.nvmem
|
||||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||||
flags_addr=268435504
|
flags_addr=268435504
|
||||||
gic_cpu_addr=520093952
|
gic_cpu_addr=520093952
|
||||||
init_param=0
|
init_param=0
|
||||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||||
load_addr_mask=268435455
|
load_addr_mask=268435455
|
||||||
machine_type=RealView_PBX
|
machine_type=RealView_PBX
|
||||||
mem_mode=timing
|
mem_mode=timing
|
||||||
|
@ -62,7 +62,7 @@ table_size=65536
|
||||||
|
|
||||||
[system.cf0.image.child]
|
[system.cf0.image.child]
|
||||||
type=RawDiskImage
|
type=RawDiskImage
|
||||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||||
read_only=true
|
read_only=true
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
|
@ -126,6 +126,7 @@ max_insts_all_threads=0
|
||||||
max_insts_any_thread=0
|
max_insts_any_thread=0
|
||||||
max_loads_all_threads=0
|
max_loads_all_threads=0
|
||||||
max_loads_any_thread=0
|
max_loads_any_thread=0
|
||||||
|
needsTSO=false
|
||||||
numIQEntries=64
|
numIQEntries=64
|
||||||
numPhysFloatRegs=256
|
numPhysFloatRegs=256
|
||||||
numPhysIntRegs=256
|
numPhysIntRegs=256
|
||||||
|
@ -157,6 +158,7 @@ tracer=system.cpu.tracer
|
||||||
trapLatency=13
|
trapLatency=13
|
||||||
wbDepth=1
|
wbDepth=1
|
||||||
wbWidth=8
|
wbWidth=8
|
||||||
|
workload=
|
||||||
dcache_port=system.cpu.dcache.cpu_side
|
dcache_port=system.cpu.dcache.cpu_side
|
||||||
icache_port=system.cpu.icache.cpu_side
|
icache_port=system.cpu.icache.cpu_side
|
||||||
|
|
||||||
|
@ -615,7 +617,6 @@ fake_mem=false
|
||||||
pio_addr=0
|
pio_addr=0
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.realview
|
|
||||||
ret_bad_addr=true
|
ret_bad_addr=true
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -657,7 +658,6 @@ system=system
|
||||||
type=A9SCU
|
type=A9SCU
|
||||||
pio_addr=520093696
|
pio_addr=520093696
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.membus.port[5]
|
pio=system.membus.port[5]
|
||||||
|
|
||||||
|
@ -667,7 +667,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268451840
|
pio_addr=268451840
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[24]
|
pio=system.iobus.port[24]
|
||||||
|
|
||||||
|
@ -737,7 +736,6 @@ max_backoff_delay=10000000
|
||||||
min_backoff_delay=4000
|
min_backoff_delay=4000
|
||||||
pio_addr=268566528
|
pio_addr=268566528
|
||||||
pio_latency=10000
|
pio_latency=10000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
vnc=system.vncserver
|
vnc=system.vncserver
|
||||||
dma=system.iobus.port[6]
|
dma=system.iobus.port[6]
|
||||||
|
@ -749,7 +747,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268632064
|
pio_addr=268632064
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[12]
|
pio=system.iobus.port[12]
|
||||||
|
|
||||||
|
@ -759,7 +756,6 @@ fake_mem=true
|
||||||
pio_addr=1073741824
|
pio_addr=1073741824
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=536870912
|
pio_size=536870912
|
||||||
platform=system.realview
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -788,7 +784,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268513280
|
pio_addr=268513280
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[19]
|
pio=system.iobus.port[19]
|
||||||
|
|
||||||
|
@ -798,7 +793,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268517376
|
pio_addr=268517376
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[20]
|
pio=system.iobus.port[20]
|
||||||
|
|
||||||
|
@ -808,7 +802,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268521472
|
pio_addr=268521472
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[21]
|
pio=system.iobus.port[21]
|
||||||
|
|
||||||
|
@ -821,7 +814,6 @@ int_num=52
|
||||||
is_mouse=false
|
is_mouse=false
|
||||||
pio_addr=268460032
|
pio_addr=268460032
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
vnc=system.vncserver
|
vnc=system.vncserver
|
||||||
pio=system.iobus.port[7]
|
pio=system.iobus.port[7]
|
||||||
|
@ -835,7 +827,6 @@ int_num=53
|
||||||
is_mouse=true
|
is_mouse=true
|
||||||
pio_addr=268464128
|
pio_addr=268464128
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
vnc=system.vncserver
|
vnc=system.vncserver
|
||||||
pio=system.iobus.port[8]
|
pio=system.iobus.port[8]
|
||||||
|
@ -846,7 +837,6 @@ fake_mem=false
|
||||||
pio_addr=520101888
|
pio_addr=520101888
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=4095
|
pio_size=4095
|
||||||
platform=system.realview
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -865,7 +855,6 @@ int_num_timer=29
|
||||||
int_num_watchdog=30
|
int_num_watchdog=30
|
||||||
pio_addr=520095232
|
pio_addr=520095232
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.membus.port[6]
|
pio=system.membus.port[6]
|
||||||
|
|
||||||
|
@ -875,7 +864,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268455936
|
pio_addr=268455936
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[25]
|
pio=system.iobus.port[25]
|
||||||
|
|
||||||
|
@ -884,7 +872,6 @@ type=RealViewCtrl
|
||||||
idreg=0
|
idreg=0
|
||||||
pio_addr=268435456
|
pio_addr=268435456
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
proc_id0=201326592
|
proc_id0=201326592
|
||||||
proc_id1=201327138
|
proc_id1=201327138
|
||||||
system=system
|
system=system
|
||||||
|
@ -896,7 +883,6 @@ amba_id=266289
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268529664
|
pio_addr=268529664
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[26]
|
pio=system.iobus.port[26]
|
||||||
|
|
||||||
|
@ -906,7 +892,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268492800
|
pio_addr=268492800
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[23]
|
pio=system.iobus.port[23]
|
||||||
|
|
||||||
|
@ -916,7 +901,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=269357056
|
pio_addr=269357056
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[16]
|
pio=system.iobus.port[16]
|
||||||
|
|
||||||
|
@ -926,7 +910,6 @@ amba_id=0
|
||||||
ignore_access=true
|
ignore_access=true
|
||||||
pio_addr=268439552
|
pio_addr=268439552
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[17]
|
pio=system.iobus.port[17]
|
||||||
|
|
||||||
|
@ -936,7 +919,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268488704
|
pio_addr=268488704
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[22]
|
pio=system.iobus.port[22]
|
||||||
|
|
||||||
|
@ -950,7 +932,6 @@ int_num0=36
|
||||||
int_num1=36
|
int_num1=36
|
||||||
pio_addr=268505088
|
pio_addr=268505088
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[3]
|
pio=system.iobus.port[3]
|
||||||
|
|
||||||
|
@ -964,7 +945,6 @@ int_num0=37
|
||||||
int_num1=37
|
int_num1=37
|
||||||
pio_addr=268509184
|
pio_addr=268509184
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[4]
|
pio=system.iobus.port[4]
|
||||||
|
|
||||||
|
@ -987,7 +967,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268476416
|
pio_addr=268476416
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[13]
|
pio=system.iobus.port[13]
|
||||||
|
|
||||||
|
@ -997,7 +976,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268480512
|
pio_addr=268480512
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[14]
|
pio=system.iobus.port[14]
|
||||||
|
|
||||||
|
@ -1007,7 +985,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268484608
|
pio_addr=268484608
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[15]
|
pio=system.iobus.port[15]
|
||||||
|
|
||||||
|
@ -1017,7 +994,6 @@ amba_id=0
|
||||||
ignore_access=false
|
ignore_access=false
|
||||||
pio_addr=268500992
|
pio_addr=268500992
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.realview
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[18]
|
pio=system.iobus.port[18]
|
||||||
|
|
||||||
|
|
|
@ -1,12 +1,14 @@
|
||||||
|
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
|
||||||
|
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 23 2012 04:21:22
|
gem5 compiled Feb 3 2012 14:00:40
|
||||||
gem5 started Jan 23 2012 09:54:06
|
gem5 started Feb 3 2012 14:01:01
|
||||||
gem5 executing on zizzer
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3
|
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||||
info: Using bootloader at address 0x80000000
|
info: Using bootloader at address 0x80000000
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
Exiting @ tick 2503566110500 because m5_exit instruction encountered
|
Exiting @ tick 2503580880500 because m5_exit instruction encountered
|
||||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=true
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -9,7 +10,6 @@ time_sync_spin_threshold=100000000
|
||||||
type=LinuxX86System
|
type=LinuxX86System
|
||||||
children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
|
children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
|
||||||
acpi_description_table_pointer=system.acpi_description_table_pointer
|
acpi_description_table_pointer=system.acpi_description_table_pointer
|
||||||
boot_cpu_frequency=500
|
|
||||||
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||||
e820_table=system.e820_table
|
e820_table=system.e820_table
|
||||||
init_param=0
|
init_param=0
|
||||||
|
@ -154,6 +154,7 @@ tracer=system.cpu.tracer
|
||||||
trapLatency=13
|
trapLatency=13
|
||||||
wbDepth=1
|
wbDepth=1
|
||||||
wbWidth=8
|
wbWidth=8
|
||||||
|
workload=
|
||||||
dcache_port=system.cpu.dcache.cpu_side
|
dcache_port=system.cpu.dcache.cpu_side
|
||||||
icache_port=system.cpu.icache.cpu_side
|
icache_port=system.cpu.icache.cpu_side
|
||||||
|
|
||||||
|
@ -532,7 +533,6 @@ type=X86LocalApic
|
||||||
int_latency=1000
|
int_latency=1000
|
||||||
pio_addr=2305843009213693952
|
pio_addr=2305843009213693952
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.pc
|
|
||||||
system=system
|
system=system
|
||||||
int_port=system.membus.port[7]
|
int_port=system.membus.port[7]
|
||||||
pio=system.membus.port[6]
|
pio=system.membus.port[6]
|
||||||
|
@ -1050,7 +1050,6 @@ fake_mem=false
|
||||||
pio_addr=0
|
pio_addr=0
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.pc
|
|
||||||
ret_bad_addr=true
|
ret_bad_addr=true
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1073,7 +1072,6 @@ fake_mem=false
|
||||||
pio_addr=9223372036854779128
|
pio_addr=9223372036854779128
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.pc
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1114,7 +1112,6 @@ fake_mem=false
|
||||||
pio_addr=9223372036854776568
|
pio_addr=9223372036854776568
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.pc
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1131,7 +1128,6 @@ fake_mem=false
|
||||||
pio_addr=9223372036854776808
|
pio_addr=9223372036854776808
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.pc
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1148,7 +1144,6 @@ fake_mem=false
|
||||||
pio_addr=9223372036854776552
|
pio_addr=9223372036854776552
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=8
|
pio_size=8
|
||||||
platform=system.pc
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1165,7 +1160,6 @@ fake_mem=false
|
||||||
pio_addr=9223372036854776818
|
pio_addr=9223372036854776818
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=2
|
pio_size=2
|
||||||
platform=system.pc
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1182,7 +1176,6 @@ fake_mem=false
|
||||||
pio_addr=9223372036854775936
|
pio_addr=9223372036854775936
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
pio_size=1
|
pio_size=1
|
||||||
platform=system.pc
|
|
||||||
ret_bad_addr=false
|
ret_bad_addr=false
|
||||||
ret_data16=65535
|
ret_data16=65535
|
||||||
ret_data32=4294967295
|
ret_data32=4294967295
|
||||||
|
@ -1222,7 +1215,6 @@ children=int_pin
|
||||||
int_pin=system.pc.south_bridge.cmos.int_pin
|
int_pin=system.pc.south_bridge.cmos.int_pin
|
||||||
pio_addr=9223372036854775920
|
pio_addr=9223372036854775920
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.pc
|
|
||||||
system=system
|
system=system
|
||||||
time=Sun Jan 1 00:00:00 2012
|
time=Sun Jan 1 00:00:00 2012
|
||||||
pio=system.iobus.port[2]
|
pio=system.iobus.port[2]
|
||||||
|
@ -1234,7 +1226,6 @@ type=X86IntSourcePin
|
||||||
type=I8237
|
type=I8237
|
||||||
pio_addr=9223372036854775808
|
pio_addr=9223372036854775808
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.pc
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[3]
|
pio=system.iobus.port[3]
|
||||||
|
|
||||||
|
@ -1419,7 +1410,6 @@ external_int_pic=system.pc.south_bridge.pic1
|
||||||
int_latency=1000
|
int_latency=1000
|
||||||
pio_addr=4273995776
|
pio_addr=4273995776
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.pc
|
|
||||||
system=system
|
system=system
|
||||||
int_port=system.iobus.port[13]
|
int_port=system.iobus.port[13]
|
||||||
pio=system.iobus.port[12]
|
pio=system.iobus.port[12]
|
||||||
|
@ -1433,7 +1423,6 @@ keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
|
||||||
mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
|
mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
|
||||||
pio_addr=0
|
pio_addr=0
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.pc
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[7]
|
pio=system.iobus.port[7]
|
||||||
|
|
||||||
|
@ -1450,7 +1439,6 @@ mode=I8259Master
|
||||||
output=system.pc.south_bridge.pic1.output
|
output=system.pc.south_bridge.pic1.output
|
||||||
pio_addr=9223372036854775840
|
pio_addr=9223372036854775840
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.pc
|
|
||||||
slave=system.pc.south_bridge.pic2
|
slave=system.pc.south_bridge.pic2
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[8]
|
pio=system.iobus.port[8]
|
||||||
|
@ -1465,7 +1453,6 @@ mode=I8259Slave
|
||||||
output=system.pc.south_bridge.pic2.output
|
output=system.pc.south_bridge.pic2.output
|
||||||
pio_addr=9223372036854775968
|
pio_addr=9223372036854775968
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.pc
|
|
||||||
slave=Null
|
slave=Null
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[9]
|
pio=system.iobus.port[9]
|
||||||
|
@ -1479,7 +1466,6 @@ children=int_pin
|
||||||
int_pin=system.pc.south_bridge.pit.int_pin
|
int_pin=system.pc.south_bridge.pit.int_pin
|
||||||
pio_addr=9223372036854775872
|
pio_addr=9223372036854775872
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.pc
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[10]
|
pio=system.iobus.port[10]
|
||||||
|
|
||||||
|
@ -1491,7 +1477,6 @@ type=PcSpeaker
|
||||||
i8254=system.pc.south_bridge.pit
|
i8254=system.pc.south_bridge.pit
|
||||||
pio_addr=9223372036854775905
|
pio_addr=9223372036854775905
|
||||||
pio_latency=1000
|
pio_latency=1000
|
||||||
platform=system.pc
|
|
||||||
system=system
|
system=system
|
||||||
pio=system.iobus.port[11]
|
pio=system.iobus.port[11]
|
||||||
|
|
||||||
|
|
|
@ -1,15 +1,15 @@
|
||||||
Redirecting stdout to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simout
|
Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
|
||||||
Redirecting stderr to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simerr
|
Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 28 2012 16:24:13
|
gem5 compiled Feb 3 2012 12:36:19
|
||||||
gem5 started Jan 28 2012 16:29:18
|
gem5 started Feb 3 2012 12:37:07
|
||||||
gem5 executing on ribera.cs.wisc.edu
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing
|
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
|
||||||
warning: add_child('terminal'): child 'terminal' already has parent
|
warning: add_child('terminal'): child 'terminal' already has parent
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
Exiting @ tick 5164643202500 because m5_exit instruction encountered
|
Exiting @ tick 5163317092500 because m5_exit instruction encountered
|
||||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=false
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=System
|
type=System
|
||||||
children=cpu membus physmem
|
children=cpu membus physmem
|
||||||
|
boot_osflags=a
|
||||||
|
init_param=0
|
||||||
|
kernel=
|
||||||
|
load_addr_mask=1099511627775
|
||||||
mem_mode=atomic
|
mem_mode=atomic
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
|
readfile=
|
||||||
|
symbolfile=
|
||||||
work_begin_ckpt_count=0
|
work_begin_ckpt_count=0
|
||||||
work_begin_cpu_id_exit=-1
|
work_begin_cpu_id_exit=-1
|
||||||
work_begin_exit_count=0
|
work_begin_exit_count=0
|
||||||
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
type=DerivO3CPU
|
type=DerivO3CPU
|
||||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||||
BTBEntries=4096
|
BTBEntries=4096
|
||||||
BTBTagSize=16
|
BTBTagSize=16
|
||||||
LFSTSize=1024
|
LFSTSize=1024
|
||||||
|
@ -52,6 +59,7 @@ decodeWidth=8
|
||||||
defer_registration=false
|
defer_registration=false
|
||||||
dispatchWidth=8
|
dispatchWidth=8
|
||||||
do_checkpoint_insts=true
|
do_checkpoint_insts=true
|
||||||
|
do_quiesce=true
|
||||||
do_statistics_insts=true
|
do_statistics_insts=true
|
||||||
dtb=system.cpu.dtb
|
dtb=system.cpu.dtb
|
||||||
fetchToDecodeDelay=1
|
fetchToDecodeDelay=1
|
||||||
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
||||||
iewToFetchDelay=1
|
iewToFetchDelay=1
|
||||||
iewToRenameDelay=1
|
iewToRenameDelay=1
|
||||||
instShiftAmt=2
|
instShiftAmt=2
|
||||||
|
interrupts=system.cpu.interrupts
|
||||||
issueToExecuteDelay=1
|
issueToExecuteDelay=1
|
||||||
issueWidth=8
|
issueWidth=8
|
||||||
itb=system.cpu.itb
|
itb=system.cpu.itb
|
||||||
|
@ -80,6 +89,7 @@ max_insts_all_threads=0
|
||||||
max_insts_any_thread=0
|
max_insts_any_thread=0
|
||||||
max_loads_all_threads=0
|
max_loads_all_threads=0
|
||||||
max_loads_any_thread=0
|
max_loads_any_thread=0
|
||||||
|
needsTSO=false
|
||||||
numIQEntries=64
|
numIQEntries=64
|
||||||
numPhysFloatRegs=256
|
numPhysFloatRegs=256
|
||||||
numPhysIntRegs=256
|
numPhysIntRegs=256
|
||||||
|
@ -88,6 +98,7 @@ numRobs=1
|
||||||
numThreads=1
|
numThreads=1
|
||||||
phase=0
|
phase=0
|
||||||
predType=tournament
|
predType=tournament
|
||||||
|
profile=0
|
||||||
progress_interval=0
|
progress_interval=0
|
||||||
renameToDecodeDelay=1
|
renameToDecodeDelay=1
|
||||||
renameToFetchDelay=1
|
renameToFetchDelay=1
|
||||||
|
@ -148,7 +159,16 @@ mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
[system.cpu.dtb]
|
[system.cpu.dtb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.dtb.walker
|
||||||
|
|
||||||
|
[system.cpu.dtb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[3]
|
||||||
|
|
||||||
[system.cpu.fuPool]
|
[system.cpu.fuPool]
|
||||||
type=FUPool
|
type=FUPool
|
||||||
|
@ -445,9 +465,21 @@ write_buffers=8
|
||||||
cpu_side=system.cpu.icache_port
|
cpu_side=system.cpu.icache_port
|
||||||
mem_side=system.cpu.toL2Bus.port[0]
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.interrupts]
|
||||||
|
type=ArmInterrupts
|
||||||
|
|
||||||
[system.cpu.itb]
|
[system.cpu.itb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.itb.walker
|
||||||
|
|
||||||
|
[system.cpu.itb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[2]
|
||||||
|
|
||||||
[system.cpu.l2cache]
|
[system.cpu.l2cache]
|
||||||
type=BaseCache
|
type=BaseCache
|
||||||
|
@ -478,7 +510,7 @@ tgts_per_mshr=5
|
||||||
trace_addr=0
|
trace_addr=0
|
||||||
two_queue=false
|
two_queue=false
|
||||||
write_buffers=8
|
write_buffers=8
|
||||||
cpu_side=system.cpu.toL2Bus.port[2]
|
cpu_side=system.cpu.toL2Bus.port[4]
|
||||||
mem_side=system.membus.port[2]
|
mem_side=system.membus.port[2]
|
||||||
|
|
||||||
[system.cpu.toL2Bus]
|
[system.cpu.toL2Bus]
|
||||||
|
@ -489,7 +521,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
[system.cpu.tracer]
|
[system.cpu.tracer]
|
||||||
type=ExeTracer
|
type=ExeTracer
|
||||||
|
@ -497,12 +529,12 @@ type=ExeTracer
|
||||||
[system.cpu.workload]
|
[system.cpu.workload]
|
||||||
type=LiveProcess
|
type=LiveProcess
|
||||||
cmd=gzip input.log 1
|
cmd=gzip input.log 1
|
||||||
cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
|
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
|
||||||
egid=100
|
egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
|
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
|
||||||
gid=100
|
gid=100
|
||||||
input=cin
|
input=cin
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
|
|
|
@ -1,10 +1,12 @@
|
||||||
|
Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simout
|
||||||
|
Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 23 2012 04:16:21
|
gem5 compiled Feb 10 2012 00:18:03
|
||||||
gem5 started Jan 23 2012 08:31:06
|
gem5 started Feb 10 2012 00:18:23
|
||||||
gem5 executing on zizzer
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
|
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
spec_init
|
spec_init
|
||||||
|
@ -38,4 +40,4 @@ Uncompressing Data
|
||||||
Uncompressed data 1048576 bytes in length
|
Uncompressed data 1048576 bytes in length
|
||||||
Uncompressed data compared correctly
|
Uncompressed data compared correctly
|
||||||
Tested 1MB buffer: OK!
|
Tested 1MB buffer: OK!
|
||||||
Exiting @ tick 177098873000 because target called exit()
|
Exiting @ tick 177116942500 because target called exit()
|
||||||
|
|
|
@ -1,24 +1,24 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.177099 # Number of seconds simulated
|
sim_seconds 0.177117 # Number of seconds simulated
|
||||||
sim_ticks 177098873000 # Number of ticks simulated
|
sim_ticks 177116942500 # Number of ticks simulated
|
||||||
final_tick 177098873000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 177116942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 154897 # Simulator instruction rate (inst/s)
|
host_inst_rate 89657 # Simulator instruction rate (inst/s)
|
||||||
host_tick_rate 45541130 # Simulator tick rate (ticks/s)
|
host_tick_rate 26362655 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 220436 # Number of bytes of host memory used
|
host_mem_usage 256136 # Number of bytes of host memory used
|
||||||
host_seconds 3888.77 # Real time elapsed on the host
|
host_seconds 6718.48 # Real time elapsed on the host
|
||||||
sim_insts 602359805 # Number of instructions simulated
|
sim_insts 602359810 # Number of instructions simulated
|
||||||
system.physmem.bytes_read 5833856 # Number of bytes read from this memory
|
system.physmem.bytes_read 5833792 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read 46976 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read 46976 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written 3720192 # Number of bytes written to this memory
|
system.physmem.bytes_written 3720320 # Number of bytes written to this memory
|
||||||
system.physmem.num_reads 91154 # Number of read requests responded to by this memory
|
system.physmem.num_reads 91153 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes 58128 # Number of write requests responded to by this memory
|
system.physmem.num_writes 58130 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||||
system.physmem.bw_read 32941237 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read 32937515 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read 265253 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read 265226 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write 21006300 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write 21004879 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total 53947537 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total 53942395 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||||
|
@ -62,141 +62,141 @@ system.cpu.itb.hits 0 # DT
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||||
system.cpu.numCycles 354197747 # number of cpu cycles simulated
|
system.cpu.numCycles 354233886 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.BPredUnit.lookups 91137531 # Number of BP lookups
|
system.cpu.BPredUnit.lookups 91144697 # Number of BP lookups
|
||||||
system.cpu.BPredUnit.condPredicted 84224367 # Number of conditional branches predicted
|
system.cpu.BPredUnit.condPredicted 84232652 # Number of conditional branches predicted
|
||||||
system.cpu.BPredUnit.condIncorrect 4001637 # Number of conditional branches incorrect
|
system.cpu.BPredUnit.condIncorrect 4003225 # Number of conditional branches incorrect
|
||||||
system.cpu.BPredUnit.BTBLookups 86284566 # Number of BTB lookups
|
system.cpu.BPredUnit.BTBLookups 86347481 # Number of BTB lookups
|
||||||
system.cpu.BPredUnit.BTBHits 80014553 # Number of BTB hits
|
system.cpu.BPredUnit.BTBHits 80064419 # Number of BTB hits
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.BPredUnit.usedRAS 1704311 # Number of times the RAS was used to get a target.
|
system.cpu.BPredUnit.usedRAS 1704141 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.BPredUnit.RASInCorrect 1605 # Number of incorrect RAS predictions.
|
system.cpu.BPredUnit.RASInCorrect 1603 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 76786839 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 76798037 # Number of cycles fetch is stalled on an Icache miss
|
||||||
system.cpu.fetch.Insts 703787736 # Number of instructions fetch has processed
|
system.cpu.fetch.Insts 703840817 # Number of instructions fetch has processed
|
||||||
system.cpu.fetch.Branches 91137531 # Number of branches that fetch encountered
|
system.cpu.fetch.Branches 91144697 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 81718864 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 81768560 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.Cycles 159146597 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.fetch.Cycles 159197395 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
system.cpu.fetch.SquashCycles 18455506 # Number of cycles fetch has spent squashing
|
system.cpu.fetch.SquashCycles 18458844 # Number of cycles fetch has spent squashing
|
||||||
system.cpu.fetch.BlockedCycles 103039518 # Number of cycles fetch has spent blocked
|
system.cpu.fetch.BlockedCycles 103018501 # Number of cycles fetch has spent blocked
|
||||||
system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
system.cpu.fetch.PendingTrapStallCycles 620 # Number of stall cycles due to pending traps
|
system.cpu.fetch.PendingTrapStallCycles 596 # Number of stall cycles due to pending traps
|
||||||
system.cpu.fetch.CacheLines 74412736 # Number of cache lines fetched
|
system.cpu.fetch.CacheLines 74422546 # Number of cache lines fetched
|
||||||
system.cpu.fetch.IcacheSquashes 1337820 # Number of outstanding Icache misses that were squashed
|
system.cpu.fetch.IcacheSquashes 1338162 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 353350911 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 353393528 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.128080 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.127927 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 2.980798 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 2.980484 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::0 194204457 54.96% 54.96% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::0 194196282 54.95% 54.95% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::1 25620928 7.25% 62.21% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::1 25625707 7.25% 62.20% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::2 19248235 5.45% 67.66% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::2 19294200 5.46% 67.66% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::3 24404617 6.91% 74.57% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::3 24432014 6.91% 74.58% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::4 11778472 3.33% 77.90% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::4 11774546 3.33% 77.91% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::5 13409998 3.80% 81.69% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::5 13391437 3.79% 81.70% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::6 4602257 1.30% 83.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::6 4604134 1.30% 83.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::7 7805373 2.21% 85.21% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::7 7796226 2.21% 85.21% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::8 52276574 14.79% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::8 52278982 14.79% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 353350911 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 353393528 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.branchRate 0.257307 # Number of branch fetches per cycle
|
system.cpu.fetch.branchRate 0.257301 # Number of branch fetches per cycle
|
||||||
system.cpu.fetch.rate 1.986991 # Number of inst fetches per cycle
|
system.cpu.fetch.rate 1.986938 # Number of inst fetches per cycle
|
||||||
system.cpu.decode.IdleCycles 98877750 # Number of cycles decode is idle
|
system.cpu.decode.IdleCycles 98941962 # Number of cycles decode is idle
|
||||||
system.cpu.decode.BlockedCycles 83515155 # Number of cycles decode is blocked
|
system.cpu.decode.BlockedCycles 83442113 # Number of cycles decode is blocked
|
||||||
system.cpu.decode.RunCycles 137076269 # Number of cycles decode is running
|
system.cpu.decode.RunCycles 137180071 # Number of cycles decode is running
|
||||||
system.cpu.decode.UnblockCycles 19506954 # Number of cycles decode is unblocking
|
system.cpu.decode.UnblockCycles 19452898 # Number of cycles decode is unblocking
|
||||||
system.cpu.decode.SquashCycles 14374783 # Number of cycles decode is squashing
|
system.cpu.decode.SquashCycles 14376484 # Number of cycles decode is squashing
|
||||||
system.cpu.decode.BranchResolved 6301291 # Number of times decode resolved a branch
|
system.cpu.decode.BranchResolved 6300700 # Number of times decode resolved a branch
|
||||||
system.cpu.decode.BranchMispred 2551 # Number of times decode detected a branch misprediction
|
system.cpu.decode.BranchMispred 2518 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.decode.DecodedInsts 740114896 # Number of instructions handled by decode
|
system.cpu.decode.DecodedInsts 740147617 # Number of instructions handled by decode
|
||||||
system.cpu.decode.SquashedInsts 7230 # Number of squashed instructions handled by decode
|
system.cpu.decode.SquashedInsts 7037 # Number of squashed instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 14374783 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 14376484 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 111843103 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 111904204 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 9537973 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 9631562 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 119731 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 118839 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 143514381 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 143566748 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 73960940 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 73795691 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 727174418 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 727217623 # Number of instructions processed by rename
|
||||||
system.cpu.rename.ROBFullEvents 286 # Number of times rename has blocked due to ROB full
|
system.cpu.rename.ROBFullEvents 278 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.rename.IQFullEvents 59845789 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 59684680 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LSQFullEvents 10289393 # Number of times rename has blocked due to LSQ full
|
system.cpu.rename.LSQFullEvents 10267337 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.rename.FullRegisterEvents 334 # Number of times there has been no free registers
|
system.cpu.rename.FullRegisterEvents 352 # Number of times there has been no free registers
|
||||||
system.cpu.rename.RenamedOperands 752889395 # Number of destination operands rename has renamed
|
system.cpu.rename.RenamedOperands 752950298 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenameLookups 3380302991 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenameLookups 3380504235 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.int_rename_lookups 3380302863 # Number of integer rename lookups
|
system.cpu.rename.int_rename_lookups 3380504107 # Number of integer rename lookups
|
||||||
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
|
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
|
||||||
system.cpu.rename.CommittedMaps 627417394 # Number of HB maps that are committed
|
system.cpu.rename.CommittedMaps 627417402 # Number of HB maps that are committed
|
||||||
system.cpu.rename.UndoneMaps 125472001 # Number of HB maps that are undone due to squashing
|
system.cpu.rename.UndoneMaps 125532896 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.rename.serializingInsts 13297 # count of serializing insts renamed
|
system.cpu.rename.serializingInsts 13135 # count of serializing insts renamed
|
||||||
system.cpu.rename.tempSerializingInsts 13294 # count of temporary serializing insts renamed
|
system.cpu.rename.tempSerializingInsts 13128 # count of temporary serializing insts renamed
|
||||||
system.cpu.rename.skidInsts 132095966 # count of insts added to the skid buffer
|
system.cpu.rename.skidInsts 131736703 # count of insts added to the skid buffer
|
||||||
system.cpu.memDep0.insertedLoads 179744866 # Number of loads inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedLoads 179759563 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.insertedStores 82855502 # Number of stores inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedStores 82851365 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.conflictingLoads 19180586 # Number of conflicting loads.
|
system.cpu.memDep0.conflictingLoads 19142240 # Number of conflicting loads.
|
||||||
system.cpu.memDep0.conflictingStores 24795671 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 24648771 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 702443112 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 702464419 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 9504 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 9443 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 663038146 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 663065354 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 743101 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 737309 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 99536301 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 99563138 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 237037166 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 237077273 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 3158 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.iqSquashedNonSpecRemoved 3096 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.iq.issued_per_cycle::samples 353350911 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::samples 353393528 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.876430 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 1.876280 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.733239 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.733355 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 85428360 24.18% 24.18% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 85420653 24.17% 24.17% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 90441308 25.60% 49.77% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 90592891 25.64% 49.81% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 76153703 21.55% 71.32% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 76061550 21.52% 71.33% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 42544702 12.04% 83.36% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 42517322 12.03% 83.36% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 25577763 7.24% 90.60% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 25489615 7.21% 90.57% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::5 18033700 5.10% 95.71% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::5 18140901 5.13% 95.71% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::6 7283699 2.06% 97.77% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::6 7279964 2.06% 97.77% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::7 6627828 1.88% 99.64% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::7 6670408 1.89% 99.65% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::8 1259848 0.36% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::8 1220224 0.35% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::total 353350911 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::total 353393528 # Number of insts issued each cycle
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntAlu 202982 4.88% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntAlu 202199 4.87% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntMult 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.88% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.87% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemRead 2990868 71.85% 76.73% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemRead 2984693 71.84% 76.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemWrite 968637 23.27% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemWrite 967527 23.29% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 412586864 62.23% 62.23% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 412589272 62.22% 62.22% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 6565 0.00% 62.23% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 6572 0.00% 62.23% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.23% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.23% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued
|
||||||
|
@ -224,137 +224,137 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.23% # Ty
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.23% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.23% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.23% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.23% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.23% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.23% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 172485012 26.01% 88.24% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 172499638 26.02% 88.24% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 77959702 11.76% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 77969869 11.76% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 663038146 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 663065354 # Type of FU issued
|
||||||
system.cpu.iq.rate 1.871943 # Inst issue rate
|
system.cpu.iq.rate 1.871829 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 4162487 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 4154419 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.006278 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.006265 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 1684332755 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 1684415928 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 802000478 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 802048612 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 650204091 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 650214601 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 667200613 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 667219753 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 29662170 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 29667951 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 30792271 # Number of loads squashed
|
system.cpu.iew.lsq.thread0.squashedLoads 30806967 # Number of loads squashed
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 224606 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iew.lsq.thread0.ignoredResponses 225012 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 11800 # Number of memory ordering violations
|
system.cpu.iew.lsq.thread0.memOrderViolation 11842 # Number of memory ordering violations
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 12634488 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 12630350 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 13695 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 13680 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 12640 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 12577 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 14374783 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 14376484 # Number of cycles IEW is squashing
|
||||||
system.cpu.iew.iewBlockCycles 826341 # Number of cycles IEW is blocking
|
system.cpu.iew.iewBlockCycles 831826 # Number of cycles IEW is blocking
|
||||||
system.cpu.iew.iewUnblockCycles 58736 # Number of cycles IEW is unblocking
|
system.cpu.iew.iewUnblockCycles 58719 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iew.iewDispatchedInsts 702522112 # Number of instructions dispatched to IQ
|
system.cpu.iew.iewDispatchedInsts 702543187 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iew.iewDispSquashedInsts 1853549 # Number of squashed instructions skipped by dispatch
|
system.cpu.iew.iewDispSquashedInsts 1852399 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iew.iewDispLoadInsts 179744866 # Number of dispatched load instructions
|
system.cpu.iew.iewDispLoadInsts 179759563 # Number of dispatched load instructions
|
||||||
system.cpu.iew.iewDispStoreInsts 82855502 # Number of dispatched store instructions
|
system.cpu.iew.iewDispStoreInsts 82851365 # Number of dispatched store instructions
|
||||||
system.cpu.iew.iewDispNonSpecInsts 8175 # Number of dispatched non-speculative instructions
|
system.cpu.iew.iewDispNonSpecInsts 8113 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.iew.iewIQFullEvents 13020 # Number of times the IQ has become full, causing a stall
|
system.cpu.iew.iewIQFullEvents 13094 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.iew.iewLSQFullEvents 5275 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iew.iewLSQFullEvents 5271 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.iew.memOrderViolationEvents 11800 # Number of memory order violations
|
system.cpu.iew.memOrderViolationEvents 11842 # Number of memory order violations
|
||||||
system.cpu.iew.predictedTakenIncorrect 4156328 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 4161334 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 497844 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 494337 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 4654172 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 4655671 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 656067860 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 656082264 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 169121282 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 169130146 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 6970286 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 6983090 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 69496 # number of nop insts executed
|
system.cpu.iew.exec_nop 69325 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 245806937 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 245820033 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 76463124 # Number of branches executed
|
system.cpu.iew.exec_branches 76462484 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 76685655 # Number of stores executed
|
system.cpu.iew.exec_stores 76689887 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 1.852264 # Inst execution rate
|
system.cpu.iew.exec_rate 1.852116 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 652210228 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 652222843 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 650204107 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 650214617 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 423315850 # num instructions producing a value
|
system.cpu.iew.wb_producers 423345319 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 657380921 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 657402766 # num instructions consuming a value
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.iew.wb_rate 1.835709 # insts written-back per cycle
|
system.cpu.iew.wb_rate 1.835552 # insts written-back per cycle
|
||||||
system.cpu.iew.wb_fanout 0.643943 # average fanout of values written-back
|
system.cpu.iew.wb_fanout 0.643966 # average fanout of values written-back
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.commit.commitCommittedInsts 602359856 # The number of committed instructions
|
system.cpu.commit.commitCommittedInsts 602359861 # The number of committed instructions
|
||||||
system.cpu.commit.commitSquashedInsts 100172226 # The number of squashed insts skipped by commit
|
system.cpu.commit.commitSquashedInsts 100193357 # The number of squashed insts skipped by commit
|
||||||
system.cpu.commit.commitNonSpecStalls 6346 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu.commit.commitNonSpecStalls 6347 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.commit.branchMispredicts 4060978 # The number of times a branch was mispredicted
|
system.cpu.commit.branchMispredicts 4062580 # The number of times a branch was mispredicted
|
||||||
system.cpu.commit.committed_per_cycle::samples 338976129 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::samples 339017045 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.776998 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::mean 1.776783 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::stdev 2.152747 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::stdev 2.152670 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::0 108154848 31.91% 31.91% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::0 108187576 31.91% 31.91% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::1 106518775 31.42% 63.33% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::1 106522126 31.42% 63.33% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::2 49308103 14.55% 77.88% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::2 49316522 14.55% 77.88% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::3 9862304 2.91% 80.79% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::3 9859363 2.91% 80.79% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::4 23329668 6.88% 87.67% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::4 23336266 6.88% 87.67% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::5 14306268 4.22% 91.89% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::5 14305882 4.22% 91.89% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::6 7919036 2.34% 94.22% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::6 7916477 2.34% 94.23% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::7 1343281 0.40% 94.62% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::7 1329398 0.39% 94.62% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::8 18233846 5.38% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::8 18243435 5.38% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::total 338976129 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::total 339017045 # Number of insts commited each cycle
|
||||||
system.cpu.commit.count 602359856 # Number of instructions committed
|
system.cpu.commit.count 602359861 # Number of instructions committed
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.commit.refs 219173609 # Number of memory references committed
|
system.cpu.commit.refs 219173611 # Number of memory references committed
|
||||||
system.cpu.commit.loads 148952595 # Number of loads committed
|
system.cpu.commit.loads 148952596 # Number of loads committed
|
||||||
system.cpu.commit.membars 1328 # Number of memory barriers committed
|
system.cpu.commit.membars 1328 # Number of memory barriers committed
|
||||||
system.cpu.commit.branches 70828602 # Number of branches committed
|
system.cpu.commit.branches 70828603 # Number of branches committed
|
||||||
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
||||||
system.cpu.commit.int_insts 533522643 # Number of committed integer instructions.
|
system.cpu.commit.int_insts 533522647 # Number of committed integer instructions.
|
||||||
system.cpu.commit.function_calls 997573 # Number of function calls committed.
|
system.cpu.commit.function_calls 997573 # Number of function calls committed.
|
||||||
system.cpu.commit.bw_lim_events 18233846 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 18243435 # number cycles where commit BW limit reached
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.rob.rob_reads 1023273753 # The number of ROB reads
|
system.cpu.rob.rob_reads 1023326216 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 1419480895 # The number of ROB writes
|
system.cpu.rob.rob_writes 1419524916 # The number of ROB writes
|
||||||
system.cpu.timesIdled 37084 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 37353 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 846836 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 840358 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu.committedInsts 602359805 # Number of Instructions Simulated
|
system.cpu.committedInsts 602359810 # Number of Instructions Simulated
|
||||||
system.cpu.committedInsts_total 602359805 # Number of Instructions Simulated
|
system.cpu.committedInsts_total 602359810 # Number of Instructions Simulated
|
||||||
system.cpu.cpi 0.588017 # CPI: Cycles Per Instruction
|
system.cpu.cpi 0.588077 # CPI: Cycles Per Instruction
|
||||||
system.cpu.cpi_total 0.588017 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 0.588077 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 1.700631 # IPC: Instructions Per Cycle
|
system.cpu.ipc 1.700458 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 1.700631 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 1.700458 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 3275893571 # number of integer regfile reads
|
system.cpu.int_regfile_reads 3275977261 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 675997918 # number of integer regfile writes
|
system.cpu.int_regfile_writes 676006750 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||||
system.cpu.misc_regfile_reads 943643021 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 943708295 # number of misc regfile reads
|
||||||
system.cpu.misc_regfile_writes 2658 # number of misc regfile writes
|
system.cpu.misc_regfile_writes 2660 # number of misc regfile writes
|
||||||
system.cpu.icache.replacements 41 # number of replacements
|
system.cpu.icache.replacements 41 # number of replacements
|
||||||
system.cpu.icache.tagsinuse 657.503073 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 657.275674 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 74411745 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 74421550 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.sampled_refs 766 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 765 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.avg_refs 97143.270235 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 97283.071895 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.occ_blocks::0 657.503073 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 657.275674 # Average occupied blocks per context
|
||||||
system.cpu.icache.occ_percent::0 0.321046 # Average percentage of cache occupancy
|
system.cpu.icache.occ_percent::0 0.320935 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.ReadReq_hits 74411745 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 74421550 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits 74411745 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 74421550 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits 74411745 # number of overall hits
|
system.cpu.icache.overall_hits 74421550 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses 991 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 996 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses 991 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 996 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses 991 # number of overall misses
|
system.cpu.icache.overall_misses 996 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 34848500 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 34937500 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency 34848500 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 34937500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency 34848500 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 34937500 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses 74412736 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 74422546 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses 74412736 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 74422546 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses 74412736 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 74422546 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 35164.984864 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 35077.811245 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency 35164.984864 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 35077.811245 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency 35164.984864 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 35077.811245 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -364,67 +364,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_mshr_hits 225 # number of ReadReq MSHR hits
|
system.cpu.icache.ReadReq_mshr_hits 231 # number of ReadReq MSHR hits
|
||||||
system.cpu.icache.demand_mshr_hits 225 # number of demand (read+write) MSHR hits
|
system.cpu.icache.demand_mshr_hits 231 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.icache.overall_mshr_hits 225 # number of overall MSHR hits
|
system.cpu.icache.overall_mshr_hits 231 # number of overall MSHR hits
|
||||||
system.cpu.icache.ReadReq_mshr_misses 766 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 765 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.demand_mshr_misses 766 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses 765 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses 766 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses 765 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 26233500 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency 26235000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency 26233500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency 26235000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency 26233500 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency 26235000 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34247.389034 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34294.117647 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 34247.389034 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 34294.117647 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 34247.389034 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 34294.117647 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.replacements 441233 # number of replacements
|
system.cpu.dcache.replacements 441200 # number of replacements
|
||||||
system.cpu.dcache.tagsinuse 4094.750739 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 4094.750887 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 205781738 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 205785268 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.sampled_refs 445329 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 445296 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.avg_refs 462.089237 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 462.131409 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 87973000 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 87972000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.occ_blocks::0 4094.750739 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 4094.750887 # Average occupied blocks per context
|
||||||
system.cpu.dcache.occ_percent::0 0.999695 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_percent::0 0.999695 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.ReadReq_hits 137926945 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 137930344 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits 67852137 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 67852261 # number of WriteReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits 1328 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits 1334 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits 1328 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits 1329 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.demand_hits 205779082 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 205782605 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits 205779082 # number of overall hits
|
system.cpu.dcache.overall_hits 205782605 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses 249074 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 248964 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses 1565394 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 1565270 # number of WriteReq misses
|
||||||
system.cpu.dcache.LoadLockedReq_misses 11 # number of LoadLockedReq misses
|
system.cpu.dcache.LoadLockedReq_misses 9 # number of LoadLockedReq misses
|
||||||
system.cpu.dcache.demand_misses 1814468 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 1814234 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses 1814468 # number of overall misses
|
system.cpu.dcache.overall_misses 1814234 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency 3282849000 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 3282822000 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency 27038418025 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 27026336525 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency 203000 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency 201000 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency 30321267025 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 30309158525 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency 30321267025 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 30309158525 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses 138176019 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 138179308 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses 1339 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses 1343 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses 1328 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses 1329 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses 207593550 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 207596839 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses 207593550 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 207596839 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.001803 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.001802 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.022550 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.022549 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.008215 # miss rate for LoadLockedReq accesses
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.006701 # miss rate for LoadLockedReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate 0.008740 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.008739 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate 0.008740 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.008739 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 13180.215518 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 13185.930496 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 17272.595925 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 17266.245775 # average WriteReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 18454.545455 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 22333.333333 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency 16710.830406 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 16706.311603 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency 16710.830406 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 16706.311603 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked
|
||||||
|
@ -433,70 +433,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks 395275 # number of writebacks
|
system.cpu.dcache.writebacks 395250 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 51126 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits 51046 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 1318013 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits 1317892 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_hits 11 # number of LoadLockedReq MSHR hits
|
system.cpu.dcache.LoadLockedReq_mshr_hits 9 # number of LoadLockedReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits 1369139 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 1368938 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits 1369139 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 1368938 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 197948 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 197918 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 247381 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 247378 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses 445329 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 445296 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses 445329 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 445296 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1625134500 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1625205500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2544872027 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2544318027 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 4170006527 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 4169523527 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 4170006527 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 4169523527 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001433 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001432 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.002145 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.002145 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.002145 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.002145 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8209.906137 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8211.509312 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10287.257417 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10285.142684 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 9363.878227 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 9363.487494 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 9363.878227 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 9363.487494 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.replacements 72960 # number of replacements
|
system.cpu.l2cache.replacements 72965 # number of replacements
|
||||||
system.cpu.l2cache.tagsinuse 17805.724339 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 17807.300199 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 422235 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 421253 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.sampled_refs 88493 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 88492 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 4.771394 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 4.760351 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.occ_blocks::0 1879.670498 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 1881.136315 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 15926.053841 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 15926.163884 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.057363 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.057408 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.486025 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.486028 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.ReadReq_hits 165899 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 165871 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits 395275 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 395250 # number of Writeback hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 189031 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits 189027 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits 354930 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 354898 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits 354930 # number of overall hits
|
system.cpu.l2cache.overall_hits 354898 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses 32812 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 32808 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses 58353 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 58355 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses 91165 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 91163 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses 91165 # number of overall misses
|
system.cpu.l2cache.overall_misses 91163 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 1126662000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 1126263500 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 2003366500 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 2003081500 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency 3130028500 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 3129345000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency 3130028500 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 3129345000 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses 198711 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 198679 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses 395275 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 395250 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses 247384 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 247382 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses 446095 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 446061 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 446095 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 446061 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.165124 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.165131 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.235880 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 0.235890 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate 0.204362 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.204373 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate 0.204362 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.204373 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34336.888943 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34328.928920 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34331.850976 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34325.790421 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34333.664235 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 34326.919913 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34333.664235 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34326.919913 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked
|
||||||
|
@ -505,28 +505,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.writebacks 58128 # number of writebacks
|
system.cpu.l2cache.writebacks 58130 # number of writebacks
|
||||||
system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
|
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
|
||||||
system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 32801 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 32798 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 58353 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 58355 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses 91154 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 91153 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses 91154 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 91153 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1019608000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1019340000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822407000 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822214500 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 2842015000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 2841554500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 2842015000 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 2841554500 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165069 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165080 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235880 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235890 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.204338 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.204351 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.204338 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.204351 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31084.662053 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.334106 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31230.733638 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31226.364493 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31178.171007 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.461104 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31178.171007 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.461104 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=false
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=System
|
type=System
|
||||||
children=cpu membus physmem
|
children=cpu membus physmem
|
||||||
|
boot_osflags=a
|
||||||
|
init_param=0
|
||||||
|
kernel=
|
||||||
|
load_addr_mask=1099511627775
|
||||||
mem_mode=atomic
|
mem_mode=atomic
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
|
readfile=
|
||||||
|
symbolfile=
|
||||||
work_begin_ckpt_count=0
|
work_begin_ckpt_count=0
|
||||||
work_begin_cpu_id_exit=-1
|
work_begin_cpu_id_exit=-1
|
||||||
work_begin_exit_count=0
|
work_begin_exit_count=0
|
||||||
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
type=DerivO3CPU
|
type=DerivO3CPU
|
||||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||||
BTBEntries=4096
|
BTBEntries=4096
|
||||||
BTBTagSize=16
|
BTBTagSize=16
|
||||||
LFSTSize=1024
|
LFSTSize=1024
|
||||||
|
@ -52,6 +59,7 @@ decodeWidth=8
|
||||||
defer_registration=false
|
defer_registration=false
|
||||||
dispatchWidth=8
|
dispatchWidth=8
|
||||||
do_checkpoint_insts=true
|
do_checkpoint_insts=true
|
||||||
|
do_quiesce=true
|
||||||
do_statistics_insts=true
|
do_statistics_insts=true
|
||||||
dtb=system.cpu.dtb
|
dtb=system.cpu.dtb
|
||||||
fetchToDecodeDelay=1
|
fetchToDecodeDelay=1
|
||||||
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
||||||
iewToFetchDelay=1
|
iewToFetchDelay=1
|
||||||
iewToRenameDelay=1
|
iewToRenameDelay=1
|
||||||
instShiftAmt=2
|
instShiftAmt=2
|
||||||
|
interrupts=system.cpu.interrupts
|
||||||
issueToExecuteDelay=1
|
issueToExecuteDelay=1
|
||||||
issueWidth=8
|
issueWidth=8
|
||||||
itb=system.cpu.itb
|
itb=system.cpu.itb
|
||||||
|
@ -89,6 +98,7 @@ numRobs=1
|
||||||
numThreads=1
|
numThreads=1
|
||||||
phase=0
|
phase=0
|
||||||
predType=tournament
|
predType=tournament
|
||||||
|
profile=0
|
||||||
progress_interval=0
|
progress_interval=0
|
||||||
renameToDecodeDelay=1
|
renameToDecodeDelay=1
|
||||||
renameToFetchDelay=1
|
renameToFetchDelay=1
|
||||||
|
@ -149,7 +159,14 @@ mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
[system.cpu.dtb]
|
[system.cpu.dtb]
|
||||||
type=X86TLB
|
type=X86TLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.dtb.walker
|
||||||
|
|
||||||
|
[system.cpu.dtb.walker]
|
||||||
|
type=X86PagetableWalker
|
||||||
|
system=system
|
||||||
|
port=system.cpu.toL2Bus.port[3]
|
||||||
|
|
||||||
[system.cpu.fuPool]
|
[system.cpu.fuPool]
|
||||||
type=FUPool
|
type=FUPool
|
||||||
|
@ -446,9 +463,25 @@ write_buffers=8
|
||||||
cpu_side=system.cpu.icache_port
|
cpu_side=system.cpu.icache_port
|
||||||
mem_side=system.cpu.toL2Bus.port[0]
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.interrupts]
|
||||||
|
type=X86LocalApic
|
||||||
|
int_latency=1000
|
||||||
|
pio_addr=2305843009213693952
|
||||||
|
pio_latency=1000
|
||||||
|
system=system
|
||||||
|
int_port=system.membus.port[4]
|
||||||
|
pio=system.membus.port[3]
|
||||||
|
|
||||||
[system.cpu.itb]
|
[system.cpu.itb]
|
||||||
type=X86TLB
|
type=X86TLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.itb.walker
|
||||||
|
|
||||||
|
[system.cpu.itb.walker]
|
||||||
|
type=X86PagetableWalker
|
||||||
|
system=system
|
||||||
|
port=system.cpu.toL2Bus.port[2]
|
||||||
|
|
||||||
[system.cpu.l2cache]
|
[system.cpu.l2cache]
|
||||||
type=BaseCache
|
type=BaseCache
|
||||||
|
@ -479,7 +512,7 @@ tgts_per_mshr=5
|
||||||
trace_addr=0
|
trace_addr=0
|
||||||
two_queue=false
|
two_queue=false
|
||||||
write_buffers=8
|
write_buffers=8
|
||||||
cpu_side=system.cpu.toL2Bus.port[2]
|
cpu_side=system.cpu.toL2Bus.port[4]
|
||||||
mem_side=system.membus.port[2]
|
mem_side=system.membus.port[2]
|
||||||
|
|
||||||
[system.cpu.toL2Bus]
|
[system.cpu.toL2Bus]
|
||||||
|
@ -490,7 +523,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
[system.cpu.tracer]
|
[system.cpu.tracer]
|
||||||
type=ExeTracer
|
type=ExeTracer
|
||||||
|
@ -498,7 +531,7 @@ type=ExeTracer
|
||||||
[system.cpu.workload]
|
[system.cpu.workload]
|
||||||
type=LiveProcess
|
type=LiveProcess
|
||||||
cmd=gzip input.log 1
|
cmd=gzip input.log 1
|
||||||
cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
|
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
|
||||||
egid=100
|
egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
|
@ -522,7 +555,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||||
|
|
||||||
[system.physmem]
|
[system.physmem]
|
||||||
type=PhysicalMemory
|
type=PhysicalMemory
|
||||||
|
|
|
@ -1,12 +1,12 @@
|
||||||
Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simout
|
Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
|
||||||
Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simerr
|
Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 28 2012 12:11:40
|
gem5 compiled Feb 9 2012 12:45:55
|
||||||
gem5 started Jan 28 2012 12:12:43
|
gem5 started Feb 9 2012 12:46:40
|
||||||
gem5 executing on ribera.cs.wisc.edu
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
|
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
spec_init
|
spec_init
|
||||||
|
@ -42,4 +42,4 @@ Uncompressing Data
|
||||||
Uncompressed data 1048576 bytes in length
|
Uncompressed data 1048576 bytes in length
|
||||||
Uncompressed data compared correctly
|
Uncompressed data compared correctly
|
||||||
Tested 1MB buffer: OK!
|
Tested 1MB buffer: OK!
|
||||||
Exiting @ tick 588785308000 because target called exit()
|
Exiting @ tick 586834596000 because target called exit()
|
||||||
|
|
|
@ -1,262 +1,262 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.588785 # Number of seconds simulated
|
sim_seconds 0.586835 # Number of seconds simulated
|
||||||
sim_ticks 588785308000 # Number of ticks simulated
|
sim_ticks 586834596000 # Number of ticks simulated
|
||||||
final_tick 588785308000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 586834596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 112730 # Simulator instruction rate (inst/s)
|
host_inst_rate 99458 # Simulator instruction rate (inst/s)
|
||||||
host_tick_rate 40933847 # Simulator tick rate (ticks/s)
|
host_tick_rate 35994653 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 244824 # Number of bytes of host memory used
|
host_mem_usage 253740 # Number of bytes of host memory used
|
||||||
host_seconds 14383.83 # Real time elapsed on the host
|
host_seconds 16303.38 # Real time elapsed on the host
|
||||||
sim_insts 1621493982 # Number of instructions simulated
|
sim_insts 1621493982 # Number of instructions simulated
|
||||||
system.physmem.bytes_read 5878272 # Number of bytes read from this memory
|
system.physmem.bytes_read 5879616 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read 57216 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read 57024 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written 3742528 # Number of bytes written to this memory
|
system.physmem.bytes_written 3743488 # Number of bytes written to this memory
|
||||||
system.physmem.num_reads 91848 # Number of read requests responded to by this memory
|
system.physmem.num_reads 91869 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes 58477 # Number of write requests responded to by this memory
|
system.physmem.num_writes 58492 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||||
system.physmem.bw_read 9983727 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read 10019205 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read 97176 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read 97172 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write 6356354 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write 6379119 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total 16340082 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total 16398324 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||||
system.cpu.numCycles 1177570617 # number of cpu cycles simulated
|
system.cpu.numCycles 1173669193 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.BPredUnit.lookups 141882222 # Number of BP lookups
|
system.cpu.BPredUnit.lookups 140536614 # Number of BP lookups
|
||||||
system.cpu.BPredUnit.condPredicted 141882222 # Number of conditional branches predicted
|
system.cpu.BPredUnit.condPredicted 140536614 # Number of conditional branches predicted
|
||||||
system.cpu.BPredUnit.condIncorrect 7459322 # Number of conditional branches incorrect
|
system.cpu.BPredUnit.condIncorrect 7896314 # Number of conditional branches incorrect
|
||||||
system.cpu.BPredUnit.BTBLookups 135523268 # Number of BTB lookups
|
system.cpu.BPredUnit.BTBLookups 133769291 # Number of BTB lookups
|
||||||
system.cpu.BPredUnit.BTBHits 134664780 # Number of BTB hits
|
system.cpu.BPredUnit.BTBHits 132901689 # Number of BTB hits
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 141519405 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 138231227 # Number of cycles fetch is stalled on an Icache miss
|
||||||
system.cpu.fetch.Insts 1135188232 # Number of instructions fetch has processed
|
system.cpu.fetch.Insts 1143529036 # Number of instructions fetch has processed
|
||||||
system.cpu.fetch.Branches 141882222 # Number of branches that fetch encountered
|
system.cpu.fetch.Branches 140536614 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 134664780 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 132901689 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.Cycles 328423216 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.fetch.Cycles 330118681 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
system.cpu.fetch.SquashCycles 56273795 # Number of cycles fetch has spent squashing
|
system.cpu.fetch.SquashCycles 56348337 # Number of cycles fetch has spent squashing
|
||||||
system.cpu.fetch.BlockedCycles 658902879 # Number of cycles fetch has spent blocked
|
system.cpu.fetch.BlockedCycles 656952944 # Number of cycles fetch has spent blocked
|
||||||
system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps
|
system.cpu.fetch.PendingTrapStallCycles 378 # Number of stall cycles due to pending traps
|
||||||
system.cpu.fetch.CacheLines 135738609 # Number of cache lines fetched
|
system.cpu.fetch.CacheLines 136534174 # Number of cache lines fetched
|
||||||
system.cpu.fetch.IcacheSquashes 998788 # Number of outstanding Icache misses that were squashed
|
system.cpu.fetch.IcacheSquashes 2392311 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 1177479353 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 1173574785 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 1.766783 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 1.778199 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 3.096310 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 3.100517 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::0 852058955 72.36% 72.36% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::0 846464435 72.13% 72.13% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::1 15948065 1.35% 73.72% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::1 17271965 1.47% 73.60% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::2 17931063 1.52% 75.24% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::2 15892053 1.35% 74.95% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::3 17495755 1.49% 76.73% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::3 19142892 1.63% 76.58% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::4 23352779 1.98% 78.71% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::4 23218397 1.98% 78.56% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::5 16626553 1.41% 80.12% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::5 16689415 1.42% 79.98% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::6 22402886 1.90% 82.02% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::6 22145456 1.89% 81.87% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::7 28214099 2.40% 84.42% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::7 30830267 2.63% 84.50% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::8 183449198 15.58% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::8 181919905 15.50% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 1177479353 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 1173574785 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.branchRate 0.120487 # Number of branch fetches per cycle
|
system.cpu.fetch.branchRate 0.119741 # Number of branch fetches per cycle
|
||||||
system.cpu.fetch.rate 0.964009 # Number of inst fetches per cycle
|
system.cpu.fetch.rate 0.974320 # Number of inst fetches per cycle
|
||||||
system.cpu.decode.IdleCycles 241266448 # Number of cycles decode is idle
|
system.cpu.decode.IdleCycles 240018155 # Number of cycles decode is idle
|
||||||
system.cpu.decode.BlockedCycles 565597424 # Number of cycles decode is blocked
|
system.cpu.decode.BlockedCycles 564065687 # Number of cycles decode is blocked
|
||||||
system.cpu.decode.RunCycles 225300633 # Number of cycles decode is running
|
system.cpu.decode.RunCycles 224667967 # Number of cycles decode is running
|
||||||
system.cpu.decode.UnblockCycles 96681345 # Number of cycles decode is unblocking
|
system.cpu.decode.UnblockCycles 96551481 # Number of cycles decode is unblocking
|
||||||
system.cpu.decode.SquashCycles 48633503 # Number of cycles decode is squashing
|
system.cpu.decode.SquashCycles 48271495 # Number of cycles decode is squashing
|
||||||
system.cpu.decode.DecodedInsts 2058834896 # Number of instructions handled by decode
|
system.cpu.decode.DecodedInsts 2053347825 # Number of instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 48633503 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 48271495 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 289994325 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 288250921 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 136667782 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 136396250 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 3607 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 3594 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 255841310 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 255481832 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 446338826 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 445170693 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 2031094400 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 2022383034 # Number of instructions processed by rename
|
||||||
system.cpu.rename.ROBFullEvents 199 # Number of times rename has blocked due to ROB full
|
system.cpu.rename.ROBFullEvents 772 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.rename.IQFullEvents 278357951 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 278054588 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LSQFullEvents 133112570 # Number of times rename has blocked due to LSQ full
|
system.cpu.rename.LSQFullEvents 132157059 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.rename.RenamedOperands 2019296537 # Number of destination operands rename has renamed
|
system.cpu.rename.RenamedOperands 2011799289 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenameLookups 4928551600 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenameLookups 4917261318 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.int_rename_lookups 4928548640 # Number of integer rename lookups
|
system.cpu.rename.int_rename_lookups 4917257566 # Number of integer rename lookups
|
||||||
system.cpu.rename.fp_rename_lookups 2960 # Number of floating rename lookups
|
system.cpu.rename.fp_rename_lookups 3752 # Number of floating rename lookups
|
||||||
system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed
|
system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed
|
||||||
system.cpu.rename.UndoneMaps 401301887 # Number of HB maps that are undone due to squashing
|
system.cpu.rename.UndoneMaps 393804639 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.rename.serializingInsts 93 # count of serializing insts renamed
|
system.cpu.rename.serializingInsts 92 # count of serializing insts renamed
|
||||||
system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed
|
system.cpu.rename.tempSerializingInsts 92 # count of temporary serializing insts renamed
|
||||||
system.cpu.rename.skidInsts 797995614 # count of insts added to the skid buffer
|
system.cpu.rename.skidInsts 795963127 # count of insts added to the skid buffer
|
||||||
system.cpu.memDep0.insertedLoads 517349896 # Number of loads inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedLoads 515675644 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.insertedStores 226176362 # Number of stores inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedStores 225280197 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.conflictingLoads 355062669 # Number of conflicting loads.
|
system.cpu.memDep0.conflictingLoads 353360778 # Number of conflicting loads.
|
||||||
system.cpu.memDep0.conflictingStores 148977960 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 147850226 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 1979799927 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 1972232230 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 215 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 190 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 1779311117 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 1776284004 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 175082 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 173989 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 358154503 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 350598274 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 654941515 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 640215855 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 165 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.iq.issued_per_cycle::samples 1177479353 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::samples 1173574785 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.511119 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 1.513567 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.319645 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.313751 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 271443176 23.05% 23.05% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 268099715 22.84% 22.84% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 420511572 35.71% 58.77% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 420406461 35.82% 58.67% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 239784716 20.36% 79.13% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 239398162 20.40% 79.07% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 159545639 13.55% 92.68% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 159391711 13.58% 92.65% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 48751983 4.14% 96.82% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 48358537 4.12% 96.77% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::5 21481111 1.82% 98.64% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::5 24330955 2.07% 98.84% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::6 13897994 1.18% 99.82% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::6 11625243 0.99% 99.83% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::7 1713551 0.15% 99.97% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::7 1646303 0.14% 99.97% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::8 349611 0.03% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::8 317698 0.03% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::total 1177479353 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::total 1173574785 # Number of insts issued each cycle
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntAlu 183781 6.86% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntAlu 185497 7.34% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntMult 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.86% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.34% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemRead 2344413 87.49% 94.35% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemRead 2190114 86.61% 93.95% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemWrite 151333 5.65% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemWrite 153108 6.05% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 26390474 1.48% 1.48% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 26819156 1.51% 1.51% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 1101178190 61.89% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 1098315644 61.83% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 457060255 25.69% 89.06% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 456429787 25.70% 89.04% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 194682198 10.94% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 194719417 10.96% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 1779311117 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 1776284004 # Type of FU issued
|
||||||
system.cpu.iq.rate 1.511002 # Inst issue rate
|
system.cpu.iq.rate 1.513445 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 2679527 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 2528719 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.001506 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.001424 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 4738956161 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 4728845466 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 2338163322 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 2323038766 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1758678242 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1755173186 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 458 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 448 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 1755600151 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 1751993548 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 207757708 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 207962564 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 98307771 # Number of loads squashed
|
system.cpu.iew.lsq.thread0.squashedLoads 96633519 # Number of loads squashed
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 75876 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iew.lsq.thread0.ignoredResponses 76725 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 215687 # Number of memory ordering violations
|
system.cpu.iew.lsq.thread0.memOrderViolation 215178 # Number of memory ordering violations
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 37990305 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 37094140 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 1126 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1306 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 48633503 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 48271495 # Number of cycles IEW is squashing
|
||||||
system.cpu.iew.iewBlockCycles 1923683 # Number of cycles IEW is blocking
|
system.cpu.iew.iewBlockCycles 1965747 # Number of cycles IEW is blocking
|
||||||
system.cpu.iew.iewUnblockCycles 157688 # Number of cycles IEW is unblocking
|
system.cpu.iew.iewUnblockCycles 154206 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iew.iewDispatchedInsts 1979800142 # Number of instructions dispatched to IQ
|
system.cpu.iew.iewDispatchedInsts 1972232420 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iew.iewDispSquashedInsts 665872 # Number of squashed instructions skipped by dispatch
|
system.cpu.iew.iewDispSquashedInsts 7113535 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iew.iewDispLoadInsts 517349896 # Number of dispatched load instructions
|
system.cpu.iew.iewDispLoadInsts 515675644 # Number of dispatched load instructions
|
||||||
system.cpu.iew.iewDispStoreInsts 226176362 # Number of dispatched store instructions
|
system.cpu.iew.iewDispStoreInsts 225280197 # Number of dispatched store instructions
|
||||||
system.cpu.iew.iewDispNonSpecInsts 85 # Number of dispatched non-speculative instructions
|
system.cpu.iew.iewDispNonSpecInsts 85 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.iew.iewIQFullEvents 70768 # Number of times the IQ has become full, causing a stall
|
system.cpu.iew.iewIQFullEvents 69568 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.iew.iewLSQFullEvents 44 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iew.iewLSQFullEvents 118 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.iew.memOrderViolationEvents 215687 # Number of memory order violations
|
system.cpu.iew.memOrderViolationEvents 215178 # Number of memory order violations
|
||||||
system.cpu.iew.predictedTakenIncorrect 4604749 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 4620478 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 3040457 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 3457907 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 7645206 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 8078385 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 1766024784 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 1762068190 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 451208749 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 450602678 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 13286333 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 14215814 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 645051015 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 644481818 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 112022135 # Number of branches executed
|
system.cpu.iew.exec_branches 111935144 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 193842266 # Number of stores executed
|
system.cpu.iew.exec_stores 193879140 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 1.499719 # Inst execution rate
|
system.cpu.iew.exec_rate 1.501333 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 1764443624 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 1756702193 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 1758678254 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 1755173198 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 1332033031 # num instructions producing a value
|
system.cpu.iew.wb_producers 1327558450 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 1982428848 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 1975144997 # num instructions consuming a value
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.iew.wb_rate 1.493480 # insts written-back per cycle
|
system.cpu.iew.wb_rate 1.495458 # insts written-back per cycle
|
||||||
system.cpu.iew.wb_fanout 0.671920 # average fanout of values written-back
|
system.cpu.iew.wb_fanout 0.672132 # average fanout of values written-back
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
|
system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
|
||||||
system.cpu.commit.commitSquashedInsts 358308768 # The number of squashed insts skipped by commit
|
system.cpu.commit.commitSquashedInsts 350742946 # The number of squashed insts skipped by commit
|
||||||
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.commit.branchMispredicts 7459361 # The number of times a branch was mispredicted
|
system.cpu.commit.branchMispredicts 7896364 # The number of times a branch was mispredicted
|
||||||
system.cpu.commit.committed_per_cycle::samples 1128845850 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::samples 1125303290 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.436418 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::mean 1.440940 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::stdev 1.651874 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::stdev 1.651939 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::0 347283519 30.76% 30.76% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::0 343524257 30.53% 30.53% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::1 441725058 39.13% 69.90% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::1 441933791 39.27% 69.80% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::2 99623372 8.83% 78.72% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::2 99674686 8.86% 78.66% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::3 136537223 12.10% 90.82% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::3 136523006 12.13% 90.79% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::4 31770740 2.81% 93.63% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::4 31731928 2.82% 93.61% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::5 26056867 2.31% 95.94% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::5 26136643 2.32% 95.93% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::6 22501724 1.99% 97.93% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::6 22505633 2.00% 97.93% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::7 8245904 0.73% 98.66% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::7 8189692 0.73% 98.66% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::8 15101443 1.34% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::8 15083654 1.34% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::total 1128845850 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::total 1125303290 # Number of insts commited each cycle
|
||||||
system.cpu.commit.count 1621493982 # Number of instructions committed
|
system.cpu.commit.count 1621493982 # Number of instructions committed
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.commit.refs 607228182 # Number of memory references committed
|
system.cpu.commit.refs 607228182 # Number of memory references committed
|
||||||
|
@ -266,48 +266,48 @@ system.cpu.commit.branches 107161579 # Nu
|
||||||
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
||||||
system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
|
system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
|
||||||
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
||||||
system.cpu.commit.bw_lim_events 15101443 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 15083654 # number cycles where commit BW limit reached
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.rob.rob_reads 3093547157 # The number of ROB reads
|
system.cpu.rob.rob_reads 3082456564 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 4008258633 # The number of ROB writes
|
system.cpu.rob.rob_writes 3992764754 # The number of ROB writes
|
||||||
system.cpu.timesIdled 21053 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 21723 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 91264 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 94408 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
|
system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
|
||||||
system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
|
system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
|
||||||
system.cpu.cpi 0.726226 # CPI: Cycles Per Instruction
|
system.cpu.cpi 0.723820 # CPI: Cycles Per Instruction
|
||||||
system.cpu.cpi_total 0.726226 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 0.723820 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 1.376982 # IPC: Instructions Per Cycle
|
system.cpu.ipc 1.381560 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 1.376982 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 1.381560 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 3270153545 # number of integer regfile reads
|
system.cpu.int_regfile_reads 3268959976 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 1754693299 # number of integer regfile writes
|
system.cpu.int_regfile_writes 1746565098 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 12 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 12 # number of floating regfile reads
|
||||||
system.cpu.misc_regfile_reads 907833056 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 905288155 # number of misc regfile reads
|
||||||
system.cpu.icache.replacements 12 # number of replacements
|
system.cpu.icache.replacements 12 # number of replacements
|
||||||
system.cpu.icache.tagsinuse 808.459907 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 807.278486 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 135737385 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 136532946 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.sampled_refs 897 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 894 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.avg_refs 151323.729097 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 152721.416107 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.occ_blocks::0 808.459907 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 807.278486 # Average occupied blocks per context
|
||||||
system.cpu.icache.occ_percent::0 0.394756 # Average percentage of cache occupancy
|
system.cpu.icache.occ_percent::0 0.394179 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.ReadReq_hits 135737385 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 136532946 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits 135737385 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 136532946 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits 135737385 # number of overall hits
|
system.cpu.icache.overall_hits 136532946 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses 1224 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 1228 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses 1224 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 1228 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses 1224 # number of overall misses
|
system.cpu.icache.overall_misses 1228 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 43199000 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 43195500 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency 43199000 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 43195500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency 43199000 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 43195500 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses 135738609 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 136534174 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses 135738609 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 136534174 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses 135738609 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 136534174 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 35293.300654 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 35175.488599 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency 35293.300654 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 35175.488599 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency 35293.300654 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 35175.488599 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -317,59 +317,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_mshr_hits 327 # number of ReadReq MSHR hits
|
system.cpu.icache.ReadReq_mshr_hits 334 # number of ReadReq MSHR hits
|
||||||
system.cpu.icache.demand_mshr_hits 327 # number of demand (read+write) MSHR hits
|
system.cpu.icache.demand_mshr_hits 334 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.icache.overall_mshr_hits 327 # number of overall MSHR hits
|
system.cpu.icache.overall_mshr_hits 334 # number of overall MSHR hits
|
||||||
system.cpu.icache.ReadReq_mshr_misses 897 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 894 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.demand_mshr_misses 897 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses 894 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses 897 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses 894 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 31683500 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency 31569000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency 31683500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency 31569000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency 31683500 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency 31569000 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35321.627648 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35312.080537 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 35321.627648 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 35312.080537 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 35321.627648 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 35312.080537 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.replacements 459032 # number of replacements
|
system.cpu.dcache.replacements 459037 # number of replacements
|
||||||
system.cpu.dcache.tagsinuse 4094.268658 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 4094.269422 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 431168175 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 430357004 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.sampled_refs 463128 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 463133 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.avg_refs 930.991378 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 929.229841 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 416529000 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 414463000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.occ_blocks::0 4094.268658 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 4094.269422 # Average occupied blocks per context
|
||||||
system.cpu.dcache.occ_percent::0 0.999577 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_percent::0 0.999577 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.ReadReq_hits 243231636 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 242420503 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits 187936539 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 187936501 # number of WriteReq hits
|
||||||
system.cpu.dcache.demand_hits 431168175 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 430357004 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits 431168175 # number of overall hits
|
system.cpu.dcache.overall_hits 430357004 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses 217117 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 217102 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses 249518 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 249556 # number of WriteReq misses
|
||||||
system.cpu.dcache.demand_misses 466635 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 466658 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses 466635 # number of overall misses
|
system.cpu.dcache.overall_misses 466658 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency 2193700500 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 2192767500 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency 3216393000 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 3219007000 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency 5410093500 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 5411774500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency 5410093500 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 5411774500 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses 243448753 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 242637605 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses 431634810 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 430823662 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses 431634810 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 430823662 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.000892 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.000895 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.001326 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.001326 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate 0.001081 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.001083 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate 0.001081 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.001083 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 10103.771239 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 10100.171809 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 12890.424739 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 12898.936511 # average WriteReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency 11593.844225 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 11596.875013 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency 11593.844225 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 11596.875013 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -378,69 +378,69 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks 409997 # number of writebacks
|
system.cpu.dcache.writebacks 409999 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 3467 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits 3488 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 38 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits 35 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits 3505 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 3523 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits 3505 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 3523 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 213650 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 213614 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 249480 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 249521 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses 463130 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 463135 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses 463130 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 463135 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1524751500 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1523998500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2467190000 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2469759000 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 3991941500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 3993757500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 3991941500 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 3993757500 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000878 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000880 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.001073 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.001075 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.001073 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.001075 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7136.679148 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7134.356831 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9889.329806 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9898.000569 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 8619.483730 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 8623.311777 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 8619.483730 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 8623.311777 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.replacements 73588 # number of replacements
|
system.cpu.l2cache.replacements 73601 # number of replacements
|
||||||
system.cpu.l2cache.tagsinuse 17962.176251 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 17971.586292 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 452941 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 452847 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.sampled_refs 89203 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 89223 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 5.077643 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 5.075451 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.occ_blocks::0 1977.761332 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 1981.498209 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 15984.414919 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 15990.088083 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.060356 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.060471 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.487806 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.487979 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.ReadReq_hits 181391 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 181345 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits 409997 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 409999 # number of Writeback hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 190788 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits 190815 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits 372179 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 372160 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits 372179 # number of overall hits
|
system.cpu.l2cache.overall_hits 372160 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses 33152 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 33162 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses 58696 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 58707 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses 91848 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 91869 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses 91848 # number of overall misses
|
system.cpu.l2cache.overall_misses 91869 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 1130561500 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 1129684500 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 2008268500 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 2008512000 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency 3138830000 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 3138196500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency 3138830000 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 3138196500 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses 214543 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 214507 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses 409997 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 409999 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses 249484 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 249522 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses 464027 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 464029 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 464027 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 464029 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.154524 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.154596 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.235270 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 0.235278 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate 0.197937 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.197981 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate 0.197937 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.197981 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34102.361848 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34065.632350 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34214.742061 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34212.478921 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34174.179078 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 34159.471639 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34174.179078 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34159.471639 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -449,27 +449,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.writebacks 58477 # number of writebacks
|
system.cpu.l2cache.writebacks 58492 # number of writebacks
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 33152 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 33162 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 58696 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 58707 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses 91848 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 91869 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses 91848 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 91869 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1027873500 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1028173500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1819617000 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1819949000 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 2847490500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 2848122500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 2847490500 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 2848122500 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154524 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154596 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235270 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235278 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.197937 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.197981 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.197937 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.197981 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.871501 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.568482 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.698514 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.545080 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.204730 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.204730 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=false
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=System
|
type=System
|
||||||
children=cpu membus physmem
|
children=cpu membus physmem
|
||||||
|
boot_osflags=a
|
||||||
|
init_param=0
|
||||||
|
kernel=
|
||||||
|
load_addr_mask=1099511627775
|
||||||
mem_mode=atomic
|
mem_mode=atomic
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
|
readfile=
|
||||||
|
symbolfile=
|
||||||
work_begin_ckpt_count=0
|
work_begin_ckpt_count=0
|
||||||
work_begin_cpu_id_exit=-1
|
work_begin_cpu_id_exit=-1
|
||||||
work_begin_exit_count=0
|
work_begin_exit_count=0
|
||||||
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
type=DerivO3CPU
|
type=DerivO3CPU
|
||||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||||
BTBEntries=4096
|
BTBEntries=4096
|
||||||
BTBTagSize=16
|
BTBTagSize=16
|
||||||
LFSTSize=1024
|
LFSTSize=1024
|
||||||
|
@ -52,6 +59,7 @@ decodeWidth=8
|
||||||
defer_registration=false
|
defer_registration=false
|
||||||
dispatchWidth=8
|
dispatchWidth=8
|
||||||
do_checkpoint_insts=true
|
do_checkpoint_insts=true
|
||||||
|
do_quiesce=true
|
||||||
do_statistics_insts=true
|
do_statistics_insts=true
|
||||||
dtb=system.cpu.dtb
|
dtb=system.cpu.dtb
|
||||||
fetchToDecodeDelay=1
|
fetchToDecodeDelay=1
|
||||||
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
||||||
iewToFetchDelay=1
|
iewToFetchDelay=1
|
||||||
iewToRenameDelay=1
|
iewToRenameDelay=1
|
||||||
instShiftAmt=2
|
instShiftAmt=2
|
||||||
|
interrupts=system.cpu.interrupts
|
||||||
issueToExecuteDelay=1
|
issueToExecuteDelay=1
|
||||||
issueWidth=8
|
issueWidth=8
|
||||||
itb=system.cpu.itb
|
itb=system.cpu.itb
|
||||||
|
@ -80,6 +89,7 @@ max_insts_all_threads=0
|
||||||
max_insts_any_thread=0
|
max_insts_any_thread=0
|
||||||
max_loads_all_threads=0
|
max_loads_all_threads=0
|
||||||
max_loads_any_thread=0
|
max_loads_any_thread=0
|
||||||
|
needsTSO=false
|
||||||
numIQEntries=64
|
numIQEntries=64
|
||||||
numPhysFloatRegs=256
|
numPhysFloatRegs=256
|
||||||
numPhysIntRegs=256
|
numPhysIntRegs=256
|
||||||
|
@ -88,6 +98,7 @@ numRobs=1
|
||||||
numThreads=1
|
numThreads=1
|
||||||
phase=0
|
phase=0
|
||||||
predType=tournament
|
predType=tournament
|
||||||
|
profile=0
|
||||||
progress_interval=0
|
progress_interval=0
|
||||||
renameToDecodeDelay=1
|
renameToDecodeDelay=1
|
||||||
renameToFetchDelay=1
|
renameToFetchDelay=1
|
||||||
|
@ -148,7 +159,16 @@ mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
[system.cpu.dtb]
|
[system.cpu.dtb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.dtb.walker
|
||||||
|
|
||||||
|
[system.cpu.dtb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[3]
|
||||||
|
|
||||||
[system.cpu.fuPool]
|
[system.cpu.fuPool]
|
||||||
type=FUPool
|
type=FUPool
|
||||||
|
@ -445,9 +465,21 @@ write_buffers=8
|
||||||
cpu_side=system.cpu.icache_port
|
cpu_side=system.cpu.icache_port
|
||||||
mem_side=system.cpu.toL2Bus.port[0]
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.interrupts]
|
||||||
|
type=ArmInterrupts
|
||||||
|
|
||||||
[system.cpu.itb]
|
[system.cpu.itb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.itb.walker
|
||||||
|
|
||||||
|
[system.cpu.itb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[2]
|
||||||
|
|
||||||
[system.cpu.l2cache]
|
[system.cpu.l2cache]
|
||||||
type=BaseCache
|
type=BaseCache
|
||||||
|
@ -478,7 +510,7 @@ tgts_per_mshr=5
|
||||||
trace_addr=0
|
trace_addr=0
|
||||||
two_queue=false
|
two_queue=false
|
||||||
write_buffers=8
|
write_buffers=8
|
||||||
cpu_side=system.cpu.toL2Bus.port[2]
|
cpu_side=system.cpu.toL2Bus.port[4]
|
||||||
mem_side=system.membus.port[2]
|
mem_side=system.membus.port[2]
|
||||||
|
|
||||||
[system.cpu.toL2Bus]
|
[system.cpu.toL2Bus]
|
||||||
|
@ -489,7 +521,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
[system.cpu.tracer]
|
[system.cpu.tracer]
|
||||||
type=ExeTracer
|
type=ExeTracer
|
||||||
|
@ -497,14 +529,14 @@ type=ExeTracer
|
||||||
[system.cpu.workload]
|
[system.cpu.workload]
|
||||||
type=LiveProcess
|
type=LiveProcess
|
||||||
cmd=mcf mcf.in
|
cmd=mcf mcf.in
|
||||||
cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
|
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||||
egid=100
|
egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||||
gid=100
|
gid=100
|
||||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
output=cout
|
output=cout
|
||||||
pid=100
|
pid=100
|
||||||
|
|
|
@ -1,10 +1,12 @@
|
||||||
|
Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout
|
||||||
|
Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 23 2012 04:16:21
|
gem5 compiled Feb 10 2012 00:18:03
|
||||||
gem5 started Jan 23 2012 08:43:41
|
gem5 started Feb 10 2012 00:18:22
|
||||||
gem5 executing on zizzer
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
|
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
|
||||||
|
@ -23,4 +25,4 @@ simplex iterations : 2663
|
||||||
flow value : 3080014995
|
flow value : 3080014995
|
||||||
checksum : 68389
|
checksum : 68389
|
||||||
optimal
|
optimal
|
||||||
Exiting @ tick 33080569000 because target called exit()
|
Exiting @ tick 33080570000 because target called exit()
|
||||||
|
|
|
@ -1,13 +1,13 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.033081 # Number of seconds simulated
|
sim_seconds 0.033081 # Number of seconds simulated
|
||||||
sim_ticks 33080569000 # Number of ticks simulated
|
sim_ticks 33080570000 # Number of ticks simulated
|
||||||
final_tick 33080569000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 33080570000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 140676 # Simulator instruction rate (inst/s)
|
host_inst_rate 45520 # Simulator instruction rate (inst/s)
|
||||||
host_tick_rate 50998874 # Simulator tick rate (ticks/s)
|
host_tick_rate 16502276 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 353196 # Number of bytes of host memory used
|
host_mem_usage 388968 # Number of bytes of host memory used
|
||||||
host_seconds 648.65 # Real time elapsed on the host
|
host_seconds 2004.61 # Real time elapsed on the host
|
||||||
sim_insts 91249885 # Number of instructions simulated
|
sim_insts 91249885 # Number of instructions simulated
|
||||||
system.physmem.bytes_read 997440 # Number of bytes read from this memory
|
system.physmem.bytes_read 997440 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read 44864 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read 44864 # Number of instructions bytes read from this memory
|
||||||
|
@ -15,10 +15,10 @@ system.physmem.bytes_written 2048 # Nu
|
||||||
system.physmem.num_reads 15585 # Number of read requests responded to by this memory
|
system.physmem.num_reads 15585 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes 32 # Number of write requests responded to by this memory
|
system.physmem.num_writes 32 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||||
system.physmem.bw_read 30151839 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read 30151838 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read 1356204 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read 1356204 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write 61909 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write 61909 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total 30213749 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total 30213748 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||||
|
@ -62,7 +62,7 @@ system.cpu.itb.hits 0 # DT
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||||
system.cpu.numCycles 66161139 # number of cpu cycles simulated
|
system.cpu.numCycles 66161141 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.BPredUnit.lookups 27503856 # Number of BP lookups
|
system.cpu.BPredUnit.lookups 27503856 # Number of BP lookups
|
||||||
|
@ -73,95 +73,95 @@ system.cpu.BPredUnit.BTBHits 23511296 # Nu
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.BPredUnit.usedRAS 109835 # Number of times the RAS was used to get a target.
|
system.cpu.BPredUnit.usedRAS 109835 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.BPredUnit.RASInCorrect 10070 # Number of incorrect RAS predictions.
|
system.cpu.BPredUnit.RASInCorrect 10070 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 15373276 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 15373267 # Number of cycles fetch is stalled on an Icache miss
|
||||||
system.cpu.fetch.Insts 131330352 # Number of instructions fetch has processed
|
system.cpu.fetch.Insts 131330347 # Number of instructions fetch has processed
|
||||||
system.cpu.fetch.Branches 27503856 # Number of branches that fetch encountered
|
system.cpu.fetch.Branches 27503856 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 23621131 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 23621131 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.Cycles 32575580 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.fetch.Cycles 32575588 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
system.cpu.fetch.SquashCycles 5466802 # Number of cycles fetch has spent squashing
|
system.cpu.fetch.SquashCycles 5466804 # Number of cycles fetch has spent squashing
|
||||||
system.cpu.fetch.BlockedCycles 14146451 # Number of cycles fetch has spent blocked
|
system.cpu.fetch.BlockedCycles 14146452 # Number of cycles fetch has spent blocked
|
||||||
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
system.cpu.fetch.PendingTrapStallCycles 14 # Number of stall cycles due to pending traps
|
system.cpu.fetch.PendingTrapStallCycles 14 # Number of stall cycles due to pending traps
|
||||||
system.cpu.fetch.CacheLines 14744728 # Number of cache lines fetched
|
system.cpu.fetch.CacheLines 14744727 # Number of cache lines fetched
|
||||||
system.cpu.fetch.IcacheSquashes 369535 # Number of outstanding Icache misses that were squashed
|
system.cpu.fetch.IcacheSquashes 369536 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 66131343 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 66131345 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.004854 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.004854 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 2.741973 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 2.741973 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::0 33609066 50.82% 50.82% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::0 33609060 50.82% 50.82% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::1 6636464 10.04% 60.86% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::1 6636469 10.04% 60.86% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::2 5762437 8.71% 69.57% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::2 5762437 8.71% 69.57% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::3 4857984 7.35% 76.92% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::3 4857985 7.35% 76.92% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::4 2814891 4.26% 81.17% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::4 2814890 4.26% 81.17% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::5 1640731 2.48% 83.65% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::5 1640731 2.48% 83.65% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::6 1559267 2.36% 86.01% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::6 1559273 2.36% 86.01% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::7 2974436 4.50% 90.51% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::7 2974432 4.50% 90.51% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::8 6276067 9.49% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::8 6276068 9.49% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 66131343 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 66131345 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.branchRate 0.415710 # Number of branch fetches per cycle
|
system.cpu.fetch.branchRate 0.415710 # Number of branch fetches per cycle
|
||||||
system.cpu.fetch.rate 1.985007 # Number of inst fetches per cycle
|
system.cpu.fetch.rate 1.985007 # Number of inst fetches per cycle
|
||||||
system.cpu.decode.IdleCycles 17946396 # Number of cycles decode is idle
|
system.cpu.decode.IdleCycles 17946387 # Number of cycles decode is idle
|
||||||
system.cpu.decode.BlockedCycles 12652276 # Number of cycles decode is blocked
|
system.cpu.decode.BlockedCycles 12652277 # Number of cycles decode is blocked
|
||||||
system.cpu.decode.RunCycles 30529024 # Number of cycles decode is running
|
system.cpu.decode.RunCycles 30529032 # Number of cycles decode is running
|
||||||
system.cpu.decode.UnblockCycles 996648 # Number of cycles decode is unblocking
|
system.cpu.decode.UnblockCycles 996648 # Number of cycles decode is unblocking
|
||||||
system.cpu.decode.SquashCycles 4006999 # Number of cycles decode is squashing
|
system.cpu.decode.SquashCycles 4007001 # Number of cycles decode is squashing
|
||||||
system.cpu.decode.BranchResolved 4433202 # Number of times decode resolved a branch
|
system.cpu.decode.BranchResolved 4433202 # Number of times decode resolved a branch
|
||||||
system.cpu.decode.BranchMispred 29411 # Number of times decode detected a branch misprediction
|
system.cpu.decode.BranchMispred 29411 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.decode.DecodedInsts 129091755 # Number of instructions handled by decode
|
system.cpu.decode.DecodedInsts 129091783 # Number of instructions handled by decode
|
||||||
system.cpu.decode.SquashedInsts 32642 # Number of squashed instructions handled by decode
|
system.cpu.decode.SquashedInsts 32642 # Number of squashed instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 4006999 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 4007001 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 19654600 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 19654593 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 1107804 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 1107803 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 8424491 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 8424491 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 29777332 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 29777338 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 3160117 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 3160119 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 124853414 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 124853428 # Number of instructions processed by rename
|
||||||
system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full
|
system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.rename.IQFullEvents 254616 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 254616 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LSQFullEvents 1879605 # Number of times rename has blocked due to LSQ full
|
system.cpu.rename.LSQFullEvents 1879607 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers
|
system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers
|
||||||
system.cpu.rename.RenamedOperands 145685583 # Number of destination operands rename has renamed
|
system.cpu.rename.RenamedOperands 145685596 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenameLookups 543523067 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenameLookups 543523130 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.int_rename_lookups 543516086 # Number of integer rename lookups
|
system.cpu.rename.int_rename_lookups 543516149 # Number of integer rename lookups
|
||||||
system.cpu.rename.fp_rename_lookups 6981 # Number of floating rename lookups
|
system.cpu.rename.fp_rename_lookups 6981 # Number of floating rename lookups
|
||||||
system.cpu.rename.CommittedMaps 107429439 # Number of HB maps that are committed
|
system.cpu.rename.CommittedMaps 107429439 # Number of HB maps that are committed
|
||||||
system.cpu.rename.UndoneMaps 38256144 # Number of HB maps that are undone due to squashing
|
system.cpu.rename.UndoneMaps 38256157 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.rename.serializingInsts 662187 # count of serializing insts renamed
|
system.cpu.rename.serializingInsts 662188 # count of serializing insts renamed
|
||||||
system.cpu.rename.tempSerializingInsts 664355 # count of temporary serializing insts renamed
|
system.cpu.rename.tempSerializingInsts 664356 # count of temporary serializing insts renamed
|
||||||
system.cpu.rename.skidInsts 7619533 # count of insts added to the skid buffer
|
system.cpu.rename.skidInsts 7619540 # count of insts added to the skid buffer
|
||||||
system.cpu.memDep0.insertedLoads 29336350 # Number of loads inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedLoads 29336358 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.insertedStores 5741000 # Number of stores inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedStores 5741000 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.conflictingLoads 1194254 # Number of conflicting loads.
|
system.cpu.memDep0.conflictingLoads 1194254 # Number of conflicting loads.
|
||||||
system.cpu.memDep0.conflictingStores 692979 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 692979 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 117270516 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 117270526 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 648807 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 648807 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 106162042 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 106162051 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 30561 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 30561 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 26211084 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 26211100 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 62748223 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 62748267 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 93963 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.iqSquashedNonSpecRemoved 93963 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.iq.issued_per_cycle::samples 66131343 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::samples 66131345 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.605321 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 1.605321 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.761707 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.761707 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 24322507 36.78% 36.78% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 24322505 36.78% 36.78% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 14238727 21.53% 58.31% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 14238731 21.53% 58.31% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 9857796 14.91% 73.22% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 9857797 14.91% 73.22% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 8080873 12.22% 85.44% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 8080871 12.22% 85.44% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 4216462 6.38% 91.81% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 4216459 6.38% 91.81% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::5 2267133 3.43% 95.24% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::5 2267136 3.43% 95.24% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::6 2478028 3.75% 98.99% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::6 2478029 3.75% 98.99% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::7 463113 0.70% 99.69% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::7 463113 0.70% 99.69% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::8 206704 0.31% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::8 206704 0.31% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::total 66131343 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::total 66131345 # Number of insts issued each cycle
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntAlu 52363 10.31% 10.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntAlu 52363 10.30% 10.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntMult 27 0.01% 10.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntMult 27 0.01% 10.31% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 10.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 10.31% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.31% # attempts to use FU when none available
|
||||||
|
@ -190,12 +190,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.31% # at
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.31% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.31% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.31% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemRead 192834 37.95% 48.26% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemRead 192835 37.95% 48.26% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemWrite 262907 51.74% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemWrite 262907 51.74% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 74696384 70.36% 70.36% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 74696385 70.36% 70.36% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 11141 0.01% 70.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 11141 0.01% 70.37% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.37% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.37% # Type of FU issued
|
||||||
|
@ -224,26 +224,26 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 260 0.00% 70.37% # Ty
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.37% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.37% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.37% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.37% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 26155378 24.64% 95.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 26155386 24.64% 95.01% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 5298717 4.99% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 5298717 4.99% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 106162042 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 106162051 # Type of FU issued
|
||||||
system.cpu.iq.rate 1.604598 # Inst issue rate
|
system.cpu.iq.rate 1.604598 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 508131 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 508132 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.004786 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.004786 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 278993219 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 278993240 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 144129610 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 144129636 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 102521129 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 102521130 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 900 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 900 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 1354 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 1354 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 412 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 412 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 106669721 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 106669731 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 452 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 452 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 366276 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 366279 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 6760478 # Number of loads squashed
|
system.cpu.iew.lsq.thread0.squashedLoads 6760486 # Number of loads squashed
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 42465 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iew.lsq.thread0.ignoredResponses 42468 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 731 # Number of memory ordering violations
|
system.cpu.iew.lsq.thread0.memOrderViolation 731 # Number of memory ordering violations
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 994251 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 994251 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
|
@ -251,12 +251,12 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 30282 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 30282 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 4006999 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 4007001 # Number of cycles IEW is squashing
|
||||||
system.cpu.iew.iewBlockCycles 182542 # Number of cycles IEW is blocking
|
system.cpu.iew.iewBlockCycles 182542 # Number of cycles IEW is blocking
|
||||||
system.cpu.iew.iewUnblockCycles 28701 # Number of cycles IEW is unblocking
|
system.cpu.iew.iewUnblockCycles 28701 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iew.iewDispatchedInsts 117958129 # Number of instructions dispatched to IQ
|
system.cpu.iew.iewDispatchedInsts 117958139 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iew.iewDispSquashedInsts 810273 # Number of squashed instructions skipped by dispatch
|
system.cpu.iew.iewDispSquashedInsts 810273 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iew.iewDispLoadInsts 29336350 # Number of dispatched load instructions
|
system.cpu.iew.iewDispLoadInsts 29336358 # Number of dispatched load instructions
|
||||||
system.cpu.iew.iewDispStoreInsts 5741000 # Number of dispatched store instructions
|
system.cpu.iew.iewDispStoreInsts 5741000 # Number of dispatched store instructions
|
||||||
system.cpu.iew.iewDispNonSpecInsts 643936 # Number of dispatched non-speculative instructions
|
system.cpu.iew.iewDispNonSpecInsts 643936 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.iew.iewIQFullEvents 9429 # Number of times the IQ has become full, causing a stall
|
system.cpu.iew.iewIQFullEvents 9429 # Number of times the IQ has become full, causing a stall
|
||||||
|
@ -265,17 +265,17 @@ system.cpu.iew.memOrderViolationEvents 731 # Nu
|
||||||
system.cpu.iew.predictedTakenIncorrect 1288873 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 1288873 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 210071 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 210071 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 1498944 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 1498944 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 104530426 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 104530427 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 25743276 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 25743276 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 1631616 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 1631624 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 38806 # number of nop insts executed
|
system.cpu.iew.exec_nop 38806 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 30946109 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 30946109 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 21214083 # Number of branches executed
|
system.cpu.iew.exec_branches 21214083 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 5202833 # Number of stores executed
|
system.cpu.iew.exec_stores 5202833 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 1.579937 # Inst execution rate
|
system.cpu.iew.exec_rate 1.579937 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 102941811 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 102941812 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 102521541 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 102521542 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 60312663 # num instructions producing a value
|
system.cpu.iew.wb_producers 60312663 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 96996327 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 96996327 # num instructions consuming a value
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
|
@ -283,7 +283,7 @@ system.cpu.iew.wb_rate 1.549573 # in
|
||||||
system.cpu.iew.wb_fanout 0.621804 # average fanout of values written-back
|
system.cpu.iew.wb_fanout 0.621804 # average fanout of values written-back
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.commit.commitCommittedInsts 91262494 # The number of committed instructions
|
system.cpu.commit.commitCommittedInsts 91262494 # The number of committed instructions
|
||||||
system.cpu.commit.commitSquashedInsts 26696986 # The number of squashed insts skipped by commit
|
system.cpu.commit.commitSquashedInsts 26696996 # The number of squashed insts skipped by commit
|
||||||
system.cpu.commit.commitNonSpecStalls 554844 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu.commit.commitNonSpecStalls 554844 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.commit.branchMispredicts 1392644 # The number of times a branch was mispredicted
|
system.cpu.commit.branchMispredicts 1392644 # The number of times a branch was mispredicted
|
||||||
system.cpu.commit.committed_per_cycle::samples 62124345 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::samples 62124345 # Number of insts commited each cycle
|
||||||
|
@ -314,42 +314,42 @@ system.cpu.commit.int_insts 72533302 # Nu
|
||||||
system.cpu.commit.function_calls 56148 # Number of function calls committed.
|
system.cpu.commit.function_calls 56148 # Number of function calls committed.
|
||||||
system.cpu.commit.bw_lim_events 4531141 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 4531141 # number cycles where commit BW limit reached
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.rob.rob_reads 175546950 # The number of ROB reads
|
system.cpu.rob.rob_reads 175546960 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 239939834 # The number of ROB writes
|
system.cpu.rob.rob_writes 239939856 # The number of ROB writes
|
||||||
system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 29796 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 29796 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu.committedInsts 91249885 # Number of Instructions Simulated
|
system.cpu.committedInsts 91249885 # Number of Instructions Simulated
|
||||||
system.cpu.committedInsts_total 91249885 # Number of Instructions Simulated
|
system.cpu.committedInsts_total 91249885 # Number of Instructions Simulated
|
||||||
system.cpu.cpi 0.725054 # CPI: Cycles Per Instruction
|
system.cpu.cpi 0.725055 # CPI: Cycles Per Instruction
|
||||||
system.cpu.cpi_total 0.725054 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 0.725055 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 1.379207 # IPC: Instructions Per Cycle
|
system.cpu.ipc 1.379207 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 1.379207 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 1.379207 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 496902731 # number of integer regfile reads
|
system.cpu.int_regfile_reads 496902735 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 120936097 # number of integer regfile writes
|
system.cpu.int_regfile_writes 120936098 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 197 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 197 # number of floating regfile reads
|
||||||
system.cpu.fp_regfile_writes 534 # number of floating regfile writes
|
system.cpu.fp_regfile_writes 534 # number of floating regfile writes
|
||||||
system.cpu.misc_regfile_reads 184886725 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 184886717 # number of misc regfile reads
|
||||||
system.cpu.misc_regfile_writes 11594 # number of misc regfile writes
|
system.cpu.misc_regfile_writes 11594 # number of misc regfile writes
|
||||||
system.cpu.icache.replacements 2 # number of replacements
|
system.cpu.icache.replacements 2 # number of replacements
|
||||||
system.cpu.icache.tagsinuse 611.587678 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 611.587679 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 14743812 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 14743811 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.avg_refs 20420.792244 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 20420.790859 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.occ_blocks::0 611.587678 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 611.587679 # Average occupied blocks per context
|
||||||
system.cpu.icache.occ_percent::0 0.298627 # Average percentage of cache occupancy
|
system.cpu.icache.occ_percent::0 0.298627 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.ReadReq_hits 14743812 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 14743811 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits 14743812 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 14743811 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits 14743812 # number of overall hits
|
system.cpu.icache.overall_hits 14743811 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses 916 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 916 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses 916 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 916 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses 916 # number of overall misses
|
system.cpu.icache.overall_misses 916 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 32376000 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 32376000 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency 32376000 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 32376000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency 32376000 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 32376000 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses 14744728 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 14744727 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses 14744728 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 14744727 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses 14744728 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 14744727 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000062 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000062 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate 0.000062 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000062 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate 0.000062 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000062 # miss rate for overall accesses
|
||||||
|
@ -387,45 +387,45 @@ system.cpu.icache.mshr_cap_events 0 # nu
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.replacements 943456 # number of replacements
|
system.cpu.dcache.replacements 943456 # number of replacements
|
||||||
system.cpu.dcache.tagsinuse 3558.808717 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 3558.808733 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 28819274 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 28819271 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.sampled_refs 947552 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 947552 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.avg_refs 30.414451 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 30.414448 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 12353041000 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 12353041000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.occ_blocks::0 3558.808717 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 3558.808733 # Average occupied blocks per context
|
||||||
system.cpu.dcache.occ_percent::0 0.868850 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_percent::0 0.868850 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.ReadReq_hits 24247443 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 24247440 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits 4559242 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 4559242 # number of WriteReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits 6797 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits 6797 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits 5792 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits 5792 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.demand_hits 28806685 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 28806682 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits 28806685 # number of overall hits
|
system.cpu.dcache.overall_hits 28806682 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses 989267 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 989267 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses 175739 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 175739 # number of WriteReq misses
|
||||||
system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses
|
system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses
|
||||||
system.cpu.dcache.demand_misses 1165006 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 1165006 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses 1165006 # number of overall misses
|
system.cpu.dcache.overall_misses 1165006 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency 5475542500 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 5475545000 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency 4498706928 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 4498707428 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency 9974249428 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 9974252428 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency 9974249428 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 9974252428 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses 25236710 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 25236707 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses 6804 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses 6804 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses 5792 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses 5792 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses 29971691 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 29971688 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses 29971691 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 29971688 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.039200 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.039200 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.037115 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.037115 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.001029 # miss rate for LoadLockedReq accesses
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.001029 # miss rate for LoadLockedReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate 0.038870 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.038870 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate 0.038870 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.038870 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 5534.949109 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 5534.951636 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 25598.796670 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 25598.799515 # average WriteReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency 8561.543398 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 8561.545973 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency 8561.543398 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 8561.545973 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 23239503 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 23239503 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 8123 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 8123 # number of cycles access was blocked
|
||||||
|
@ -445,31 +445,31 @@ system.cpu.dcache.WriteReq_mshr_misses 44526 # nu
|
||||||
system.cpu.dcache.demand_mshr_misses 947553 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 947553 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses 947553 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 947553 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2253075000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 2253076500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1081062556 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 1081063056 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 3334137556 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 3334139556 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 3334137556 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 3334139556 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.035782 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.035782 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009404 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009404 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.031615 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.031615 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.031615 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.031615 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2495.025066 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2495.026727 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24279.354894 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24279.366123 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3518.681864 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 3518.683974 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3518.681864 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 3518.683974 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.replacements 744 # number of replacements
|
system.cpu.l2cache.replacements 744 # number of replacements
|
||||||
system.cpu.l2cache.tagsinuse 9229.669539 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 9229.669691 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 1596774 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 1596774 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.sampled_refs 15569 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 15569 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 102.561115 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 102.561115 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.occ_blocks::0 392.792284 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 392.792276 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 8836.877255 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 8836.877415 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.011987 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.011987 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.269680 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.269680 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.ReadReq_hits 901413 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 901413 # number of ReadReq hits
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=false
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=System
|
type=System
|
||||||
children=cpu membus physmem
|
children=cpu membus physmem
|
||||||
|
boot_osflags=a
|
||||||
|
init_param=0
|
||||||
|
kernel=
|
||||||
|
load_addr_mask=1099511627775
|
||||||
mem_mode=atomic
|
mem_mode=atomic
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
|
readfile=
|
||||||
|
symbolfile=
|
||||||
work_begin_ckpt_count=0
|
work_begin_ckpt_count=0
|
||||||
work_begin_cpu_id_exit=-1
|
work_begin_cpu_id_exit=-1
|
||||||
work_begin_exit_count=0
|
work_begin_exit_count=0
|
||||||
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
type=DerivO3CPU
|
type=DerivO3CPU
|
||||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||||
BTBEntries=4096
|
BTBEntries=4096
|
||||||
BTBTagSize=16
|
BTBTagSize=16
|
||||||
LFSTSize=1024
|
LFSTSize=1024
|
||||||
|
@ -52,6 +59,7 @@ decodeWidth=8
|
||||||
defer_registration=false
|
defer_registration=false
|
||||||
dispatchWidth=8
|
dispatchWidth=8
|
||||||
do_checkpoint_insts=true
|
do_checkpoint_insts=true
|
||||||
|
do_quiesce=true
|
||||||
do_statistics_insts=true
|
do_statistics_insts=true
|
||||||
dtb=system.cpu.dtb
|
dtb=system.cpu.dtb
|
||||||
fetchToDecodeDelay=1
|
fetchToDecodeDelay=1
|
||||||
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
||||||
iewToFetchDelay=1
|
iewToFetchDelay=1
|
||||||
iewToRenameDelay=1
|
iewToRenameDelay=1
|
||||||
instShiftAmt=2
|
instShiftAmt=2
|
||||||
|
interrupts=system.cpu.interrupts
|
||||||
issueToExecuteDelay=1
|
issueToExecuteDelay=1
|
||||||
issueWidth=8
|
issueWidth=8
|
||||||
itb=system.cpu.itb
|
itb=system.cpu.itb
|
||||||
|
@ -89,6 +98,7 @@ numRobs=1
|
||||||
numThreads=1
|
numThreads=1
|
||||||
phase=0
|
phase=0
|
||||||
predType=tournament
|
predType=tournament
|
||||||
|
profile=0
|
||||||
progress_interval=0
|
progress_interval=0
|
||||||
renameToDecodeDelay=1
|
renameToDecodeDelay=1
|
||||||
renameToFetchDelay=1
|
renameToFetchDelay=1
|
||||||
|
@ -149,7 +159,14 @@ mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
[system.cpu.dtb]
|
[system.cpu.dtb]
|
||||||
type=X86TLB
|
type=X86TLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.dtb.walker
|
||||||
|
|
||||||
|
[system.cpu.dtb.walker]
|
||||||
|
type=X86PagetableWalker
|
||||||
|
system=system
|
||||||
|
port=system.cpu.toL2Bus.port[3]
|
||||||
|
|
||||||
[system.cpu.fuPool]
|
[system.cpu.fuPool]
|
||||||
type=FUPool
|
type=FUPool
|
||||||
|
@ -446,9 +463,25 @@ write_buffers=8
|
||||||
cpu_side=system.cpu.icache_port
|
cpu_side=system.cpu.icache_port
|
||||||
mem_side=system.cpu.toL2Bus.port[0]
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.interrupts]
|
||||||
|
type=X86LocalApic
|
||||||
|
int_latency=1000
|
||||||
|
pio_addr=2305843009213693952
|
||||||
|
pio_latency=1000
|
||||||
|
system=system
|
||||||
|
int_port=system.membus.port[4]
|
||||||
|
pio=system.membus.port[3]
|
||||||
|
|
||||||
[system.cpu.itb]
|
[system.cpu.itb]
|
||||||
type=X86TLB
|
type=X86TLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.itb.walker
|
||||||
|
|
||||||
|
[system.cpu.itb.walker]
|
||||||
|
type=X86PagetableWalker
|
||||||
|
system=system
|
||||||
|
port=system.cpu.toL2Bus.port[2]
|
||||||
|
|
||||||
[system.cpu.l2cache]
|
[system.cpu.l2cache]
|
||||||
type=BaseCache
|
type=BaseCache
|
||||||
|
@ -479,7 +512,7 @@ tgts_per_mshr=5
|
||||||
trace_addr=0
|
trace_addr=0
|
||||||
two_queue=false
|
two_queue=false
|
||||||
write_buffers=8
|
write_buffers=8
|
||||||
cpu_side=system.cpu.toL2Bus.port[2]
|
cpu_side=system.cpu.toL2Bus.port[4]
|
||||||
mem_side=system.membus.port[2]
|
mem_side=system.membus.port[2]
|
||||||
|
|
||||||
[system.cpu.toL2Bus]
|
[system.cpu.toL2Bus]
|
||||||
|
@ -490,7 +523,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
[system.cpu.tracer]
|
[system.cpu.tracer]
|
||||||
type=ExeTracer
|
type=ExeTracer
|
||||||
|
@ -498,7 +531,7 @@ type=ExeTracer
|
||||||
[system.cpu.workload]
|
[system.cpu.workload]
|
||||||
type=LiveProcess
|
type=LiveProcess
|
||||||
cmd=mcf mcf.in
|
cmd=mcf mcf.in
|
||||||
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
|
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||||
egid=100
|
egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
|
@ -522,7 +555,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||||
|
|
||||||
[system.physmem]
|
[system.physmem]
|
||||||
type=PhysicalMemory
|
type=PhysicalMemory
|
||||||
|
|
|
@ -1,12 +1,12 @@
|
||||||
Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simout
|
Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
|
||||||
Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simerr
|
Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 28 2012 12:11:40
|
gem5 compiled Feb 9 2012 12:45:55
|
||||||
gem5 started Jan 28 2012 12:12:43
|
gem5 started Feb 9 2012 12:46:40
|
||||||
gem5 executing on ribera.cs.wisc.edu
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
|
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
|
||||||
|
@ -25,4 +25,4 @@ simplex iterations : 2663
|
||||||
flow value : 3080014995
|
flow value : 3080014995
|
||||||
checksum : 68389
|
checksum : 68389
|
||||||
optimal
|
optimal
|
||||||
Exiting @ tick 70097938500 because target called exit()
|
Exiting @ tick 70046988500 because target called exit()
|
||||||
|
|
|
@ -1,262 +1,262 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.070098 # Number of seconds simulated
|
sim_seconds 0.070047 # Number of seconds simulated
|
||||||
sim_ticks 70097938500 # Number of ticks simulated
|
sim_ticks 70046988500 # Number of ticks simulated
|
||||||
final_tick 70097938500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 70046988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 110386 # Simulator instruction rate (inst/s)
|
host_inst_rate 78701 # Simulator instruction rate (inst/s)
|
||||||
host_tick_rate 27814669 # Simulator tick rate (ticks/s)
|
host_tick_rate 19816485 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 379416 # Number of bytes of host memory used
|
host_mem_usage 388420 # Number of bytes of host memory used
|
||||||
host_seconds 2520.18 # Real time elapsed on the host
|
host_seconds 3534.78 # Real time elapsed on the host
|
||||||
sim_insts 278192519 # Number of instructions simulated
|
sim_insts 278192519 # Number of instructions simulated
|
||||||
system.physmem.bytes_read 3896128 # Number of bytes read from this memory
|
system.physmem.bytes_read 3895936 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read 65152 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read 65216 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written 892416 # Number of bytes written to this memory
|
system.physmem.bytes_written 892288 # Number of bytes written to this memory
|
||||||
system.physmem.num_reads 60877 # Number of read requests responded to by this memory
|
system.physmem.num_reads 60874 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes 13944 # Number of write requests responded to by this memory
|
system.physmem.num_writes 13942 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||||
system.physmem.bw_read 55581207 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read 55618894 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read 929442 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read 931032 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write 12730988 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write 12738421 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total 68312194 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total 68357314 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||||
system.cpu.numCycles 140195878 # number of cpu cycles simulated
|
system.cpu.numCycles 140093978 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.BPredUnit.lookups 37928407 # Number of BP lookups
|
system.cpu.BPredUnit.lookups 37937752 # Number of BP lookups
|
||||||
system.cpu.BPredUnit.condPredicted 37928407 # Number of conditional branches predicted
|
system.cpu.BPredUnit.condPredicted 37937752 # Number of conditional branches predicted
|
||||||
system.cpu.BPredUnit.condIncorrect 1334678 # Number of conditional branches incorrect
|
system.cpu.BPredUnit.condIncorrect 1331995 # Number of conditional branches incorrect
|
||||||
system.cpu.BPredUnit.BTBLookups 33548417 # Number of BTB lookups
|
system.cpu.BPredUnit.BTBLookups 33815417 # Number of BTB lookups
|
||||||
system.cpu.BPredUnit.BTBHits 33040245 # Number of BTB hits
|
system.cpu.BPredUnit.BTBHits 33320649 # Number of BTB hits
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 29060209 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 29024363 # Number of cycles fetch is stalled on an Icache miss
|
||||||
system.cpu.fetch.Insts 203598338 # Number of instructions fetch has processed
|
system.cpu.fetch.Insts 203514307 # Number of instructions fetch has processed
|
||||||
system.cpu.fetch.Branches 37928407 # Number of branches that fetch encountered
|
system.cpu.fetch.Branches 37937752 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 33040245 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 33320649 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.Cycles 63274026 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.fetch.Cycles 63466806 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
system.cpu.fetch.SquashCycles 10249926 # Number of cycles fetch has spent squashing
|
system.cpu.fetch.SquashCycles 10233892 # Number of cycles fetch has spent squashing
|
||||||
system.cpu.fetch.BlockedCycles 38189577 # Number of cycles fetch has spent blocked
|
system.cpu.fetch.BlockedCycles 37945043 # Number of cycles fetch has spent blocked
|
||||||
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
system.cpu.fetch.PendingTrapStallCycles 77 # Number of stall cycles due to pending traps
|
system.cpu.fetch.PendingTrapStallCycles 68 # Number of stall cycles due to pending traps
|
||||||
system.cpu.fetch.CacheLines 28245503 # Number of cache lines fetched
|
system.cpu.fetch.CacheLines 28213885 # Number of cache lines fetched
|
||||||
system.cpu.fetch.IcacheSquashes 214193 # Number of outstanding Icache misses that were squashed
|
system.cpu.fetch.IcacheSquashes 212642 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 139407654 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 139306492 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.577879 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.579216 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 3.292775 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 3.290579 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::0 78584615 56.37% 56.37% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::0 78286088 56.20% 56.20% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::1 3556242 2.55% 58.92% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::1 3759512 2.70% 58.90% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::2 2802198 2.01% 60.93% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::2 2809249 2.02% 60.91% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::3 4529245 3.25% 64.18% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::3 4511465 3.24% 64.15% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::4 6913485 4.96% 69.14% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::4 7046412 5.06% 69.21% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::5 5169478 3.71% 72.85% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::5 5071327 3.64% 72.85% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::6 7697084 5.52% 78.37% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::6 7671850 5.51% 78.36% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::7 4298531 3.08% 81.45% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::7 4389018 3.15% 81.51% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::8 25856776 18.55% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::8 25761571 18.49% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 139407654 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 139306492 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.branchRate 0.270539 # Number of branch fetches per cycle
|
system.cpu.fetch.branchRate 0.270802 # Number of branch fetches per cycle
|
||||||
system.cpu.fetch.rate 1.452242 # Number of inst fetches per cycle
|
system.cpu.fetch.rate 1.452698 # Number of inst fetches per cycle
|
||||||
system.cpu.decode.IdleCycles 41988791 # Number of cycles decode is idle
|
system.cpu.decode.IdleCycles 41961886 # Number of cycles decode is idle
|
||||||
system.cpu.decode.BlockedCycles 28417024 # Number of cycles decode is blocked
|
system.cpu.decode.BlockedCycles 28163540 # Number of cycles decode is blocked
|
||||||
system.cpu.decode.RunCycles 52030953 # Number of cycles decode is running
|
system.cpu.decode.RunCycles 52299140 # Number of cycles decode is running
|
||||||
system.cpu.decode.UnblockCycles 8087139 # Number of cycles decode is unblocking
|
system.cpu.decode.UnblockCycles 8011732 # Number of cycles decode is unblocking
|
||||||
system.cpu.decode.SquashCycles 8883747 # Number of cycles decode is squashing
|
system.cpu.decode.SquashCycles 8870194 # Number of cycles decode is squashing
|
||||||
system.cpu.decode.DecodedInsts 355040007 # Number of instructions handled by decode
|
system.cpu.decode.DecodedInsts 354926885 # Number of instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 8883747 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 8870194 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 48483810 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 48488899 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 4810408 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 4721769 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 9079 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 9082 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 52929871 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 53110553 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 24290739 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 24105995 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 350051728 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 349921643 # Number of instructions processed by rename
|
||||||
system.cpu.rename.ROBFullEvents 20 # Number of times rename has blocked due to ROB full
|
system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.rename.IQFullEvents 103496 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 105361 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LSQFullEvents 20366187 # Number of times rename has blocked due to LSQ full
|
system.cpu.rename.LSQFullEvents 20166032 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.rename.RenamedOperands 314282471 # Number of destination operands rename has renamed
|
system.cpu.rename.RenamedOperands 314159745 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenameLookups 860902327 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenameLookups 860584858 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.int_rename_lookups 860897388 # Number of integer rename lookups
|
system.cpu.rename.int_rename_lookups 860581891 # Number of integer rename lookups
|
||||||
system.cpu.rename.fp_rename_lookups 4939 # Number of floating rename lookups
|
system.cpu.rename.fp_rename_lookups 2967 # Number of floating rename lookups
|
||||||
system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed
|
system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed
|
||||||
system.cpu.rename.UndoneMaps 65938279 # Number of HB maps that are undone due to squashing
|
system.cpu.rename.UndoneMaps 65815553 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.rename.serializingInsts 478 # count of serializing insts renamed
|
system.cpu.rename.serializingInsts 479 # count of serializing insts renamed
|
||||||
system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed
|
system.cpu.rename.tempSerializingInsts 473 # count of temporary serializing insts renamed
|
||||||
system.cpu.rename.skidInsts 57634584 # count of insts added to the skid buffer
|
system.cpu.rename.skidInsts 57293063 # count of insts added to the skid buffer
|
||||||
system.cpu.memDep0.insertedLoads 112617334 # Number of loads inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedLoads 112603571 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.insertedStores 37601195 # Number of stores inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedStores 37556545 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.conflictingLoads 47838969 # Number of conflicting loads.
|
system.cpu.memDep0.conflictingLoads 47800126 # Number of conflicting loads.
|
||||||
system.cpu.memDep0.conflictingStores 8379867 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 8208845 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 343415839 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 343290045 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 2328 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 2336 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 316096096 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 316029105 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 78808 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 76885 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 65029362 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 64917017 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 92942153 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 92716043 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 1882 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.iqSquashedNonSpecRemoved 1890 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.iq.issued_per_cycle::samples 139407654 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::samples 139306492 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::mean 2.267423 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 2.268588 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.745481 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.744230 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 32098361 23.02% 23.02% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 32068137 23.02% 23.02% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 17868067 12.82% 35.84% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 17712067 12.71% 35.73% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 24417482 17.52% 53.36% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 24423194 17.53% 53.27% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 32093883 23.02% 76.38% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 32289069 23.18% 76.44% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 18421218 13.21% 89.59% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 18335734 13.16% 89.61% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::5 9527374 6.83% 96.43% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::5 9491103 6.81% 96.42% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::6 3128162 2.24% 98.67% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::6 3154604 2.26% 98.68% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::7 1804154 1.29% 99.96% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::7 1783304 1.28% 99.96% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::8 48953 0.04% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::8 49280 0.04% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::total 139407654 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::total 139306492 # Number of insts issued each cycle
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntAlu 25731 1.31% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntAlu 25569 1.30% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntMult 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.30% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemRead 1863505 95.00% 96.31% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemRead 1859415 94.86% 96.17% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemWrite 72393 3.69% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemWrite 75095 3.83% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 180196286 57.01% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 180131547 57.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatAdd 342 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatAdd 149 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 101438567 32.09% 89.10% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 101432595 32.10% 89.10% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 34444190 10.90% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 34448103 10.90% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 316096096 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 316029105 # Type of FU issued
|
||||||
system.cpu.iq.rate 2.254675 # Inst issue rate
|
system.cpu.iq.rate 2.255836 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 1961629 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 1960079 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.006206 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.006202 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 773638738 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 773400844 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 408477370 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 408240794 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 312370165 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 312293905 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 1545 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 822 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 3169 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 1922 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 656 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 316 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 318040246 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 317972066 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 768 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 407 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 52318776 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 52311971 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 21837946 # Number of loads squashed
|
system.cpu.iew.lsq.thread0.squashedLoads 21824183 # Number of loads squashed
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 139826 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iew.lsq.thread0.ignoredResponses 143830 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 33737 # Number of memory ordering violations
|
system.cpu.iew.lsq.thread0.memOrderViolation 34021 # Number of memory ordering violations
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 6161444 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 6116794 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 3258 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 3244 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 3821 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 3822 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 8883747 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 8870194 # Number of cycles IEW is squashing
|
||||||
system.cpu.iew.iewBlockCycles 984872 # Number of cycles IEW is blocking
|
system.cpu.iew.iewBlockCycles 981730 # Number of cycles IEW is blocking
|
||||||
system.cpu.iew.iewUnblockCycles 88741 # Number of cycles IEW is unblocking
|
system.cpu.iew.iewUnblockCycles 88786 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iew.iewDispatchedInsts 343418167 # Number of instructions dispatched to IQ
|
system.cpu.iew.iewDispatchedInsts 343292381 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iew.iewDispSquashedInsts 39651 # Number of squashed instructions skipped by dispatch
|
system.cpu.iew.iewDispSquashedInsts 39929 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iew.iewDispLoadInsts 112617334 # Number of dispatched load instructions
|
system.cpu.iew.iewDispLoadInsts 112603571 # Number of dispatched load instructions
|
||||||
system.cpu.iew.iewDispStoreInsts 37601195 # Number of dispatched store instructions
|
system.cpu.iew.iewDispStoreInsts 37556545 # Number of dispatched store instructions
|
||||||
system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
|
system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.iew.iewIQFullEvents 1341 # Number of times the IQ has become full, causing a stall
|
system.cpu.iew.iewIQFullEvents 1316 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.iew.iewLSQFullEvents 42673 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iew.iewLSQFullEvents 42406 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.iew.memOrderViolationEvents 33737 # Number of memory order violations
|
system.cpu.iew.memOrderViolationEvents 34021 # Number of memory order violations
|
||||||
system.cpu.iew.predictedTakenIncorrect 1237180 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 1234482 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 215729 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 211725 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 1452909 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 1446207 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 313907375 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 313835720 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 100815222 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 100810143 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 2188721 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 2193385 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 134855811 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 134854161 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 31730666 # Number of branches executed
|
system.cpu.iew.exec_branches 31726163 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 34040589 # Number of stores executed
|
system.cpu.iew.exec_stores 34044018 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 2.239063 # Inst execution rate
|
system.cpu.iew.exec_rate 2.240180 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 313087219 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 313006075 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 312370821 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 312294221 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 231825034 # num instructions producing a value
|
system.cpu.iew.wb_producers 231754622 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 317282535 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 317218208 # num instructions consuming a value
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.iew.wb_rate 2.228103 # insts written-back per cycle
|
system.cpu.iew.wb_rate 2.229177 # insts written-back per cycle
|
||||||
system.cpu.iew.wb_fanout 0.730658 # average fanout of values written-back
|
system.cpu.iew.wb_fanout 0.730584 # average fanout of values written-back
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
|
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
|
||||||
system.cpu.commit.commitSquashedInsts 65229233 # The number of squashed insts skipped by commit
|
system.cpu.commit.commitSquashedInsts 65103374 # The number of squashed insts skipped by commit
|
||||||
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.commit.branchMispredicts 1334689 # The number of times a branch was mispredicted
|
system.cpu.commit.branchMispredicts 1332005 # The number of times a branch was mispredicted
|
||||||
system.cpu.commit.committed_per_cycle::samples 130523907 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::samples 130436298 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::mean 2.131353 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::mean 2.132785 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::stdev 2.650695 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::stdev 2.651894 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::0 49374885 37.83% 37.83% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::0 49351461 37.84% 37.84% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::1 24990571 19.15% 56.97% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::1 24978168 19.15% 56.99% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::2 17165469 13.15% 70.13% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::2 17073618 13.09% 70.08% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::3 12454302 9.54% 79.67% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::3 12436945 9.53% 79.61% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::4 3472302 2.66% 82.33% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::4 3526211 2.70% 82.31% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::5 3453203 2.65% 84.97% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::5 3453253 2.65% 84.96% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::6 2713996 2.08% 87.05% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::6 2711146 2.08% 87.04% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::7 1124527 0.86% 87.91% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::7 1125673 0.86% 87.90% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::8 15774652 12.09% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::8 15779823 12.10% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::total 130523907 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::total 130436298 # Number of insts commited each cycle
|
||||||
system.cpu.commit.count 278192519 # Number of instructions committed
|
system.cpu.commit.count 278192519 # Number of instructions committed
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.commit.refs 122219139 # Number of memory references committed
|
system.cpu.commit.refs 122219139 # Number of memory references committed
|
||||||
|
@ -266,49 +266,49 @@ system.cpu.commit.branches 29309710 # Nu
|
||||||
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
|
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
|
||||||
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
|
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
|
||||||
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
||||||
system.cpu.commit.bw_lim_events 15774652 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 15779823 # number cycles where commit BW limit reached
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.rob.rob_reads 458171007 # The number of ROB reads
|
system.cpu.rob.rob_reads 457952368 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 695745355 # The number of ROB writes
|
system.cpu.rob.rob_writes 695479183 # The number of ROB writes
|
||||||
system.cpu.timesIdled 23904 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 23894 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 788224 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 787486 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu.committedInsts 278192519 # Number of Instructions Simulated
|
system.cpu.committedInsts 278192519 # Number of Instructions Simulated
|
||||||
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
|
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
|
||||||
system.cpu.cpi 0.503953 # CPI: Cycles Per Instruction
|
system.cpu.cpi 0.503586 # CPI: Cycles Per Instruction
|
||||||
system.cpu.cpi_total 0.503953 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 0.503586 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 1.984313 # IPC: Instructions Per Cycle
|
system.cpu.ipc 1.985756 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 1.984313 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 1.985756 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 554439426 # number of integer regfile reads
|
system.cpu.int_regfile_reads 554395898 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 279882097 # number of integer regfile writes
|
system.cpu.int_regfile_writes 279799467 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 791 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 352 # number of floating regfile reads
|
||||||
system.cpu.fp_regfile_writes 562 # number of floating regfile writes
|
system.cpu.fp_regfile_writes 262 # number of floating regfile writes
|
||||||
system.cpu.misc_regfile_reads 200975844 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 200946158 # number of misc regfile reads
|
||||||
system.cpu.icache.replacements 62 # number of replacements
|
system.cpu.icache.replacements 64 # number of replacements
|
||||||
system.cpu.icache.tagsinuse 823.089414 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 822.534021 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 28244206 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 28212585 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.sampled_refs 1023 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 1024 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.avg_refs 27609.194526 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 27551.352539 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.occ_blocks::0 823.089414 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 822.534021 # Average occupied blocks per context
|
||||||
system.cpu.icache.occ_percent::0 0.401899 # Average percentage of cache occupancy
|
system.cpu.icache.occ_percent::0 0.401628 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.ReadReq_hits 28244206 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 28212585 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits 28244206 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 28212585 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits 28244206 # number of overall hits
|
system.cpu.icache.overall_hits 28212585 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses 1297 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 1300 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses 1297 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 1300 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses 1297 # number of overall misses
|
system.cpu.icache.overall_misses 1300 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 46884000 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 46952500 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency 46884000 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 46952500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency 46884000 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 46952500 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses 28245503 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 28213885 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses 28245503 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 28213885 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses 28245503 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 28213885 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 36148.033924 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 36117.307692 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency 36148.033924 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 36117.307692 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency 36148.033924 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 36117.307692 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -318,59 +318,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_mshr_hits 273 # number of ReadReq MSHR hits
|
system.cpu.icache.ReadReq_mshr_hits 275 # number of ReadReq MSHR hits
|
||||||
system.cpu.icache.demand_mshr_hits 273 # number of demand (read+write) MSHR hits
|
system.cpu.icache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.icache.overall_mshr_hits 273 # number of overall MSHR hits
|
system.cpu.icache.overall_mshr_hits 275 # number of overall MSHR hits
|
||||||
system.cpu.icache.ReadReq_mshr_misses 1024 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 1025 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.demand_mshr_misses 1024 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses 1025 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses 1024 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses 1025 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 36044000 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency 36071500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency 36044000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency 36071500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency 36044000 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency 36071500 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35199.218750 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35191.707317 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 35199.218750 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 35191.707317 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 35199.218750 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 35191.707317 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.replacements 2072801 # number of replacements
|
system.cpu.dcache.replacements 2072906 # number of replacements
|
||||||
system.cpu.dcache.tagsinuse 4073.016957 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 4073.029614 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 77487718 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 77489413 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.sampled_refs 2076897 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 2077002 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.avg_refs 37.309370 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 37.308300 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 23652058000 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 23588256000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.occ_blocks::0 4073.016957 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 4073.029614 # Average occupied blocks per context
|
||||||
system.cpu.dcache.occ_percent::0 0.994389 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_percent::0 0.994392 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.ReadReq_hits 46133976 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 46135653 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits 31353733 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 31353751 # number of WriteReq hits
|
||||||
system.cpu.dcache.demand_hits 77487709 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 77489404 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits 77487709 # number of overall hits
|
system.cpu.dcache.overall_hits 77489404 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses 2288597 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 2289012 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses 86018 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 86000 # number of WriteReq misses
|
||||||
system.cpu.dcache.demand_misses 2374615 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 2375012 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses 2374615 # number of overall misses
|
system.cpu.dcache.overall_misses 2375012 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency 13760644500 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 13766771000 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency 1501321288 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 1501245288 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency 15261965788 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 15268016288 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency 15261965788 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 15268016288 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses 48422573 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 48424665 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses 79862324 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 79864416 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses 79862324 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 79864416 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.047263 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.047270 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.002736 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.002735 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate 0.029734 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.029738 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate 0.029734 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.029738 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 6012.698828 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 6014.285203 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 17453.571206 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 17456.340558 # average WriteReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency 6427.132730 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 6428.605956 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency 6427.132730 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 6428.605956 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -379,72 +379,72 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks 1880524 # number of writebacks
|
system.cpu.dcache.writebacks 1880780 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 293812 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits 294089 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 3902 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits 3918 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits 297714 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 298007 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits 297714 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 298007 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 1994785 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 1994923 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 82116 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 82082 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses 2076901 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 2077005 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses 2076901 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 2077005 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 5560782500 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 5565133500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1157739288 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 1157645788 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 6718521788 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 6722779288 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 6718521788 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 6722779288 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.041195 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.041196 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002612 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002611 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.026006 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.026007 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.026006 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.026007 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2787.660074 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2789.648272 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14098.827123 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14103.528033 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3234.878209 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 3236.766059 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3234.878209 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 3236.766059 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.replacements 33248 # number of replacements
|
system.cpu.l2cache.replacements 33246 # number of replacements
|
||||||
system.cpu.l2cache.tagsinuse 18948.902283 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 18964.988080 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 3764067 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 3764517 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.sampled_refs 61254 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 61253 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 61.450142 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 61.458492 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.occ_blocks::0 6031.150094 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 6037.038666 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 12917.752189 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 12927.949414 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.184056 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.184236 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.394219 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.394530 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.ReadReq_hits 1964318 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 1964445 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits 1880524 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 1880780 # number of Writeback hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 52728 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits 52709 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits 2017046 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 2017154 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits 2017046 # number of overall hits
|
system.cpu.l2cache.overall_hits 2017154 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses 31362 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 31361 # number of ReadReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses 29515 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 29513 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses 60877 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 60874 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses 60877 # number of overall misses
|
system.cpu.l2cache.overall_misses 60874 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 1071112000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 1071202500 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 1006258500 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 1006190000 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency 2077370500 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 2077392500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency 2077370500 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 2077392500 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses 1995680 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 1995806 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses 1880524 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 1880780 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses 82243 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 82222 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses 2077923 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 2078028 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 2077923 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 2078028 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.015715 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.015713 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.358876 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 0.358943 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate 0.029297 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.029294 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate 0.029297 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.029294 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34153.179006 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34157.153790 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34093.122141 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34093.111510 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34124.061632 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 34126.104741 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34124.061632 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34126.104741 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -453,31 +453,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.writebacks 13944 # number of writebacks
|
system.cpu.l2cache.writebacks 13942 # number of writebacks
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 31362 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 31361 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 29515 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 29513 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses 60877 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 60874 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses 60877 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 60874 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 972890000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 972854000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 914988000 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 914925500 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 1887878000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 1887779500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 1887878000 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 1887779500 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.015715 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.015713 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.358876 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.358943 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.029297 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.029294 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.029297 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.029294 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.299662 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.140907 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.779265 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.762376 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31011.350756 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31011.260965 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31011.350756 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31011.260965 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=false
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=System
|
type=System
|
||||||
children=cpu membus physmem
|
children=cpu membus physmem
|
||||||
|
boot_osflags=a
|
||||||
|
init_param=0
|
||||||
|
kernel=
|
||||||
|
load_addr_mask=1099511627775
|
||||||
mem_mode=atomic
|
mem_mode=atomic
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
|
readfile=
|
||||||
|
symbolfile=
|
||||||
work_begin_ckpt_count=0
|
work_begin_ckpt_count=0
|
||||||
work_begin_cpu_id_exit=-1
|
work_begin_cpu_id_exit=-1
|
||||||
work_begin_exit_count=0
|
work_begin_exit_count=0
|
||||||
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
type=DerivO3CPU
|
type=DerivO3CPU
|
||||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||||
BTBEntries=4096
|
BTBEntries=4096
|
||||||
BTBTagSize=16
|
BTBTagSize=16
|
||||||
LFSTSize=1024
|
LFSTSize=1024
|
||||||
|
@ -52,6 +59,7 @@ decodeWidth=8
|
||||||
defer_registration=false
|
defer_registration=false
|
||||||
dispatchWidth=8
|
dispatchWidth=8
|
||||||
do_checkpoint_insts=true
|
do_checkpoint_insts=true
|
||||||
|
do_quiesce=true
|
||||||
do_statistics_insts=true
|
do_statistics_insts=true
|
||||||
dtb=system.cpu.dtb
|
dtb=system.cpu.dtb
|
||||||
fetchToDecodeDelay=1
|
fetchToDecodeDelay=1
|
||||||
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
||||||
iewToFetchDelay=1
|
iewToFetchDelay=1
|
||||||
iewToRenameDelay=1
|
iewToRenameDelay=1
|
||||||
instShiftAmt=2
|
instShiftAmt=2
|
||||||
|
interrupts=system.cpu.interrupts
|
||||||
issueToExecuteDelay=1
|
issueToExecuteDelay=1
|
||||||
issueWidth=8
|
issueWidth=8
|
||||||
itb=system.cpu.itb
|
itb=system.cpu.itb
|
||||||
|
@ -80,6 +89,7 @@ max_insts_all_threads=0
|
||||||
max_insts_any_thread=0
|
max_insts_any_thread=0
|
||||||
max_loads_all_threads=0
|
max_loads_all_threads=0
|
||||||
max_loads_any_thread=0
|
max_loads_any_thread=0
|
||||||
|
needsTSO=false
|
||||||
numIQEntries=64
|
numIQEntries=64
|
||||||
numPhysFloatRegs=256
|
numPhysFloatRegs=256
|
||||||
numPhysIntRegs=256
|
numPhysIntRegs=256
|
||||||
|
@ -88,6 +98,7 @@ numRobs=1
|
||||||
numThreads=1
|
numThreads=1
|
||||||
phase=0
|
phase=0
|
||||||
predType=tournament
|
predType=tournament
|
||||||
|
profile=0
|
||||||
progress_interval=0
|
progress_interval=0
|
||||||
renameToDecodeDelay=1
|
renameToDecodeDelay=1
|
||||||
renameToFetchDelay=1
|
renameToFetchDelay=1
|
||||||
|
@ -148,7 +159,16 @@ mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
[system.cpu.dtb]
|
[system.cpu.dtb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.dtb.walker
|
||||||
|
|
||||||
|
[system.cpu.dtb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[3]
|
||||||
|
|
||||||
[system.cpu.fuPool]
|
[system.cpu.fuPool]
|
||||||
type=FUPool
|
type=FUPool
|
||||||
|
@ -445,9 +465,21 @@ write_buffers=8
|
||||||
cpu_side=system.cpu.icache_port
|
cpu_side=system.cpu.icache_port
|
||||||
mem_side=system.cpu.toL2Bus.port[0]
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.interrupts]
|
||||||
|
type=ArmInterrupts
|
||||||
|
|
||||||
[system.cpu.itb]
|
[system.cpu.itb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.itb.walker
|
||||||
|
|
||||||
|
[system.cpu.itb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[2]
|
||||||
|
|
||||||
[system.cpu.l2cache]
|
[system.cpu.l2cache]
|
||||||
type=BaseCache
|
type=BaseCache
|
||||||
|
@ -478,7 +510,7 @@ tgts_per_mshr=5
|
||||||
trace_addr=0
|
trace_addr=0
|
||||||
two_queue=false
|
two_queue=false
|
||||||
write_buffers=8
|
write_buffers=8
|
||||||
cpu_side=system.cpu.toL2Bus.port[2]
|
cpu_side=system.cpu.toL2Bus.port[4]
|
||||||
mem_side=system.membus.port[2]
|
mem_side=system.membus.port[2]
|
||||||
|
|
||||||
[system.cpu.toL2Bus]
|
[system.cpu.toL2Bus]
|
||||||
|
@ -489,7 +521,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
[system.cpu.tracer]
|
[system.cpu.tracer]
|
||||||
type=ExeTracer
|
type=ExeTracer
|
||||||
|
@ -497,14 +529,14 @@ type=ExeTracer
|
||||||
[system.cpu.workload]
|
[system.cpu.workload]
|
||||||
type=LiveProcess
|
type=LiveProcess
|
||||||
cmd=parser 2.1.dict -batch
|
cmd=parser 2.1.dict -batch
|
||||||
cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
|
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||||
egid=100
|
egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||||
gid=100
|
gid=100
|
||||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
output=cout
|
output=cout
|
||||||
pid=100
|
pid=100
|
||||||
|
|
|
@ -1,10 +1,12 @@
|
||||||
|
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout
|
||||||
|
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 23 2012 04:16:21
|
gem5 compiled Feb 10 2012 00:18:03
|
||||||
gem5 started Jan 23 2012 08:49:36
|
gem5 started Feb 10 2012 00:18:20
|
||||||
gem5 executing on zizzer
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
|
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
|
||||||
|
@ -67,4 +69,4 @@ info: Increasing stack size by one page.
|
||||||
about 2 million people attended
|
about 2 million people attended
|
||||||
the five best costumes got prizes
|
the five best costumes got prizes
|
||||||
No errors!
|
No errors!
|
||||||
Exiting @ tick 274198757500 because target called exit()
|
Exiting @ tick 274128411000 because target called exit()
|
||||||
|
|
|
@ -1,24 +1,24 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.274199 # Number of seconds simulated
|
sim_seconds 0.274128 # Number of seconds simulated
|
||||||
sim_ticks 274198757500 # Number of ticks simulated
|
sim_ticks 274128411000 # Number of ticks simulated
|
||||||
final_tick 274198757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 274128411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 114096 # Simulator instruction rate (inst/s)
|
host_inst_rate 67477 # Simulator instruction rate (inst/s)
|
||||||
host_tick_rate 54566255 # Simulator tick rate (ticks/s)
|
host_tick_rate 32262353 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 225172 # Number of bytes of host memory used
|
host_mem_usage 260864 # Number of bytes of host memory used
|
||||||
host_seconds 5025.06 # Real time elapsed on the host
|
host_seconds 8496.85 # Real time elapsed on the host
|
||||||
sim_insts 573341162 # Number of instructions simulated
|
sim_insts 573341187 # Number of instructions simulated
|
||||||
system.physmem.bytes_read 15248640 # Number of bytes read from this memory
|
system.physmem.bytes_read 15240192 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read 230400 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read 229568 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written 10960192 # Number of bytes written to this memory
|
system.physmem.bytes_written 10959680 # Number of bytes written to this memory
|
||||||
system.physmem.num_reads 238260 # Number of read requests responded to by this memory
|
system.physmem.num_reads 238128 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes 171253 # Number of write requests responded to by this memory
|
system.physmem.num_writes 171245 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||||
system.physmem.bw_read 55611631 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read 55595084 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read 840266 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read 837447 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write 39971706 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write 39980095 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total 95583336 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total 95575179 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||||
|
@ -62,106 +62,106 @@ system.cpu.itb.hits 0 # DT
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||||
system.cpu.numCycles 548397516 # number of cpu cycles simulated
|
system.cpu.numCycles 548256823 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.BPredUnit.lookups 225101784 # Number of BP lookups
|
system.cpu.BPredUnit.lookups 224897268 # Number of BP lookups
|
||||||
system.cpu.BPredUnit.condPredicted 179007547 # Number of conditional branches predicted
|
system.cpu.BPredUnit.condPredicted 178814817 # Number of conditional branches predicted
|
||||||
system.cpu.BPredUnit.condIncorrect 18307036 # Number of conditional branches incorrect
|
system.cpu.BPredUnit.condIncorrect 18282790 # Number of conditional branches incorrect
|
||||||
system.cpu.BPredUnit.BTBLookups 189868979 # Number of BTB lookups
|
system.cpu.BPredUnit.BTBLookups 189563731 # Number of BTB lookups
|
||||||
system.cpu.BPredUnit.BTBHits 156087931 # Number of BTB hits
|
system.cpu.BPredUnit.BTBHits 156236753 # Number of BTB hits
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.BPredUnit.usedRAS 11743928 # Number of times the RAS was used to get a target.
|
system.cpu.BPredUnit.usedRAS 11742995 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.BPredUnit.RASInCorrect 2589266 # Number of incorrect RAS predictions.
|
system.cpu.BPredUnit.RASInCorrect 2591276 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 154237973 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 154191878 # Number of cycles fetch is stalled on an Icache miss
|
||||||
system.cpu.fetch.Insts 996342059 # Number of instructions fetch has processed
|
system.cpu.fetch.Insts 995397299 # Number of instructions fetch has processed
|
||||||
system.cpu.fetch.Branches 225101784 # Number of branches that fetch encountered
|
system.cpu.fetch.Branches 224897268 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 167831859 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 167979748 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.Cycles 251951083 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.fetch.Cycles 252064252 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
system.cpu.fetch.SquashCycles 70115496 # Number of cycles fetch has spent squashing
|
system.cpu.fetch.SquashCycles 69921430 # Number of cycles fetch has spent squashing
|
||||||
system.cpu.fetch.BlockedCycles 88916227 # Number of cycles fetch has spent blocked
|
system.cpu.fetch.BlockedCycles 88879876 # Number of cycles fetch has spent blocked
|
||||||
system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
system.cpu.fetch.PendingTrapStallCycles 27190 # Number of stall cycles due to pending traps
|
system.cpu.fetch.PendingTrapStallCycles 27589 # Number of stall cycles due to pending traps
|
||||||
system.cpu.fetch.CacheLines 141601056 # Number of cache lines fetched
|
system.cpu.fetch.CacheLines 141619226 # Number of cache lines fetched
|
||||||
system.cpu.fetch.IcacheSquashes 4591339 # Number of outstanding Icache misses that were squashed
|
system.cpu.fetch.IcacheSquashes 4743130 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 544609039 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 544471710 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.120756 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.119468 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 2.818747 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 2.816244 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::0 292670234 53.74% 53.74% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::0 292419737 53.71% 53.71% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::1 22602609 4.15% 57.89% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::1 22605861 4.15% 57.86% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::2 39324759 7.22% 65.11% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::2 39604588 7.27% 65.13% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::3 38673680 7.10% 72.21% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::3 38612877 7.09% 72.22% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::4 44132407 8.10% 80.32% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::4 44079940 8.10% 80.32% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::5 15219761 2.79% 83.11% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::5 15590470 2.86% 83.18% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::6 18468380 3.39% 86.50% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::6 18445012 3.39% 86.57% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::7 13866800 2.55% 89.05% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::7 13511392 2.48% 89.05% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::8 59650409 10.95% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::8 59601833 10.95% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 544609039 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 544471710 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.branchRate 0.410472 # Number of branch fetches per cycle
|
system.cpu.fetch.branchRate 0.410204 # Number of branch fetches per cycle
|
||||||
system.cpu.fetch.rate 1.816825 # Number of inst fetches per cycle
|
system.cpu.fetch.rate 1.815568 # Number of inst fetches per cycle
|
||||||
system.cpu.decode.IdleCycles 173360184 # Number of cycles decode is idle
|
system.cpu.decode.IdleCycles 173466263 # Number of cycles decode is idle
|
||||||
system.cpu.decode.BlockedCycles 84631968 # Number of cycles decode is blocked
|
system.cpu.decode.BlockedCycles 84575198 # Number of cycles decode is blocked
|
||||||
system.cpu.decode.RunCycles 232819510 # Number of cycles decode is running
|
system.cpu.decode.RunCycles 232805016 # Number of cycles decode is running
|
||||||
system.cpu.decode.UnblockCycles 4407510 # Number of cycles decode is unblocking
|
system.cpu.decode.UnblockCycles 4404092 # Number of cycles decode is unblocking
|
||||||
system.cpu.decode.SquashCycles 49389867 # Number of cycles decode is squashing
|
system.cpu.decode.SquashCycles 49221141 # Number of cycles decode is squashing
|
||||||
system.cpu.decode.BranchResolved 33096702 # Number of times decode resolved a branch
|
system.cpu.decode.BranchResolved 33081437 # Number of times decode resolved a branch
|
||||||
system.cpu.decode.BranchMispred 88546 # Number of times decode detected a branch misprediction
|
system.cpu.decode.BranchMispred 88923 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.decode.DecodedInsts 1070717063 # Number of instructions handled by decode
|
system.cpu.decode.DecodedInsts 1069021878 # Number of instructions handled by decode
|
||||||
system.cpu.decode.SquashedInsts 220828 # Number of squashed instructions handled by decode
|
system.cpu.decode.SquashedInsts 219487 # Number of squashed instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 49389867 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 49221141 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 189439670 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 189418333 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 6246457 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 6243189 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 67211324 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 67194010 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 221002512 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 221110320 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 11319209 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 11284717 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 984442373 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 983280870 # Number of instructions processed by rename
|
||||||
system.cpu.rename.ROBFullEvents 1013 # Number of times rename has blocked due to ROB full
|
system.cpu.rename.ROBFullEvents 1088 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.rename.IQFullEvents 2966416 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 2966299 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LSQFullEvents 5236155 # Number of times rename has blocked due to LSQ full
|
system.cpu.rename.LSQFullEvents 5203884 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.rename.FullRegisterEvents 73 # Number of times there has been no free registers
|
system.cpu.rename.FullRegisterEvents 24 # Number of times there has been no free registers
|
||||||
system.cpu.rename.RenamedOperands 1176369692 # Number of destination operands rename has renamed
|
system.cpu.rename.RenamedOperands 1174814245 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenameLookups 4273292331 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenameLookups 4267939396 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.int_rename_lookups 4273289228 # Number of integer rename lookups
|
system.cpu.rename.int_rename_lookups 4267936218 # Number of integer rename lookups
|
||||||
system.cpu.rename.fp_rename_lookups 3103 # Number of floating rename lookups
|
system.cpu.rename.fp_rename_lookups 3178 # Number of floating rename lookups
|
||||||
system.cpu.rename.CommittedMaps 672199296 # Number of HB maps that are committed
|
system.cpu.rename.CommittedMaps 672199336 # Number of HB maps that are committed
|
||||||
system.cpu.rename.UndoneMaps 504170396 # Number of HB maps that are undone due to squashing
|
system.cpu.rename.UndoneMaps 502614909 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.rename.serializingInsts 6164964 # count of serializing insts renamed
|
system.cpu.rename.serializingInsts 6158838 # count of serializing insts renamed
|
||||||
system.cpu.rename.tempSerializingInsts 6164681 # count of temporary serializing insts renamed
|
system.cpu.rename.tempSerializingInsts 6158596 # count of temporary serializing insts renamed
|
||||||
system.cpu.rename.skidInsts 63358237 # count of insts added to the skid buffer
|
system.cpu.rename.skidInsts 63324865 # count of insts added to the skid buffer
|
||||||
system.cpu.memDep0.insertedLoads 196378247 # Number of loads inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedLoads 196341124 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.insertedStores 77986326 # Number of stores inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedStores 77971699 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.conflictingLoads 17967729 # Number of conflicting loads.
|
system.cpu.memDep0.conflictingLoads 17887364 # Number of conflicting loads.
|
||||||
system.cpu.memDep0.conflictingStores 12612066 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 12637820 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 870602735 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 869953710 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 7830625 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 7817073 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 735457773 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 735125256 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 1536942 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 1650830 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 302215535 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 301557809 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 751654986 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 749773525 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 3952431 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.iqSquashedNonSpecRemoved 3938874 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.iq.issued_per_cycle::samples 544609039 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::samples 544471710 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.350433 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 1.350162 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.595771 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.594792 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 241479375 44.34% 44.34% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 241490713 44.35% 44.35% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 95418106 17.52% 61.86% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 95232425 17.49% 61.84% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 86231703 15.83% 77.69% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 86360231 15.86% 77.71% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 59231990 10.88% 88.57% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 58954468 10.83% 88.53% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 36938301 6.78% 95.35% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 37235413 6.84% 95.37% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::5 14710122 2.70% 98.05% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::5 14676941 2.70% 98.07% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::6 6373652 1.17% 99.22% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::6 6419263 1.18% 99.25% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::7 3471755 0.64% 99.86% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::7 3351018 0.62% 99.86% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::8 754035 0.14% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::8 751238 0.14% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::total 544609039 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::total 544471710 # Number of insts issued each cycle
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntAlu 133367 1.38% 1.38% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntAlu 133047 1.38% 1.38% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available
|
||||||
|
@ -190,15 +190,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # at
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemRead 6658147 68.82% 70.20% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemRead 6635057 68.81% 70.19% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemWrite 2883419 29.80% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemWrite 2874860 29.81% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 497367446 67.63% 67.63% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 497160573 67.63% 67.63% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 380524 0.05% 67.68% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 379945 0.05% 67.68% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatAdd 142 0.00% 67.68% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatAdd 138 0.00% 67.68% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued
|
||||||
|
@ -224,137 +224,137 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.68% # Ty
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 170820646 23.23% 90.91% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 170682566 23.22% 90.90% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 66889012 9.09% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 66902031 9.10% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 735457773 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 735125256 # Type of FU issued
|
||||||
system.cpu.iq.rate 1.341103 # Inst issue rate
|
system.cpu.iq.rate 1.340841 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 9674933 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 9642964 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.013155 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.013117 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 2026736140 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 2026015704 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 1180706061 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 1179385447 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 693772826 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 693708754 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 320 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 312 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 454 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 466 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 745132544 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 744768062 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 162 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 158 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 8466293 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 8478103 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 69605317 # Number of loads squashed
|
system.cpu.iew.lsq.thread0.squashedLoads 69568189 # Number of loads squashed
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 50613 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iew.lsq.thread0.ignoredResponses 50872 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 61790 # Number of memory ordering violations
|
system.cpu.iew.lsq.thread0.memOrderViolation 61447 # Number of memory ordering violations
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 20382475 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 20367843 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 28472 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 28247 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 334 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 358 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 49389867 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 49221141 # Number of cycles IEW is squashing
|
||||||
system.cpu.iew.iewBlockCycles 2700739 # Number of cycles IEW is blocking
|
system.cpu.iew.iewBlockCycles 2690580 # Number of cycles IEW is blocking
|
||||||
system.cpu.iew.iewUnblockCycles 121924 # Number of cycles IEW is unblocking
|
system.cpu.iew.iewUnblockCycles 121747 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iew.iewDispatchedInsts 887765924 # Number of instructions dispatched to IQ
|
system.cpu.iew.iewDispatchedInsts 887104350 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iew.iewDispSquashedInsts 12225511 # Number of squashed instructions skipped by dispatch
|
system.cpu.iew.iewDispSquashedInsts 12434546 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iew.iewDispLoadInsts 196378247 # Number of dispatched load instructions
|
system.cpu.iew.iewDispLoadInsts 196341124 # Number of dispatched load instructions
|
||||||
system.cpu.iew.iewDispStoreInsts 77986326 # Number of dispatched store instructions
|
system.cpu.iew.iewDispStoreInsts 77971699 # Number of dispatched store instructions
|
||||||
system.cpu.iew.iewDispNonSpecInsts 6083275 # Number of dispatched non-speculative instructions
|
system.cpu.iew.iewDispNonSpecInsts 6076746 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.iew.iewIQFullEvents 46564 # Number of times the IQ has become full, causing a stall
|
system.cpu.iew.iewIQFullEvents 46013 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.iew.iewLSQFullEvents 7422 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iew.iewLSQFullEvents 7579 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.iew.memOrderViolationEvents 61790 # Number of memory order violations
|
system.cpu.iew.memOrderViolationEvents 61447 # Number of memory order violations
|
||||||
system.cpu.iew.predictedTakenIncorrect 18530018 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 18517236 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 5460534 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 5450893 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 23990552 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 23968129 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 711163338 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 710591708 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 161856987 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 161345852 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 24294435 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 24533548 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 9332564 # number of nop insts executed
|
system.cpu.iew.exec_nop 9333567 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 226770071 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 226275553 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 147519559 # Number of branches executed
|
system.cpu.iew.exec_branches 147479421 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 64913084 # Number of stores executed
|
system.cpu.iew.exec_stores 64929701 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 1.296803 # Inst execution rate
|
system.cpu.iew.exec_rate 1.296093 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 699318417 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 699249012 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 693772842 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 693708770 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 395045304 # num instructions producing a value
|
system.cpu.iew.wb_producers 395011112 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 663504976 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 663436791 # num instructions consuming a value
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.iew.wb_rate 1.265091 # insts written-back per cycle
|
system.cpu.iew.wb_rate 1.265299 # insts written-back per cycle
|
||||||
system.cpu.iew.wb_fanout 0.595392 # average fanout of values written-back
|
system.cpu.iew.wb_fanout 0.595401 # average fanout of values written-back
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.commit.commitCommittedInsts 574685046 # The number of committed instructions
|
system.cpu.commit.commitCommittedInsts 574685071 # The number of committed instructions
|
||||||
system.cpu.commit.commitSquashedInsts 313100037 # The number of squashed insts skipped by commit
|
system.cpu.commit.commitSquashedInsts 312438031 # The number of squashed insts skipped by commit
|
||||||
system.cpu.commit.commitNonSpecStalls 3878194 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu.commit.commitNonSpecStalls 3878199 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.commit.branchMispredicts 20503761 # The number of times a branch was mispredicted
|
system.cpu.commit.branchMispredicts 20478103 # The number of times a branch was mispredicted
|
||||||
system.cpu.commit.committed_per_cycle::samples 495219173 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::samples 495250570 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.160466 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::mean 1.160393 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::stdev 1.863525 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::stdev 1.863970 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::0 259975062 52.50% 52.50% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::0 259977309 52.49% 52.49% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::1 116222276 23.47% 75.97% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::1 116342120 23.49% 75.99% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::2 44533135 8.99% 84.96% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::2 44473265 8.98% 84.97% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::3 21295357 4.30% 89.26% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::3 21252753 4.29% 89.26% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::4 19840150 4.01% 93.26% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::4 19820819 4.00% 93.26% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::5 7283820 1.47% 94.74% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::5 7387112 1.49% 94.75% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::6 7518006 1.52% 96.25% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::6 7391590 1.49% 96.24% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::7 3788243 0.76% 97.02% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::7 3775030 0.76% 97.01% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::8 14763124 2.98% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::8 14830572 2.99% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::total 495219173 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::total 495250570 # Number of insts commited each cycle
|
||||||
system.cpu.commit.count 574685046 # Number of instructions committed
|
system.cpu.commit.count 574685071 # Number of instructions committed
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.commit.refs 184376781 # Number of memory references committed
|
system.cpu.commit.refs 184376791 # Number of memory references committed
|
||||||
system.cpu.commit.loads 126772930 # Number of loads committed
|
system.cpu.commit.loads 126772935 # Number of loads committed
|
||||||
system.cpu.commit.membars 1488542 # Number of memory barriers committed
|
system.cpu.commit.membars 1488542 # Number of memory barriers committed
|
||||||
system.cpu.commit.branches 120192115 # Number of branches committed
|
system.cpu.commit.branches 120192120 # Number of branches committed
|
||||||
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
||||||
system.cpu.commit.int_insts 473701197 # Number of committed integer instructions.
|
system.cpu.commit.int_insts 473701217 # Number of committed integer instructions.
|
||||||
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
|
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
|
||||||
system.cpu.commit.bw_lim_events 14763124 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 14830572 # number cycles where commit BW limit reached
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.rob.rob_reads 1368233994 # The number of ROB reads
|
system.cpu.rob.rob_reads 1367535962 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 1825140894 # The number of ROB writes
|
system.cpu.rob.rob_writes 1823647630 # The number of ROB writes
|
||||||
system.cpu.timesIdled 96084 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 94158 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 3788477 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 3785113 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu.committedInsts 573341162 # Number of Instructions Simulated
|
system.cpu.committedInsts 573341187 # Number of Instructions Simulated
|
||||||
system.cpu.committedInsts_total 573341162 # Number of Instructions Simulated
|
system.cpu.committedInsts_total 573341187 # Number of Instructions Simulated
|
||||||
system.cpu.cpi 0.956494 # CPI: Cycles Per Instruction
|
system.cpu.cpi 0.956249 # CPI: Cycles Per Instruction
|
||||||
system.cpu.cpi_total 0.956494 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 0.956249 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 1.045485 # IPC: Instructions Per Cycle
|
system.cpu.ipc 1.045753 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 1.045485 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 1.045753 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 3291621496 # number of integer regfile reads
|
system.cpu.int_regfile_reads 3289345591 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 815258640 # number of integer regfile writes
|
system.cpu.int_regfile_writes 815117578 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||||
system.cpu.misc_regfile_reads 1231509968 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 1230585750 # number of misc regfile reads
|
||||||
system.cpu.misc_regfile_writes 4463832 # number of misc regfile writes
|
system.cpu.misc_regfile_writes 4463842 # number of misc regfile writes
|
||||||
system.cpu.icache.replacements 12844 # number of replacements
|
system.cpu.icache.replacements 12883 # number of replacements
|
||||||
system.cpu.icache.tagsinuse 1060.855578 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 1062.179544 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 141584558 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 141602716 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.sampled_refs 14688 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 14723 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.avg_refs 9639.471541 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 9617.789581 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.occ_blocks::0 1060.855578 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 1062.179544 # Average occupied blocks per context
|
||||||
system.cpu.icache.occ_percent::0 0.517996 # Average percentage of cache occupancy
|
system.cpu.icache.occ_percent::0 0.518642 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.ReadReq_hits 141584561 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 141602717 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits 141584561 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 141602717 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits 141584561 # number of overall hits
|
system.cpu.icache.overall_hits 141602717 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses 16495 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 16509 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses 16495 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 16509 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses 16495 # number of overall misses
|
system.cpu.icache.overall_misses 16509 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 235861500 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 235489500 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency 235861500 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 235489500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency 235861500 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 235489500 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses 141601056 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 141619226 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses 141601056 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 141619226 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses 141601056 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 141619226 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000116 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000117 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate 0.000116 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000117 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate 0.000116 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000117 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 14298.969385 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 14264.310376 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency 14298.969385 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 14264.310376 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency 14298.969385 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 14264.310376 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -364,145 +364,145 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.writebacks 1 # number of writebacks
|
system.cpu.icache.writebacks 1 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_mshr_hits 1651 # number of ReadReq MSHR hits
|
system.cpu.icache.ReadReq_mshr_hits 1646 # number of ReadReq MSHR hits
|
||||||
system.cpu.icache.demand_mshr_hits 1651 # number of demand (read+write) MSHR hits
|
system.cpu.icache.demand_mshr_hits 1646 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.icache.overall_mshr_hits 1651 # number of overall MSHR hits
|
system.cpu.icache.overall_mshr_hits 1646 # number of overall MSHR hits
|
||||||
system.cpu.icache.ReadReq_mshr_misses 14844 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 14863 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.demand_mshr_misses 14844 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses 14863 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses 14844 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses 14863 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 154845500 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency 154537000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency 154845500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency 154537000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency 154845500 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency 154537000 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10431.521153 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10397.429859 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 10431.521153 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 10397.429859 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 10431.521153 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 10397.429859 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.replacements 1212341 # number of replacements
|
system.cpu.dcache.replacements 1212291 # number of replacements
|
||||||
system.cpu.dcache.tagsinuse 4058.230538 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 4058.220860 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 204314278 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 203801196 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.sampled_refs 1216437 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 1216387 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.avg_refs 167.961249 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 167.546345 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 5623770000 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 5623769000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.occ_blocks::0 4058.230538 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 4058.220860 # Average occupied blocks per context
|
||||||
system.cpu.dcache.occ_percent::0 0.990779 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_percent::0 0.990777 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.ReadReq_hits 146820758 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 146308743 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits 52766592 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 52772298 # number of WriteReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits 2494784 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits 2488014 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits 2231915 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits 2231920 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.demand_hits 199587350 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 199081041 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits 199587350 # number of overall hits
|
system.cpu.dcache.overall_hits 199081041 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses 1243424 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 1241922 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses 1472714 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 1467008 # number of WriteReq misses
|
||||||
system.cpu.dcache.LoadLockedReq_misses 59 # number of LoadLockedReq misses
|
system.cpu.dcache.LoadLockedReq_misses 55 # number of LoadLockedReq misses
|
||||||
system.cpu.dcache.demand_misses 2716138 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 2708930 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses 2716138 # number of overall misses
|
system.cpu.dcache.overall_misses 2708930 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency 14347379500 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 14257023500 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency 25015184497 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 24962643993 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency 557000 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency 523000 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency 39362563997 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 39219667493 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency 39362563997 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 39219667493 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses 148064182 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 147550665 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses 2494843 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses 2488069 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses 2231915 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses 2231920 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses 202303488 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 201789971 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses 202303488 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 201789971 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.008398 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.008417 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.027152 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.027047 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.000024 # miss rate for LoadLockedReq accesses
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.000022 # miss rate for LoadLockedReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate 0.013426 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.013425 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate 0.013426 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.013425 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 11538.605898 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 11479.805898 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 16985.772185 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 17016.024448 # average WriteReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 9440.677966 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 9509.090909 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency 14492.107543 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 14477.918401 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency 14492.107543 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 14477.918401 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 502000 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 484000 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_targets 64 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_targets 61 # number of cycles access was blocked
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets 7843.750000 # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets 7934.426230 # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks 1079461 # number of writebacks
|
system.cpu.dcache.writebacks 1079423 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 367349 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits 365990 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 1132203 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits 1126420 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_hits 59 # number of LoadLockedReq MSHR hits
|
system.cpu.dcache.LoadLockedReq_mshr_hits 55 # number of LoadLockedReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits 1499552 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 1492410 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits 1499552 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 1492410 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 876075 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 875932 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 340511 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 340588 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses 1216586 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 1216520 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses 1216586 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 1216520 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 6316165000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 6305474000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 4359865500 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 4364186500 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 10676030500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 10669660500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 10676030500 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 10669660500 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005917 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005936 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006278 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006279 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.006014 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.006029 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.006014 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.006029 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7209.616757 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7198.588475 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12803.890330 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12813.682514 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 8775.401410 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 8770.641255 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 8775.401410 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 8770.641255 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.replacements 219133 # number of replacements
|
system.cpu.l2cache.replacements 218982 # number of replacements
|
||||||
system.cpu.l2cache.tagsinuse 21061.116186 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 21063.326998 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 1567440 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 1568375 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.sampled_refs 239478 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 239342 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 6.545236 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 6.552862 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 204357736000 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 204310095000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.occ_blocks::0 7517.812526 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 7519.880092 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 13543.303660 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 13543.446906 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.229425 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.229489 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.413309 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.413313 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.ReadReq_hits 760340 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 760536 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits 1079462 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 1079424 # number of Writeback hits
|
||||||
system.cpu.l2cache.UpgradeReq_hits 116 # number of UpgradeReq hits
|
system.cpu.l2cache.UpgradeReq_hits 96 # number of UpgradeReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 232507 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits 232415 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits 992847 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 992951 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits 992847 # number of overall hits
|
system.cpu.l2cache.overall_hits 992951 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses 130056 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 129729 # number of ReadReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_misses 33 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses 35 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses 108226 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 108423 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses 238282 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 238152 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses 238282 # number of overall misses
|
system.cpu.l2cache.overall_misses 238152 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 4448635000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 4437312000 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_miss_latency 68000 # number of UpgradeReq miss cycles
|
system.cpu.l2cache.UpgradeReq_miss_latency 171500 # number of UpgradeReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 3706374500 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 3713377000 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency 8155009500 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 8150689000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency 8155009500 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 8150689000 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses 890396 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 890265 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses 1079462 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 1079424 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_accesses 149 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses 131 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses 340733 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 340838 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses 1231129 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 1231103 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 1231129 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 1231103 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.146065 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.145720 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.221477 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.267176 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.317627 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 0.318107 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate 0.193548 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.193446 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate 0.193548 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.193446 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34205.534539 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34204.472400 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 2060.606061 # average UpgradeReq miss latency
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4900 # average UpgradeReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34246.618188 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34248.978538 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34224.194442 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 34224.734623 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34224.194442 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34224.734623 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -511,32 +511,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.writebacks 171253 # number of writebacks
|
system.cpu.l2cache.writebacks 171245 # number of writebacks
|
||||||
system.cpu.l2cache.ReadReq_mshr_hits 19 # number of ReadReq MSHR hits
|
system.cpu.l2cache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits
|
||||||
system.cpu.l2cache.demand_mshr_hits 19 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_hits 19 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 22 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 130037 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 129707 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses 33 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 108226 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 108423 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses 238263 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 238130 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses 238263 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 238130 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4037689500 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 4027357500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1023000 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1085000 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3355622000 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3362010000 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 7393311500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 7389367500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 7393311500 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 7389367500 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146044 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.145695 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.221477 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.267176 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317627 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.318107 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.193532 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.193428 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.193532 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.193428 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31050.312603 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31049.654221 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.691793 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.273152 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.813001 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.813001 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=false
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=System
|
type=System
|
||||||
children=cpu membus physmem
|
children=cpu membus physmem
|
||||||
|
boot_osflags=a
|
||||||
|
init_param=0
|
||||||
|
kernel=
|
||||||
|
load_addr_mask=1099511627775
|
||||||
mem_mode=atomic
|
mem_mode=atomic
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
|
readfile=
|
||||||
|
symbolfile=
|
||||||
work_begin_ckpt_count=0
|
work_begin_ckpt_count=0
|
||||||
work_begin_cpu_id_exit=-1
|
work_begin_cpu_id_exit=-1
|
||||||
work_begin_exit_count=0
|
work_begin_exit_count=0
|
||||||
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
type=DerivO3CPU
|
type=DerivO3CPU
|
||||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||||
BTBEntries=4096
|
BTBEntries=4096
|
||||||
BTBTagSize=16
|
BTBTagSize=16
|
||||||
LFSTSize=1024
|
LFSTSize=1024
|
||||||
|
@ -52,6 +59,7 @@ decodeWidth=8
|
||||||
defer_registration=false
|
defer_registration=false
|
||||||
dispatchWidth=8
|
dispatchWidth=8
|
||||||
do_checkpoint_insts=true
|
do_checkpoint_insts=true
|
||||||
|
do_quiesce=true
|
||||||
do_statistics_insts=true
|
do_statistics_insts=true
|
||||||
dtb=system.cpu.dtb
|
dtb=system.cpu.dtb
|
||||||
fetchToDecodeDelay=1
|
fetchToDecodeDelay=1
|
||||||
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
||||||
iewToFetchDelay=1
|
iewToFetchDelay=1
|
||||||
iewToRenameDelay=1
|
iewToRenameDelay=1
|
||||||
instShiftAmt=2
|
instShiftAmt=2
|
||||||
|
interrupts=system.cpu.interrupts
|
||||||
issueToExecuteDelay=1
|
issueToExecuteDelay=1
|
||||||
issueWidth=8
|
issueWidth=8
|
||||||
itb=system.cpu.itb
|
itb=system.cpu.itb
|
||||||
|
@ -89,6 +98,7 @@ numRobs=1
|
||||||
numThreads=1
|
numThreads=1
|
||||||
phase=0
|
phase=0
|
||||||
predType=tournament
|
predType=tournament
|
||||||
|
profile=0
|
||||||
progress_interval=0
|
progress_interval=0
|
||||||
renameToDecodeDelay=1
|
renameToDecodeDelay=1
|
||||||
renameToFetchDelay=1
|
renameToFetchDelay=1
|
||||||
|
@ -149,7 +159,14 @@ mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
[system.cpu.dtb]
|
[system.cpu.dtb]
|
||||||
type=X86TLB
|
type=X86TLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.dtb.walker
|
||||||
|
|
||||||
|
[system.cpu.dtb.walker]
|
||||||
|
type=X86PagetableWalker
|
||||||
|
system=system
|
||||||
|
port=system.cpu.toL2Bus.port[3]
|
||||||
|
|
||||||
[system.cpu.fuPool]
|
[system.cpu.fuPool]
|
||||||
type=FUPool
|
type=FUPool
|
||||||
|
@ -446,9 +463,25 @@ write_buffers=8
|
||||||
cpu_side=system.cpu.icache_port
|
cpu_side=system.cpu.icache_port
|
||||||
mem_side=system.cpu.toL2Bus.port[0]
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.interrupts]
|
||||||
|
type=X86LocalApic
|
||||||
|
int_latency=1000
|
||||||
|
pio_addr=2305843009213693952
|
||||||
|
pio_latency=1000
|
||||||
|
system=system
|
||||||
|
int_port=system.membus.port[4]
|
||||||
|
pio=system.membus.port[3]
|
||||||
|
|
||||||
[system.cpu.itb]
|
[system.cpu.itb]
|
||||||
type=X86TLB
|
type=X86TLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.itb.walker
|
||||||
|
|
||||||
|
[system.cpu.itb.walker]
|
||||||
|
type=X86PagetableWalker
|
||||||
|
system=system
|
||||||
|
port=system.cpu.toL2Bus.port[2]
|
||||||
|
|
||||||
[system.cpu.l2cache]
|
[system.cpu.l2cache]
|
||||||
type=BaseCache
|
type=BaseCache
|
||||||
|
@ -479,7 +512,7 @@ tgts_per_mshr=5
|
||||||
trace_addr=0
|
trace_addr=0
|
||||||
two_queue=false
|
two_queue=false
|
||||||
write_buffers=8
|
write_buffers=8
|
||||||
cpu_side=system.cpu.toL2Bus.port[2]
|
cpu_side=system.cpu.toL2Bus.port[4]
|
||||||
mem_side=system.membus.port[2]
|
mem_side=system.membus.port[2]
|
||||||
|
|
||||||
[system.cpu.toL2Bus]
|
[system.cpu.toL2Bus]
|
||||||
|
@ -490,7 +523,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
[system.cpu.tracer]
|
[system.cpu.tracer]
|
||||||
type=ExeTracer
|
type=ExeTracer
|
||||||
|
@ -498,7 +531,7 @@ type=ExeTracer
|
||||||
[system.cpu.workload]
|
[system.cpu.workload]
|
||||||
type=LiveProcess
|
type=LiveProcess
|
||||||
cmd=parser 2.1.dict -batch
|
cmd=parser 2.1.dict -batch
|
||||||
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
|
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||||
egid=100
|
egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
|
@ -522,7 +555,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||||
|
|
||||||
[system.physmem]
|
[system.physmem]
|
||||||
type=PhysicalMemory
|
type=PhysicalMemory
|
||||||
|
|
|
@ -1,12 +1,12 @@
|
||||||
Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simout
|
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
|
||||||
Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simerr
|
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 28 2012 12:11:40
|
gem5 compiled Feb 9 2012 12:45:55
|
||||||
gem5 started Jan 28 2012 12:12:44
|
gem5 started Feb 9 2012 12:46:40
|
||||||
gem5 executing on ribera.cs.wisc.edu
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
|
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
|
||||||
|
@ -71,4 +71,4 @@ info: Increasing stack size by one page.
|
||||||
about 2 million people attended
|
about 2 million people attended
|
||||||
the five best costumes got prizes
|
the five best costumes got prizes
|
||||||
No errors!
|
No errors!
|
||||||
Exiting @ tick 488997764000 because target called exit()
|
Exiting @ tick 488026375000 because target called exit()
|
||||||
|
|
|
@ -1,263 +1,264 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.488998 # Number of seconds simulated
|
sim_seconds 0.488026 # Number of seconds simulated
|
||||||
sim_ticks 488997764000 # Number of ticks simulated
|
sim_ticks 488026375000 # Number of ticks simulated
|
||||||
final_tick 488997764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 488026375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 107684 # Simulator instruction rate (inst/s)
|
host_inst_rate 87795 # Simulator instruction rate (inst/s)
|
||||||
host_tick_rate 34439407 # Simulator tick rate (ticks/s)
|
host_tick_rate 28022613 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 280760 # Number of bytes of host memory used
|
host_mem_usage 289796 # Number of bytes of host memory used
|
||||||
host_seconds 14198.79 # Real time elapsed on the host
|
host_seconds 17415.45 # Real time elapsed on the host
|
||||||
sim_insts 1528988756 # Number of instructions simulated
|
sim_insts 1528988756 # Number of instructions simulated
|
||||||
system.physmem.bytes_read 37533312 # Number of bytes read from this memory
|
system.physmem.bytes_read 37539712 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read 347328 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read 347136 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written 26337408 # Number of bytes written to this memory
|
system.physmem.bytes_written 26338560 # Number of bytes written to this memory
|
||||||
system.physmem.num_reads 586458 # Number of read requests responded to by this memory
|
system.physmem.num_reads 586558 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes 411522 # Number of write requests responded to by this memory
|
system.physmem.num_writes 411540 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||||
system.physmem.bw_read 76755590 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read 76921482 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read 710285 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read 711306 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write 53859976 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write 53969542 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total 130615567 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total 130891024 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||||
system.cpu.numCycles 977995529 # number of cpu cycles simulated
|
system.cpu.numCycles 976052751 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.BPredUnit.lookups 244993586 # Number of BP lookups
|
system.cpu.BPredUnit.lookups 244909233 # Number of BP lookups
|
||||||
system.cpu.BPredUnit.condPredicted 244993586 # Number of conditional branches predicted
|
system.cpu.BPredUnit.condPredicted 244909233 # Number of conditional branches predicted
|
||||||
system.cpu.BPredUnit.condIncorrect 16602389 # Number of conditional branches incorrect
|
system.cpu.BPredUnit.condIncorrect 16551670 # Number of conditional branches incorrect
|
||||||
system.cpu.BPredUnit.BTBLookups 235528185 # Number of BTB lookups
|
system.cpu.BPredUnit.BTBLookups 235577670 # Number of BTB lookups
|
||||||
system.cpu.BPredUnit.BTBHits 217667296 # Number of BTB hits
|
system.cpu.BPredUnit.BTBHits 217623896 # Number of BTB hits
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 204934624 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 203635164 # Number of cycles fetch is stalled on an Icache miss
|
||||||
system.cpu.fetch.Insts 1339258211 # Number of instructions fetch has processed
|
system.cpu.fetch.Insts 1335786629 # Number of instructions fetch has processed
|
||||||
system.cpu.fetch.Branches 244993586 # Number of branches that fetch encountered
|
system.cpu.fetch.Branches 244909233 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 217667296 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 217623896 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.Cycles 435322465 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.fetch.Cycles 434745893 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
system.cpu.fetch.SquashCycles 118846275 # Number of cycles fetch has spent squashing
|
system.cpu.fetch.SquashCycles 118311552 # Number of cycles fetch has spent squashing
|
||||||
system.cpu.fetch.BlockedCycles 217468055 # Number of cycles fetch has spent blocked
|
system.cpu.fetch.BlockedCycles 217882141 # Number of cycles fetch has spent blocked
|
||||||
system.cpu.fetch.MiscStallCycles 30116 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.fetch.MiscStallCycles 29891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
system.cpu.fetch.PendingTrapStallCycles 232804 # Number of stall cycles due to pending traps
|
system.cpu.fetch.PendingTrapStallCycles 232496 # Number of stall cycles due to pending traps
|
||||||
system.cpu.fetch.CacheLines 194158401 # Number of cache lines fetched
|
system.cpu.fetch.CacheLines 193900404 # Number of cache lines fetched
|
||||||
system.cpu.fetch.IcacheSquashes 4161421 # Number of outstanding Icache misses that were squashed
|
system.cpu.fetch.IcacheSquashes 4295951 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 959969834 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 958022628 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.603022 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.604337 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 3.318234 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 3.317097 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::0 528643490 55.07% 55.07% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::0 527271952 55.04% 55.04% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::1 32333608 3.37% 58.44% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::1 32005205 3.34% 58.38% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::2 38757249 4.04% 62.47% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::2 38652146 4.03% 62.41% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::3 32421466 3.38% 65.85% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::3 32799855 3.42% 65.84% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::4 21788164 2.27% 68.12% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::4 21637734 2.26% 68.10% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::5 36314533 3.78% 71.90% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::5 36320351 3.79% 71.89% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::6 48923013 5.10% 77.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::6 49291435 5.15% 77.03% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::7 36860126 3.84% 80.84% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::7 36948107 3.86% 80.89% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::8 183928185 19.16% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::8 183095843 19.11% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 959969834 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 958022628 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.branchRate 0.250506 # Number of branch fetches per cycle
|
system.cpu.fetch.branchRate 0.250918 # Number of branch fetches per cycle
|
||||||
system.cpu.fetch.rate 1.369391 # Number of inst fetches per cycle
|
system.cpu.fetch.rate 1.368560 # Number of inst fetches per cycle
|
||||||
system.cpu.decode.IdleCycles 264672814 # Number of cycles decode is idle
|
system.cpu.decode.IdleCycles 263275556 # Number of cycles decode is idle
|
||||||
system.cpu.decode.BlockedCycles 172740484 # Number of cycles decode is blocked
|
system.cpu.decode.BlockedCycles 173167084 # Number of cycles decode is blocked
|
||||||
system.cpu.decode.RunCycles 371802947 # Number of cycles decode is running
|
system.cpu.decode.RunCycles 371540300 # Number of cycles decode is running
|
||||||
system.cpu.decode.UnblockCycles 48771819 # Number of cycles decode is unblocking
|
system.cpu.decode.UnblockCycles 48542645 # Number of cycles decode is unblocking
|
||||||
system.cpu.decode.SquashCycles 101981770 # Number of cycles decode is squashing
|
system.cpu.decode.SquashCycles 101497043 # Number of cycles decode is squashing
|
||||||
system.cpu.decode.DecodedInsts 2436948242 # Number of instructions handled by decode
|
system.cpu.decode.DecodedInsts 2434504159 # Number of instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 101981770 # Number of cycles rename is squashing
|
system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
|
||||||
system.cpu.rename.IdleCycles 302199214 # Number of cycles rename is idle
|
system.cpu.rename.SquashCycles 101497043 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.BlockCycles 38454889 # Number of cycles rename is blocking
|
system.cpu.rename.IdleCycles 300930740 # Number of cycles rename is idle
|
||||||
system.cpu.rename.serializeStallCycles 15108 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.BlockCycles 38821666 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.RunCycles 381795429 # Number of cycles rename is running
|
system.cpu.rename.serializeStallCycles 14830 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.UnblockCycles 135523424 # Number of cycles rename is unblocking
|
system.cpu.rename.RunCycles 381234584 # Number of cycles rename is running
|
||||||
system.cpu.rename.RenamedInsts 2384665027 # Number of instructions processed by rename
|
system.cpu.rename.UnblockCycles 135523765 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.ROBFullEvents 2593 # Number of times rename has blocked due to ROB full
|
system.cpu.rename.RenamedInsts 2382098494 # Number of instructions processed by rename
|
||||||
system.cpu.rename.IQFullEvents 22692453 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.ROBFullEvents 2610 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.rename.LSQFullEvents 94335239 # Number of times rename has blocked due to LSQ full
|
system.cpu.rename.IQFullEvents 23187923 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.FullRegisterEvents 23 # Number of times there has been no free registers
|
system.cpu.rename.LSQFullEvents 93850518 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.rename.RenamedOperands 2218279276 # Number of destination operands rename has renamed
|
system.cpu.rename.FullRegisterEvents 43 # Number of times there has been no free registers
|
||||||
system.cpu.rename.RenameLookups 5608704737 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenamedOperands 2215803805 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.int_rename_lookups 5608168752 # Number of integer rename lookups
|
system.cpu.rename.RenameLookups 5602953970 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.fp_rename_lookups 535985 # Number of floating rename lookups
|
system.cpu.rename.int_rename_lookups 5602704256 # Number of integer rename lookups
|
||||||
|
system.cpu.rename.fp_rename_lookups 249714 # Number of floating rename lookups
|
||||||
system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
|
system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
|
||||||
system.cpu.rename.UndoneMaps 790980249 # Number of HB maps that are undone due to squashing
|
system.cpu.rename.UndoneMaps 788504778 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.rename.serializingInsts 1421 # count of serializing insts renamed
|
system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed
|
||||||
system.cpu.rename.tempSerializingInsts 1399 # count of temporary serializing insts renamed
|
system.cpu.rename.tempSerializingInsts 1415 # count of temporary serializing insts renamed
|
||||||
system.cpu.rename.skidInsts 314817660 # count of insts added to the skid buffer
|
system.cpu.rename.skidInsts 315035024 # count of insts added to the skid buffer
|
||||||
system.cpu.memDep0.insertedLoads 575520947 # Number of loads inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedLoads 575221657 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.insertedStores 225733737 # Number of stores inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedStores 225407627 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.conflictingLoads 224565693 # Number of conflicting loads.
|
system.cpu.memDep0.conflictingLoads 224840659 # Number of conflicting loads.
|
||||||
system.cpu.memDep0.conflictingStores 66120103 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 66447324 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 2277627469 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 2274732306 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 14301 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 12754 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 1920324328 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 1918512611 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 1300872 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 1302000 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 746152360 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 743201845 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 1169098860 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 1165991477 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 13748 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.iqSquashedNonSpecRemoved 12201 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.iq.issued_per_cycle::samples 959969834 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::samples 958022628 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::mean 2.000401 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 2.002575 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.810923 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.809760 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 279838383 29.15% 29.15% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 277706841 28.99% 28.99% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 159390008 16.60% 45.75% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 160285139 16.73% 45.72% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 161109543 16.78% 62.54% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 161386173 16.85% 62.56% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 151059392 15.74% 78.27% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 150309706 15.69% 78.25% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 108561364 11.31% 89.58% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 108022954 11.28% 89.53% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::5 60361287 6.29% 95.87% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::5 60994203 6.37% 95.90% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::6 29161241 3.04% 98.91% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::6 28856033 3.01% 98.91% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::7 9391207 0.98% 99.89% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::7 9365653 0.98% 99.89% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::8 1097409 0.11% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::8 1095926 0.11% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::total 959969834 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::total 958022628 # Number of insts issued each cycle
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntAlu 2254063 14.63% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntAlu 2261253 14.71% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntMult 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.63% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.71% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemRead 10153281 65.89% 80.52% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemRead 10108961 65.75% 80.46% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemWrite 3001149 19.48% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemWrite 3003496 19.54% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 2493580 0.13% 0.13% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 2434143 0.13% 0.13% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 1273165358 66.30% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 1271908482 66.30% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 463198530 24.12% 90.55% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 462991606 24.13% 90.56% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 181466860 9.45% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 181178380 9.44% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 1920324328 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 1918512611 # Type of FU issued
|
||||||
system.cpu.iq.rate 1.963531 # Inst issue rate
|
system.cpu.iq.rate 1.965583 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 15408493 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 15373710 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.008024 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.008013 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 4817321768 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 4811718392 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 3023912415 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 3018136915 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1872800388 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1871298739 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 6087 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 5168 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 152738 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 82228 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 1933237228 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 1931450456 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 2013 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 1722 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 171308750 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 171083363 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 191418787 # Number of loads squashed
|
system.cpu.iew.lsq.thread0.squashedLoads 191119497 # Number of loads squashed
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 428547 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iew.lsq.thread0.ignoredResponses 436651 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 281164 # Number of memory ordering violations
|
system.cpu.iew.lsq.thread0.memOrderViolation 282394 # Number of memory ordering violations
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 76573878 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 76247769 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 6486 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 6215 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 101981770 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 101497043 # Number of cycles IEW is squashing
|
||||||
system.cpu.iew.iewBlockCycles 7663639 # Number of cycles IEW is blocking
|
system.cpu.iew.iewBlockCycles 7669372 # Number of cycles IEW is blocking
|
||||||
system.cpu.iew.iewUnblockCycles 1191899 # Number of cycles IEW is unblocking
|
system.cpu.iew.iewUnblockCycles 1230820 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iew.iewDispatchedInsts 2277641770 # Number of instructions dispatched to IQ
|
system.cpu.iew.iewDispatchedInsts 2274745060 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iew.iewDispSquashedInsts 1232812 # Number of squashed instructions skipped by dispatch
|
system.cpu.iew.iewDispSquashedInsts 1222472 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iew.iewDispLoadInsts 575520947 # Number of dispatched load instructions
|
system.cpu.iew.iewDispLoadInsts 575221657 # Number of dispatched load instructions
|
||||||
system.cpu.iew.iewDispStoreInsts 225734063 # Number of dispatched store instructions
|
system.cpu.iew.iewDispStoreInsts 225407954 # Number of dispatched store instructions
|
||||||
system.cpu.iew.iewDispNonSpecInsts 6109 # Number of dispatched non-speculative instructions
|
system.cpu.iew.iewDispNonSpecInsts 6105 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.iew.iewIQFullEvents 836752 # Number of times the IQ has become full, causing a stall
|
system.cpu.iew.iewIQFullEvents 878634 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.iew.iewLSQFullEvents 17253 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iew.iewLSQFullEvents 17249 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.iew.memOrderViolationEvents 281164 # Number of memory order violations
|
system.cpu.iew.memOrderViolationEvents 282394 # Number of memory order violations
|
||||||
system.cpu.iew.predictedTakenIncorrect 15662112 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 15676996 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 2402353 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 2334571 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 18064465 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 18011567 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 1886684972 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 1885150488 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 454230068 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 454035777 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 33639356 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 33362123 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 628354292 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 627868559 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 176563619 # Number of branches executed
|
system.cpu.iew.exec_branches 176458351 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 174124224 # Number of stores executed
|
system.cpu.iew.exec_stores 173832782 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 1.929135 # Inst execution rate
|
system.cpu.iew.exec_rate 1.931402 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 1880378728 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 1879040223 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 1872800542 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 1871298858 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 1438142804 # num instructions producing a value
|
system.cpu.iew.wb_producers 1436941600 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 2128029574 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 2126368380 # num instructions consuming a value
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.iew.wb_rate 1.914938 # insts written-back per cycle
|
system.cpu.iew.wb_rate 1.917211 # insts written-back per cycle
|
||||||
system.cpu.iew.wb_fanout 0.675810 # average fanout of values written-back
|
system.cpu.iew.wb_fanout 0.675773 # average fanout of values written-back
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
|
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
|
||||||
system.cpu.commit.commitSquashedInsts 748676946 # The number of squashed insts skipped by commit
|
system.cpu.commit.commitSquashedInsts 745779287 # The number of squashed insts skipped by commit
|
||||||
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.commit.branchMispredicts 16628282 # The number of times a branch was mispredicted
|
system.cpu.commit.branchMispredicts 16577287 # The number of times a branch was mispredicted
|
||||||
system.cpu.commit.committed_per_cycle::samples 857988064 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::samples 856525585 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.782063 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::mean 1.785106 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::stdev 2.285478 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::stdev 2.285139 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::0 333514129 38.87% 38.87% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::0 331592690 38.71% 38.71% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::1 211603589 24.66% 63.53% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::1 211839945 24.73% 63.45% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::2 76333139 8.90% 72.43% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::2 76804588 8.97% 72.41% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::3 92892872 10.83% 83.26% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::3 92775414 10.83% 83.24% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::4 33741100 3.93% 87.19% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::4 33678704 3.93% 87.18% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::5 28402540 3.31% 90.50% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::5 28505123 3.33% 90.50% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::6 15787299 1.84% 92.34% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::6 15688691 1.83% 92.34% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::7 11367789 1.32% 93.67% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::7 11282624 1.32% 93.65% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::8 54345607 6.33% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::8 54357806 6.35% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::total 857988064 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::total 856525585 # Number of insts commited each cycle
|
||||||
system.cpu.commit.count 1528988756 # Number of instructions committed
|
system.cpu.commit.count 1528988756 # Number of instructions committed
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.commit.refs 533262345 # Number of memory references committed
|
system.cpu.commit.refs 533262345 # Number of memory references committed
|
||||||
|
@ -267,48 +268,48 @@ system.cpu.commit.branches 149758588 # Nu
|
||||||
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
||||||
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
|
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
|
||||||
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
||||||
system.cpu.commit.bw_lim_events 54345607 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 54357806 # number cycles where commit BW limit reached
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.rob.rob_reads 3081308159 # The number of ROB reads
|
system.cpu.rob.rob_reads 3076935822 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 4657476889 # The number of ROB writes
|
system.cpu.rob.rob_writes 4651204201 # The number of ROB writes
|
||||||
system.cpu.timesIdled 418960 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 418807 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 18025695 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 18030123 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
|
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
|
||||||
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
|
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
|
||||||
system.cpu.cpi 0.639636 # CPI: Cycles Per Instruction
|
system.cpu.cpi 0.638365 # CPI: Cycles Per Instruction
|
||||||
system.cpu.cpi_total 0.639636 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 0.638365 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 1.563390 # IPC: Instructions Per Cycle
|
system.cpu.ipc 1.566502 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 1.563390 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 1.566502 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 3178059548 # number of integer regfile reads
|
system.cpu.int_regfile_reads 3175693593 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 1743141344 # number of integer regfile writes
|
system.cpu.int_regfile_writes 1742205758 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 155 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 120 # number of floating regfile reads
|
||||||
system.cpu.misc_regfile_reads 1037170422 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 1036377940 # number of misc regfile reads
|
||||||
system.cpu.icache.replacements 10067 # number of replacements
|
system.cpu.icache.replacements 10111 # number of replacements
|
||||||
system.cpu.icache.tagsinuse 971.911936 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 973.820201 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 193916703 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 193659156 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.sampled_refs 11565 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 11601 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.avg_refs 16767.548898 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 16693.315749 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.occ_blocks::0 971.911936 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 973.820201 # Average occupied blocks per context
|
||||||
system.cpu.icache.occ_percent::0 0.474566 # Average percentage of cache occupancy
|
system.cpu.icache.occ_percent::0 0.475498 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.ReadReq_hits 193923334 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 193665655 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits 193923334 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 193665655 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits 193923334 # number of overall hits
|
system.cpu.icache.overall_hits 193665655 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses 235067 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 234749 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses 235067 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 234749 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses 235067 # number of overall misses
|
system.cpu.icache.overall_misses 234749 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 1701123000 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 1699920500 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency 1701123000 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 1699920500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency 1701123000 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 1699920500 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses 194158401 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 193900404 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses 194158401 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 193900404 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses 194158401 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 193900404 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.001211 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.001211 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate 0.001211 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.001211 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate 0.001211 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.001211 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 7236.758031 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 7241.438728 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency 7236.758031 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 7241.438728 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency 7236.758031 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 7241.438728 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -317,60 +318,60 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.writebacks 8 # number of writebacks
|
system.cpu.icache.writebacks 4 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_mshr_hits 2036 # number of ReadReq MSHR hits
|
system.cpu.icache.ReadReq_mshr_hits 2040 # number of ReadReq MSHR hits
|
||||||
system.cpu.icache.demand_mshr_hits 2036 # number of demand (read+write) MSHR hits
|
system.cpu.icache.demand_mshr_hits 2040 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.icache.overall_mshr_hits 2036 # number of overall MSHR hits
|
system.cpu.icache.overall_mshr_hits 2040 # number of overall MSHR hits
|
||||||
system.cpu.icache.ReadReq_mshr_misses 233031 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 232709 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.demand_mshr_misses 233031 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses 232709 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses 233031 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses 232709 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 952412000 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency 952455000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency 952412000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency 952455000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency 952412000 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency 952455000 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.001200 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.001200 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.001200 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate 0.001200 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.001200 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate 0.001200 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4087.061378 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4092.901435 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 4087.061378 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 4092.901435 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 4087.061378 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 4092.901435 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.replacements 2529213 # number of replacements
|
system.cpu.dcache.replacements 2529316 # number of replacements
|
||||||
system.cpu.dcache.tagsinuse 4087.436678 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 4087.520068 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 427576950 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 427611101 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.sampled_refs 2533309 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 2533412 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.avg_refs 168.781996 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 168.788614 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 2167021000 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 2115074000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.occ_blocks::0 4087.436678 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 4087.520068 # Average occupied blocks per context
|
||||||
system.cpu.dcache.occ_percent::0 0.997909 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_percent::0 0.997930 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.ReadReq_hits 278854362 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 278887188 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits 148163093 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 148162157 # number of WriteReq hits
|
||||||
system.cpu.dcache.demand_hits 427017455 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 427049345 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits 427017455 # number of overall hits
|
system.cpu.dcache.overall_hits 427049345 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses 2666620 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 2665882 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses 997108 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 998044 # number of WriteReq misses
|
||||||
system.cpu.dcache.demand_misses 3663728 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 3663926 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses 3663728 # number of overall misses
|
system.cpu.dcache.overall_misses 3663926 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency 39487606500 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 39487902000 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency 20600704500 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 20586128000 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency 60088311000 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 60074030000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency 60088311000 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 60074030000 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses 281520982 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 281553070 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses 430681183 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 430713271 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses 430681183 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 430713271 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.009472 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.009468 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.006685 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.006691 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate 0.008507 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.008507 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate 0.008507 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.008507 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 14808.111579 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 14812.321776 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 20660.454535 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 20626.473382 # average WriteReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency 16400.865730 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 16396.081689 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency 16400.865730 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 16396.081689 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -379,75 +380,75 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks 2229973 # number of writebacks
|
system.cpu.dcache.writebacks 2229932 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 903774 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits 902993 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 5204 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits 908978 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 909446 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits 908978 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 909446 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 1762846 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 1762889 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 991904 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 991591 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses 2754750 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 2754480 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses 2754750 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 2754480 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 14963544500 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 14966916500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 17553990000 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 17535799000 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 32517534500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 32502715500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 32517534500 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 32502715500 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.006262 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.006261 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006650 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006648 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.006396 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.006395 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.006396 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.006395 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8488.287973 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8489.993698 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17697.267074 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17684.508028 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 11804.168981 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 11799.946088 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 11804.168981 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 11799.946088 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.replacements 575697 # number of replacements
|
system.cpu.l2cache.replacements 575774 # number of replacements
|
||||||
system.cpu.l2cache.tagsinuse 21610.714484 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 21621.732877 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 3195541 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 3195554 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.sampled_refs 594856 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 594946 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 5.371957 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 5.371166 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 269628029000 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 268816776000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.occ_blocks::0 7828.943593 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 7838.250700 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 13781.770891 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 13783.482177 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.238920 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.239204 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.420586 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.420638 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.ReadReq_hits 1434292 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 1434280 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits 2229981 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 2229936 # number of Writeback hits
|
||||||
system.cpu.l2cache.UpgradeReq_hits 1300 # number of UpgradeReq hits
|
system.cpu.l2cache.UpgradeReq_hits 1289 # number of UpgradeReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 523974 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits 524029 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits 1958266 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 1958309 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits 1958266 # number of overall hits
|
system.cpu.l2cache.overall_hits 1958309 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses 339366 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 339456 # number of ReadReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_misses 220134 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses 219771 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses 247116 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 247125 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses 586482 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 586581 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses 586482 # number of overall misses
|
system.cpu.l2cache.overall_misses 586581 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 11591670000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 11594725000 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_miss_latency 9750500 # number of UpgradeReq miss cycles
|
system.cpu.l2cache.UpgradeReq_miss_latency 9650000 # number of UpgradeReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 8467686500 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 8467808500 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency 20059356500 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 20062533500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency 20059356500 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 20062533500 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses 1773658 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 1773736 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses 2229981 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 2229936 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_accesses 221434 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses 221060 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses 771090 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 771154 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses 2544748 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 2544890 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 2544748 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 2544890 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.191337 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.191379 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.994129 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.994169 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.320476 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 0.320461 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate 0.230468 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.230494 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate 0.230468 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.230494 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34156.839518 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34156.783206 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 44.293476 # average UpgradeReq miss latency
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 43.909342 # average UpgradeReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34266.039026 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34265.284775 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34202.851068 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 34202.494626 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34202.851068 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34202.494626 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -456,31 +457,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.writebacks 411522 # number of writebacks
|
system.cpu.l2cache.writebacks 411540 # number of writebacks
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 339366 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 339456 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses 220134 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses 219771 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 247116 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 247125 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses 586482 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 586581 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses 586482 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 586581 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 10527298500 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 10530013500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6824577500 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6813351000 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7661565500 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7661828500 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 18188864000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 18191842000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 18188864000 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 18191842000 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191337 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191379 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994129 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994169 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320476 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320461 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.230468 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.230494 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.230468 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.230494 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.486731 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.260358 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31001.923828 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.047586 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31003.923259 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31003.858371 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.507661 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.350245 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.507661 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.350245 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=false
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=System
|
type=System
|
||||||
children=cpu membus physmem
|
children=cpu membus physmem
|
||||||
|
boot_osflags=a
|
||||||
|
init_param=0
|
||||||
|
kernel=
|
||||||
|
load_addr_mask=1099511627775
|
||||||
mem_mode=atomic
|
mem_mode=atomic
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
|
readfile=
|
||||||
|
symbolfile=
|
||||||
work_begin_ckpt_count=0
|
work_begin_ckpt_count=0
|
||||||
work_begin_cpu_id_exit=-1
|
work_begin_cpu_id_exit=-1
|
||||||
work_begin_exit_count=0
|
work_begin_exit_count=0
|
||||||
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
type=DerivO3CPU
|
type=DerivO3CPU
|
||||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||||
BTBEntries=4096
|
BTBEntries=4096
|
||||||
BTBTagSize=16
|
BTBTagSize=16
|
||||||
LFSTSize=1024
|
LFSTSize=1024
|
||||||
|
@ -52,6 +59,7 @@ decodeWidth=8
|
||||||
defer_registration=false
|
defer_registration=false
|
||||||
dispatchWidth=8
|
dispatchWidth=8
|
||||||
do_checkpoint_insts=true
|
do_checkpoint_insts=true
|
||||||
|
do_quiesce=true
|
||||||
do_statistics_insts=true
|
do_statistics_insts=true
|
||||||
dtb=system.cpu.dtb
|
dtb=system.cpu.dtb
|
||||||
fetchToDecodeDelay=1
|
fetchToDecodeDelay=1
|
||||||
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
||||||
iewToFetchDelay=1
|
iewToFetchDelay=1
|
||||||
iewToRenameDelay=1
|
iewToRenameDelay=1
|
||||||
instShiftAmt=2
|
instShiftAmt=2
|
||||||
|
interrupts=system.cpu.interrupts
|
||||||
issueToExecuteDelay=1
|
issueToExecuteDelay=1
|
||||||
issueWidth=8
|
issueWidth=8
|
||||||
itb=system.cpu.itb
|
itb=system.cpu.itb
|
||||||
|
@ -80,6 +89,7 @@ max_insts_all_threads=0
|
||||||
max_insts_any_thread=0
|
max_insts_any_thread=0
|
||||||
max_loads_all_threads=0
|
max_loads_all_threads=0
|
||||||
max_loads_any_thread=0
|
max_loads_any_thread=0
|
||||||
|
needsTSO=false
|
||||||
numIQEntries=64
|
numIQEntries=64
|
||||||
numPhysFloatRegs=256
|
numPhysFloatRegs=256
|
||||||
numPhysIntRegs=256
|
numPhysIntRegs=256
|
||||||
|
@ -88,6 +98,7 @@ numRobs=1
|
||||||
numThreads=1
|
numThreads=1
|
||||||
phase=0
|
phase=0
|
||||||
predType=tournament
|
predType=tournament
|
||||||
|
profile=0
|
||||||
progress_interval=0
|
progress_interval=0
|
||||||
renameToDecodeDelay=1
|
renameToDecodeDelay=1
|
||||||
renameToFetchDelay=1
|
renameToFetchDelay=1
|
||||||
|
@ -148,7 +159,16 @@ mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
[system.cpu.dtb]
|
[system.cpu.dtb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.dtb.walker
|
||||||
|
|
||||||
|
[system.cpu.dtb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[3]
|
||||||
|
|
||||||
[system.cpu.fuPool]
|
[system.cpu.fuPool]
|
||||||
type=FUPool
|
type=FUPool
|
||||||
|
@ -445,9 +465,21 @@ write_buffers=8
|
||||||
cpu_side=system.cpu.icache_port
|
cpu_side=system.cpu.icache_port
|
||||||
mem_side=system.cpu.toL2Bus.port[0]
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.interrupts]
|
||||||
|
type=ArmInterrupts
|
||||||
|
|
||||||
[system.cpu.itb]
|
[system.cpu.itb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.itb.walker
|
||||||
|
|
||||||
|
[system.cpu.itb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[2]
|
||||||
|
|
||||||
[system.cpu.l2cache]
|
[system.cpu.l2cache]
|
||||||
type=BaseCache
|
type=BaseCache
|
||||||
|
@ -478,7 +510,7 @@ tgts_per_mshr=5
|
||||||
trace_addr=0
|
trace_addr=0
|
||||||
two_queue=false
|
two_queue=false
|
||||||
write_buffers=8
|
write_buffers=8
|
||||||
cpu_side=system.cpu.toL2Bus.port[2]
|
cpu_side=system.cpu.toL2Bus.port[4]
|
||||||
mem_side=system.membus.port[2]
|
mem_side=system.membus.port[2]
|
||||||
|
|
||||||
[system.cpu.toL2Bus]
|
[system.cpu.toL2Bus]
|
||||||
|
@ -489,7 +521,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
[system.cpu.tracer]
|
[system.cpu.tracer]
|
||||||
type=ExeTracer
|
type=ExeTracer
|
||||||
|
@ -497,12 +529,12 @@ type=ExeTracer
|
||||||
[system.cpu.workload]
|
[system.cpu.workload]
|
||||||
type=LiveProcess
|
type=LiveProcess
|
||||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||||
cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
|
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
|
||||||
egid=100
|
egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
|
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
|
||||||
gid=100
|
gid=100
|
||||||
input=cin
|
input=cin
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
|
|
|
@ -1,10 +1,12 @@
|
||||||
|
Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout
|
||||||
|
Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 23 2012 04:16:21
|
gem5 compiled Feb 10 2012 00:18:03
|
||||||
gem5 started Jan 23 2012 08:57:55
|
gem5 started Feb 10 2012 00:18:22
|
||||||
gem5 executing on zizzer
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
|
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
@ -13,4 +15,4 @@ info: Increasing stack size by one page.
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
OO-style eon Time= 0.100000
|
OO-style eon Time= 0.100000
|
||||||
Exiting @ tick 104497559500 because target called exit()
|
Exiting @ tick 104492506500 because target called exit()
|
||||||
|
|
|
@ -1,23 +1,23 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.104498 # Number of seconds simulated
|
sim_seconds 0.104493 # Number of seconds simulated
|
||||||
sim_ticks 104497559500 # Number of ticks simulated
|
sim_ticks 104492506500 # Number of ticks simulated
|
||||||
final_tick 104497559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 104492506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 155883 # Simulator instruction rate (inst/s)
|
host_inst_rate 80425 # Simulator instruction rate (inst/s)
|
||||||
host_tick_rate 46665641 # Simulator tick rate (ticks/s)
|
host_tick_rate 24075162 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 228988 # Number of bytes of host memory used
|
host_mem_usage 264476 # Number of bytes of host memory used
|
||||||
host_seconds 2239.28 # Real time elapsed on the host
|
host_seconds 4340.26 # Real time elapsed on the host
|
||||||
sim_insts 349066034 # Number of instructions simulated
|
sim_insts 349066034 # Number of instructions simulated
|
||||||
system.physmem.bytes_read 464512 # Number of bytes read from this memory
|
system.physmem.bytes_read 464000 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read 192704 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read 192512 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
||||||
system.physmem.num_reads 7258 # Number of read requests responded to by this memory
|
system.physmem.num_reads 7250 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes 0 # Number of write requests responded to by this memory
|
system.physmem.num_writes 0 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||||
system.physmem.bw_read 4445195 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read 4440510 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read 1844100 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read 1842352 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total 4445195 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total 4440510 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||||
|
@ -61,105 +61,105 @@ system.cpu.itb.hits 0 # DT
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||||
system.cpu.numCycles 208995120 # number of cpu cycles simulated
|
system.cpu.numCycles 208985014 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.BPredUnit.lookups 38326507 # Number of BP lookups
|
system.cpu.BPredUnit.lookups 38314474 # Number of BP lookups
|
||||||
system.cpu.BPredUnit.condPredicted 21101495 # Number of conditional branches predicted
|
system.cpu.BPredUnit.condPredicted 21092938 # Number of conditional branches predicted
|
||||||
system.cpu.BPredUnit.condIncorrect 3258977 # Number of conditional branches incorrect
|
system.cpu.BPredUnit.condIncorrect 3256966 # Number of conditional branches incorrect
|
||||||
system.cpu.BPredUnit.BTBLookups 27386254 # Number of BTB lookups
|
system.cpu.BPredUnit.BTBLookups 27298627 # Number of BTB lookups
|
||||||
system.cpu.BPredUnit.BTBHits 21276883 # Number of BTB hits
|
system.cpu.BPredUnit.BTBHits 21213565 # Number of BTB hits
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.BPredUnit.usedRAS 7682399 # Number of times the RAS was used to get a target.
|
system.cpu.BPredUnit.usedRAS 7683795 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.BPredUnit.RASInCorrect 61114 # Number of incorrect RAS predictions.
|
system.cpu.BPredUnit.RASInCorrect 61136 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 43645867 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 43642080 # Number of cycles fetch is stalled on an Icache miss
|
||||||
system.cpu.fetch.Insts 338408122 # Number of instructions fetch has processed
|
system.cpu.fetch.Insts 338343690 # Number of instructions fetch has processed
|
||||||
system.cpu.fetch.Branches 38326507 # Number of branches that fetch encountered
|
system.cpu.fetch.Branches 38314474 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 28959282 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 28897360 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.Cycles 79027162 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.fetch.Cycles 78995706 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
system.cpu.fetch.SquashCycles 10989913 # Number of cycles fetch has spent squashing
|
system.cpu.fetch.SquashCycles 10989579 # Number of cycles fetch has spent squashing
|
||||||
system.cpu.fetch.BlockedCycles 78526305 # Number of cycles fetch has spent blocked
|
system.cpu.fetch.BlockedCycles 78549841 # Number of cycles fetch has spent blocked
|
||||||
system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
system.cpu.fetch.PendingTrapStallCycles 81 # Number of stall cycles due to pending traps
|
system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps
|
||||||
system.cpu.fetch.CacheLines 41243030 # Number of cache lines fetched
|
system.cpu.fetch.CacheLines 41237520 # Number of cache lines fetched
|
||||||
system.cpu.fetch.IcacheSquashes 908340 # Number of outstanding Icache misses that were squashed
|
system.cpu.fetch.IcacheSquashes 904571 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 208882385 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 208872334 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.119969 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.119807 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 3.192320 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 3.192773 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::0 130507129 62.48% 62.48% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::0 130527843 62.49% 62.49% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::1 9423807 4.51% 66.99% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::1 9429667 4.51% 67.01% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::2 6028759 2.89% 69.88% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::2 6020154 2.88% 69.89% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::3 6771553 3.24% 73.12% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::3 6750748 3.23% 73.12% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::4 5439017 2.60% 75.72% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::4 5430125 2.60% 75.72% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::5 4859666 2.33% 78.05% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::5 4858478 2.33% 78.05% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::6 3802857 1.82% 79.87% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::6 3783272 1.81% 79.86% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::7 4240079 2.03% 81.90% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::7 4242115 2.03% 81.89% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::8 37809518 18.10% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::8 37829932 18.11% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 208882385 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 208872334 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.branchRate 0.183385 # Number of branch fetches per cycle
|
system.cpu.fetch.branchRate 0.183336 # Number of branch fetches per cycle
|
||||||
system.cpu.fetch.rate 1.619215 # Number of inst fetches per cycle
|
system.cpu.fetch.rate 1.618985 # Number of inst fetches per cycle
|
||||||
system.cpu.decode.IdleCycles 51208963 # Number of cycles decode is idle
|
system.cpu.decode.IdleCycles 51215510 # Number of cycles decode is idle
|
||||||
system.cpu.decode.BlockedCycles 73647751 # Number of cycles decode is blocked
|
system.cpu.decode.BlockedCycles 73658589 # Number of cycles decode is blocked
|
||||||
system.cpu.decode.RunCycles 72596931 # Number of cycles decode is running
|
system.cpu.decode.RunCycles 72565491 # Number of cycles decode is running
|
||||||
system.cpu.decode.UnblockCycles 3816657 # Number of cycles decode is unblocking
|
system.cpu.decode.UnblockCycles 3819053 # Number of cycles decode is unblocking
|
||||||
system.cpu.decode.SquashCycles 7612083 # Number of cycles decode is squashing
|
system.cpu.decode.SquashCycles 7613691 # Number of cycles decode is squashing
|
||||||
system.cpu.decode.BranchResolved 7463930 # Number of times decode resolved a branch
|
system.cpu.decode.BranchResolved 7463255 # Number of times decode resolved a branch
|
||||||
system.cpu.decode.BranchMispred 71162 # Number of times decode detected a branch misprediction
|
system.cpu.decode.BranchMispred 71181 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.decode.DecodedInsts 431701457 # Number of instructions handled by decode
|
system.cpu.decode.DecodedInsts 431647720 # Number of instructions handled by decode
|
||||||
system.cpu.decode.SquashedInsts 197547 # Number of squashed instructions handled by decode
|
system.cpu.decode.SquashedInsts 198442 # Number of squashed instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 7612083 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 7613691 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 58859623 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 58863443 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 1188483 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 1188654 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 57604104 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 57607169 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 68958235 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 68932187 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 14659857 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 14667190 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 416634975 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 416637973 # Number of instructions processed by rename
|
||||||
system.cpu.rename.IQFullEvents 21102 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 21102 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LSQFullEvents 8024802 # Number of times rename has blocked due to LSQ full
|
system.cpu.rename.LSQFullEvents 8032684 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.rename.FullRegisterEvents 88 # Number of times there has been no free registers
|
system.cpu.rename.FullRegisterEvents 88 # Number of times there has been no free registers
|
||||||
system.cpu.rename.RenamedOperands 455431964 # Number of destination operands rename has renamed
|
system.cpu.rename.RenamedOperands 455385433 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenameLookups 2446622850 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenameLookups 2446563589 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.int_rename_lookups 1351809132 # Number of integer rename lookups
|
system.cpu.rename.int_rename_lookups 1351891912 # Number of integer rename lookups
|
||||||
system.cpu.rename.fp_rename_lookups 1094813718 # Number of floating rename lookups
|
system.cpu.rename.fp_rename_lookups 1094671677 # Number of floating rename lookups
|
||||||
system.cpu.rename.CommittedMaps 384568599 # Number of HB maps that are committed
|
system.cpu.rename.CommittedMaps 384568599 # Number of HB maps that are committed
|
||||||
system.cpu.rename.UndoneMaps 70863365 # Number of HB maps that are undone due to squashing
|
system.cpu.rename.UndoneMaps 70816834 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.rename.serializingInsts 3987641 # count of serializing insts renamed
|
system.cpu.rename.serializingInsts 3986585 # count of serializing insts renamed
|
||||||
system.cpu.rename.tempSerializingInsts 4044473 # count of temporary serializing insts renamed
|
system.cpu.rename.tempSerializingInsts 4043449 # count of temporary serializing insts renamed
|
||||||
system.cpu.rename.skidInsts 48252141 # count of insts added to the skid buffer
|
system.cpu.rename.skidInsts 48232782 # count of insts added to the skid buffer
|
||||||
system.cpu.memDep0.insertedLoads 108792162 # Number of loads inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedLoads 108804127 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.insertedStores 93099672 # Number of stores inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedStores 93109820 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.conflictingLoads 3342545 # Number of conflicting loads.
|
system.cpu.memDep0.conflictingLoads 3374999 # Number of conflicting loads.
|
||||||
system.cpu.memDep0.conflictingStores 2273908 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 2307513 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 394239255 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 394258042 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 3865155 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 3864226 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 379120981 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 379117437 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 1801347 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 1806866 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 46369193 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 46393196 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 143590674 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 143558304 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 309514 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.iqSquashedNonSpecRemoved 308585 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.iq.issued_per_cycle::samples 208882385 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::samples 208872334 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.814997 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 1.815068 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.995935 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.996247 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 82049002 39.28% 39.28% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 82047947 39.28% 39.28% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 34801326 16.66% 55.94% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 34785806 16.65% 55.94% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 24478546 11.72% 67.66% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 24508634 11.73% 67.67% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 18529016 8.87% 76.53% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 18508923 8.86% 76.53% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 21712805 10.39% 86.92% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 21724585 10.40% 86.93% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::5 15357191 7.35% 94.28% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::5 15318663 7.33% 94.27% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::6 8402907 4.02% 98.30% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::6 8418302 4.03% 98.30% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::7 2691838 1.29% 99.59% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::7 2689665 1.29% 99.58% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::8 859754 0.41% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::8 869809 0.42% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::total 208882385 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::total 208872334 # Number of insts issued each cycle
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntAlu 2250 0.01% 0.01% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntAlu 2261 0.01% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available
|
||||||
|
@ -179,22 +179,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # at
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 10815 0.06% 0.10% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAdd 10246 0.06% 0.10% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 2509 0.01% 0.12% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCmp 2469 0.01% 0.12% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 378 0.00% 0.12% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCvt 378 0.00% 0.12% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.12% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.12% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 64370 0.37% 0.49% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMisc 64552 0.37% 0.49% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 798 0.00% 0.50% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMult 790 0.00% 0.49% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 177500 1.02% 1.52% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMultAcc 177361 1.02% 1.52% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemRead 9658261 55.66% 57.18% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemRead 9662090 55.64% 57.16% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemWrite 7430721 42.82% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemWrite 7440153 42.84% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 129606192 34.19% 34.19% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 129612173 34.19% 34.19% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 2147281 0.57% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 2147283 0.57% 34.75% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.75% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.75% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.75% # Type of FU issued
|
||||||
|
@ -205,7 +205,7 @@ system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.75% # Ty
|
||||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.75% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.75% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.75% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdCmp 13 0.00% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdCmp 15 0.00% 34.75% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.75% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.75% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.75% # Type of FU issued
|
||||||
|
@ -213,94 +213,94 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.75% # Ty
|
||||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.75% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.75% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.75% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.75% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAdd 6746387 1.78% 36.53% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAdd 6745842 1.78% 36.53% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.53% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.53% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCmp 8673518 2.29% 38.82% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCmp 8678031 2.29% 38.82% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCvt 3499070 0.92% 39.74% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCvt 3497767 0.92% 39.75% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatDiv 1584810 0.42% 40.16% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1584514 0.42% 40.16% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMisc 21149805 5.58% 45.74% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMisc 21146877 5.58% 45.74% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 7187648 1.90% 47.64% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 7187357 1.90% 47.64% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147289 1.89% 49.52% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7146686 1.89% 49.52% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.57% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.57% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 103746274 27.36% 76.93% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 103748568 27.37% 76.93% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 87457408 23.07% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 87447038 23.07% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 379120981 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 379117437 # Type of FU issued
|
||||||
system.cpu.iq.rate 1.814018 # Inst issue rate
|
system.cpu.iq.rate 1.814089 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 17352648 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 17365346 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.045771 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.045805 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 735350759 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 735356252 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 310614656 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 310675933 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 251531674 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 251537712 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 250927583 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 250923168 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 133866908 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 133847541 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 118270115 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 118277096 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 267600383 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 267613476 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 128873246 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 128869307 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 7282081 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 7295740 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 14143162 # Number of loads squashed
|
system.cpu.iew.lsq.thread0.squashedLoads 14155127 # Number of loads squashed
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 112354 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iew.lsq.thread0.ignoredResponses 112471 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 8279 # Number of memory ordering violations
|
system.cpu.iew.lsq.thread0.memOrderViolation 8340 # Number of memory ordering violations
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 10723841 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 10733989 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 272 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 274 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 7612083 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 7613691 # Number of cycles IEW is squashing
|
||||||
system.cpu.iew.iewBlockCycles 19341 # Number of cycles IEW is blocking
|
system.cpu.iew.iewBlockCycles 19337 # Number of cycles IEW is blocking
|
||||||
system.cpu.iew.iewUnblockCycles 437 # Number of cycles IEW is unblocking
|
system.cpu.iew.iewUnblockCycles 437 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iew.iewDispatchedInsts 398151655 # Number of instructions dispatched to IQ
|
system.cpu.iew.iewDispatchedInsts 398169516 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iew.iewDispSquashedInsts 2633597 # Number of squashed instructions skipped by dispatch
|
system.cpu.iew.iewDispSquashedInsts 2638152 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iew.iewDispLoadInsts 108792162 # Number of dispatched load instructions
|
system.cpu.iew.iewDispLoadInsts 108804127 # Number of dispatched load instructions
|
||||||
system.cpu.iew.iewDispStoreInsts 93099672 # Number of dispatched store instructions
|
system.cpu.iew.iewDispStoreInsts 93109820 # Number of dispatched store instructions
|
||||||
system.cpu.iew.iewDispNonSpecInsts 3853935 # Number of dispatched non-speculative instructions
|
system.cpu.iew.iewDispNonSpecInsts 3853005 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall
|
system.cpu.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.iew.iewLSQFullEvents 205 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iew.iewLSQFullEvents 205 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.iew.memOrderViolationEvents 8279 # Number of memory order violations
|
system.cpu.iew.memOrderViolationEvents 8340 # Number of memory order violations
|
||||||
system.cpu.iew.predictedTakenIncorrect 3193235 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 3192687 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 309338 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 308539 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 3502573 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 3501226 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 373031388 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 373035381 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 102121270 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 102118243 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 6089593 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 6082056 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 47245 # number of nop insts executed
|
system.cpu.iew.exec_nop 47248 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 188074720 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 188073317 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 32215232 # Number of branches executed
|
system.cpu.iew.exec_branches 32214551 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 85953450 # Number of stores executed
|
system.cpu.iew.exec_stores 85955074 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 1.784881 # Inst execution rate
|
system.cpu.iew.exec_rate 1.784986 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 370805637 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 370819014 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 369801789 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 369814808 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 175613931 # num instructions producing a value
|
system.cpu.iew.wb_producers 175635069 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 345608979 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 345639533 # num instructions consuming a value
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.iew.wb_rate 1.769428 # insts written-back per cycle
|
system.cpu.iew.wb_rate 1.769576 # insts written-back per cycle
|
||||||
system.cpu.iew.wb_fanout 0.508129 # average fanout of values written-back
|
system.cpu.iew.wb_fanout 0.508145 # average fanout of values written-back
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.commit.commitCommittedInsts 349066646 # The number of committed instructions
|
system.cpu.commit.commitCommittedInsts 349066646 # The number of committed instructions
|
||||||
system.cpu.commit.commitSquashedInsts 49085191 # The number of squashed insts skipped by commit
|
system.cpu.commit.commitSquashedInsts 49103053 # The number of squashed insts skipped by commit
|
||||||
system.cpu.commit.commitNonSpecStalls 3555641 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu.commit.commitNonSpecStalls 3555641 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.commit.branchMispredicts 3229927 # The number of times a branch was mispredicted
|
system.cpu.commit.branchMispredicts 3227876 # The number of times a branch was mispredicted
|
||||||
system.cpu.commit.committed_per_cycle::samples 201270303 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::samples 201258644 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.734318 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::mean 1.734418 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::stdev 2.320939 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::stdev 2.321139 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::0 89873146 44.65% 44.65% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::0 89876372 44.66% 44.66% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::1 39586205 19.67% 64.32% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::1 39560210 19.66% 64.31% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::2 17962686 8.92% 73.25% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::2 17969648 8.93% 73.24% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::3 13145817 6.53% 79.78% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::3 13168483 6.54% 79.79% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::4 14573998 7.24% 87.02% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::4 14551255 7.23% 87.02% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::5 7584463 3.77% 90.79% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::5 7589820 3.77% 90.79% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::6 3507612 1.74% 92.53% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::6 3505620 1.74% 92.53% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::7 3437369 1.71% 94.24% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::7 3424037 1.70% 94.23% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::8 11599007 5.76% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::8 11613199 5.77% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::total 201270303 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::total 201258644 # Number of insts commited each cycle
|
||||||
system.cpu.commit.count 349066646 # Number of instructions committed
|
system.cpu.commit.count 349066646 # Number of instructions committed
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.commit.refs 177024831 # Number of memory references committed
|
system.cpu.commit.refs 177024831 # Number of memory references committed
|
||||||
|
@ -310,50 +310,50 @@ system.cpu.commit.branches 30521879 # Nu
|
||||||
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
|
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
|
||||||
system.cpu.commit.int_insts 279585929 # Number of committed integer instructions.
|
system.cpu.commit.int_insts 279585929 # Number of committed integer instructions.
|
||||||
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
|
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
|
||||||
system.cpu.commit.bw_lim_events 11599007 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 11613199 # number cycles where commit BW limit reached
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.rob.rob_reads 587820610 # The number of ROB reads
|
system.cpu.rob.rob_reads 587812621 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 803918901 # The number of ROB writes
|
system.cpu.rob.rob_writes 803956224 # The number of ROB writes
|
||||||
system.cpu.timesIdled 2585 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 112735 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 112680 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu.committedInsts 349066034 # Number of Instructions Simulated
|
system.cpu.committedInsts 349066034 # Number of Instructions Simulated
|
||||||
system.cpu.committedInsts_total 349066034 # Number of Instructions Simulated
|
system.cpu.committedInsts_total 349066034 # Number of Instructions Simulated
|
||||||
system.cpu.cpi 0.598727 # CPI: Cycles Per Instruction
|
system.cpu.cpi 0.598698 # CPI: Cycles Per Instruction
|
||||||
system.cpu.cpi_total 0.598727 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 0.598698 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 1.670211 # IPC: Instructions Per Cycle
|
system.cpu.ipc 1.670292 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 1.670211 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 1.670292 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 1781871579 # number of integer regfile reads
|
system.cpu.int_regfile_reads 1781918480 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 235815438 # number of integer regfile writes
|
system.cpu.int_regfile_writes 235832393 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 188771754 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 188783884 # number of floating regfile reads
|
||||||
system.cpu.fp_regfile_writes 133861667 # number of floating regfile writes
|
system.cpu.fp_regfile_writes 133870920 # number of floating regfile writes
|
||||||
system.cpu.misc_regfile_reads 1003473737 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 1003409978 # number of misc regfile reads
|
||||||
system.cpu.misc_regfile_writes 34422193 # number of misc regfile writes
|
system.cpu.misc_regfile_writes 34422193 # number of misc regfile writes
|
||||||
system.cpu.icache.replacements 14107 # number of replacements
|
system.cpu.icache.replacements 14108 # number of replacements
|
||||||
system.cpu.icache.tagsinuse 1842.677380 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 1842.733120 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 41226387 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 41220872 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.sampled_refs 15987 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 15988 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.avg_refs 2578.744417 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 2578.238179 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.occ_blocks::0 1842.677380 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 1842.733120 # Average occupied blocks per context
|
||||||
system.cpu.icache.occ_percent::0 0.899745 # Average percentage of cache occupancy
|
system.cpu.icache.occ_percent::0 0.899772 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.ReadReq_hits 41226387 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 41220872 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits 41226387 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 41220872 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits 41226387 # number of overall hits
|
system.cpu.icache.overall_hits 41220872 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses 16643 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 16648 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses 16643 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 16648 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses 16643 # number of overall misses
|
system.cpu.icache.overall_misses 16648 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 201090500 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 201025000 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency 201090500 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 201025000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency 201090500 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 201025000 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses 41243030 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 41237520 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses 41243030 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 41237520 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses 41243030 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 41237520 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000404 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000404 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate 0.000404 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000404 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate 0.000404 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000404 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 12082.587274 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 12075.024027 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency 12082.587274 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 12075.024027 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency 12082.587274 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 12075.024027 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -366,64 +366,64 @@ system.cpu.icache.writebacks 0 # nu
|
||||||
system.cpu.icache.ReadReq_mshr_hits 637 # number of ReadReq MSHR hits
|
system.cpu.icache.ReadReq_mshr_hits 637 # number of ReadReq MSHR hits
|
||||||
system.cpu.icache.demand_mshr_hits 637 # number of demand (read+write) MSHR hits
|
system.cpu.icache.demand_mshr_hits 637 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.icache.overall_mshr_hits 637 # number of overall MSHR hits
|
system.cpu.icache.overall_mshr_hits 637 # number of overall MSHR hits
|
||||||
system.cpu.icache.ReadReq_mshr_misses 16006 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 16011 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.demand_mshr_misses 16006 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses 16011 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses 16006 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses 16011 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 136032000 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency 135953500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency 136032000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency 135953500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency 136032000 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency 135953500 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000388 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000388 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000388 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate 0.000388 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000388 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate 0.000388 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8498.812945 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8491.256011 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 8498.812945 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 8491.256011 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 8498.812945 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 8491.256011 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.replacements 1408 # number of replacements
|
system.cpu.dcache.replacements 1410 # number of replacements
|
||||||
system.cpu.dcache.tagsinuse 3101.194672 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 3098.497902 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 176614084 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 176602100 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.sampled_refs 4596 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 4594 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.avg_refs 38427.781549 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 38441.902481 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.occ_blocks::0 3101.194672 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 3098.497902 # Average occupied blocks per context
|
||||||
system.cpu.dcache.occ_percent::0 0.757128 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_percent::0 0.756469 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.ReadReq_hits 94558380 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 94546395 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits 82033210 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 82033205 # number of WriteReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits 11361 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits 11358 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits 11114 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits 11114 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.demand_hits 176591590 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 176579600 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits 176591590 # number of overall hits
|
system.cpu.dcache.overall_hits 176579600 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses 3380 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 3383 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses 19484 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 19489 # number of WriteReq misses
|
||||||
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
|
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
|
||||||
system.cpu.dcache.demand_misses 22864 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 22872 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses 22864 # number of overall misses
|
system.cpu.dcache.overall_misses 22872 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency 111762500 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 111712500 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency 649531500 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 649715000 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency 761294000 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 761427500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency 761294000 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 761427500 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses 94561760 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 94549778 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses 11363 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses 11360 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses 11114 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses 11114 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses 176614454 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 176602472 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses 176614454 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 176602472 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.000237 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.000238 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate 0.000129 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.000130 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate 0.000129 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.000130 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 33065.828402 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 33021.726278 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 33336.660850 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 33337.523731 # average WriteReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency 33296.623513 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 33290.814096 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency 33296.623513 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 33290.814096 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 307500 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 307500 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -432,73 +432,73 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets 27954.545455 # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets 27954.545455 # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks 1030 # number of writebacks
|
system.cpu.dcache.writebacks 1034 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 1630 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits 1633 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 16619 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits 16622 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
|
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits 18249 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 18255 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits 18249 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 18255 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 1750 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 1750 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 2865 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 2867 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses 4615 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 4617 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses 4615 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 4617 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 53437000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 53344000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 101725000 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 101787500 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 155162000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 155131500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 155162000 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 155131500 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30535.428571 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30482.285714 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35506.108202 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35503.139170 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 33621.235103 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 33600.064977 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 33621.235103 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 33600.064977 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.replacements 57 # number of replacements
|
system.cpu.l2cache.replacements 57 # number of replacements
|
||||||
system.cpu.l2cache.tagsinuse 3897.011564 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 3892.486015 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 13334 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 13341 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.sampled_refs 5354 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 5352 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 2.490474 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 2.492713 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.occ_blocks::0 3518.810301 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 3513.908293 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 378.201262 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 378.577721 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.107386 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.107236 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.011542 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.011553 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.ReadReq_hits 13251 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 13258 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits 1030 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 1034 # number of Writeback hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 19 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits 19 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits 13270 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 13277 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits 13270 # number of overall hits
|
system.cpu.l2cache.overall_hits 13277 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses 4485 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 4479 # number of ReadReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses 23 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses 2828 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 2826 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses 7313 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 7305 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses 7313 # number of overall misses
|
system.cpu.l2cache.overall_misses 7305 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 153892500 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 153679500 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 97502000 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 97429500 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency 251394500 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 251109000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency 251394500 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 251109000 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses 17736 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 17737 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses 1030 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 1034 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses 23 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses 2847 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 2845 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses 20583 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 20582 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 20583 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 20582 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.252876 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.252523 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.993326 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 0.993322 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate 0.355293 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.354922 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate 0.355293 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.354922 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34312.709030 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34311.118553 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34477.369165 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34476.114650 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34376.384521 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 34374.948665 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34376.384521 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34374.948665 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -511,28 +511,28 @@ system.cpu.l2cache.writebacks 0 # nu
|
||||||
system.cpu.l2cache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits
|
system.cpu.l2cache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits
|
||||||
system.cpu.l2cache.demand_mshr_hits 55 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 55 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_hits 55 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 55 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 4430 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 4424 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses 23 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 2828 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 2826 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses 7258 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 7250 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses 7258 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 7250 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 138008000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 137822500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 589000 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 713000 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 88479500 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 88418000 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 226487500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 226240500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 226487500 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 226240500 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.249774 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.249422 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993326 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993322 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.352621 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.352250 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.352621 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.352250 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31153.047404 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31153.367993 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31286.951909 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31287.331918 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.221824 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.586207 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.221824 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.586207 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=false
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=System
|
type=System
|
||||||
children=cpu membus physmem
|
children=cpu membus physmem
|
||||||
|
boot_osflags=a
|
||||||
|
init_param=0
|
||||||
|
kernel=
|
||||||
|
load_addr_mask=1099511627775
|
||||||
mem_mode=atomic
|
mem_mode=atomic
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
|
readfile=
|
||||||
|
symbolfile=
|
||||||
work_begin_ckpt_count=0
|
work_begin_ckpt_count=0
|
||||||
work_begin_cpu_id_exit=-1
|
work_begin_cpu_id_exit=-1
|
||||||
work_begin_exit_count=0
|
work_begin_exit_count=0
|
||||||
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
type=DerivO3CPU
|
type=DerivO3CPU
|
||||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||||
BTBEntries=4096
|
BTBEntries=4096
|
||||||
BTBTagSize=16
|
BTBTagSize=16
|
||||||
LFSTSize=1024
|
LFSTSize=1024
|
||||||
|
@ -52,6 +59,7 @@ decodeWidth=8
|
||||||
defer_registration=false
|
defer_registration=false
|
||||||
dispatchWidth=8
|
dispatchWidth=8
|
||||||
do_checkpoint_insts=true
|
do_checkpoint_insts=true
|
||||||
|
do_quiesce=true
|
||||||
do_statistics_insts=true
|
do_statistics_insts=true
|
||||||
dtb=system.cpu.dtb
|
dtb=system.cpu.dtb
|
||||||
fetchToDecodeDelay=1
|
fetchToDecodeDelay=1
|
||||||
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
||||||
iewToFetchDelay=1
|
iewToFetchDelay=1
|
||||||
iewToRenameDelay=1
|
iewToRenameDelay=1
|
||||||
instShiftAmt=2
|
instShiftAmt=2
|
||||||
|
interrupts=system.cpu.interrupts
|
||||||
issueToExecuteDelay=1
|
issueToExecuteDelay=1
|
||||||
issueWidth=8
|
issueWidth=8
|
||||||
itb=system.cpu.itb
|
itb=system.cpu.itb
|
||||||
|
@ -80,6 +89,7 @@ max_insts_all_threads=0
|
||||||
max_insts_any_thread=0
|
max_insts_any_thread=0
|
||||||
max_loads_all_threads=0
|
max_loads_all_threads=0
|
||||||
max_loads_any_thread=0
|
max_loads_any_thread=0
|
||||||
|
needsTSO=false
|
||||||
numIQEntries=64
|
numIQEntries=64
|
||||||
numPhysFloatRegs=256
|
numPhysFloatRegs=256
|
||||||
numPhysIntRegs=256
|
numPhysIntRegs=256
|
||||||
|
@ -88,6 +98,7 @@ numRobs=1
|
||||||
numThreads=1
|
numThreads=1
|
||||||
phase=0
|
phase=0
|
||||||
predType=tournament
|
predType=tournament
|
||||||
|
profile=0
|
||||||
progress_interval=0
|
progress_interval=0
|
||||||
renameToDecodeDelay=1
|
renameToDecodeDelay=1
|
||||||
renameToFetchDelay=1
|
renameToFetchDelay=1
|
||||||
|
@ -148,7 +159,16 @@ mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
[system.cpu.dtb]
|
[system.cpu.dtb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.dtb.walker
|
||||||
|
|
||||||
|
[system.cpu.dtb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[3]
|
||||||
|
|
||||||
[system.cpu.fuPool]
|
[system.cpu.fuPool]
|
||||||
type=FUPool
|
type=FUPool
|
||||||
|
@ -445,9 +465,21 @@ write_buffers=8
|
||||||
cpu_side=system.cpu.icache_port
|
cpu_side=system.cpu.icache_port
|
||||||
mem_side=system.cpu.toL2Bus.port[0]
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.interrupts]
|
||||||
|
type=ArmInterrupts
|
||||||
|
|
||||||
[system.cpu.itb]
|
[system.cpu.itb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.itb.walker
|
||||||
|
|
||||||
|
[system.cpu.itb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[2]
|
||||||
|
|
||||||
[system.cpu.l2cache]
|
[system.cpu.l2cache]
|
||||||
type=BaseCache
|
type=BaseCache
|
||||||
|
@ -478,7 +510,7 @@ tgts_per_mshr=5
|
||||||
trace_addr=0
|
trace_addr=0
|
||||||
two_queue=false
|
two_queue=false
|
||||||
write_buffers=8
|
write_buffers=8
|
||||||
cpu_side=system.cpu.toL2Bus.port[2]
|
cpu_side=system.cpu.toL2Bus.port[4]
|
||||||
mem_side=system.membus.port[2]
|
mem_side=system.membus.port[2]
|
||||||
|
|
||||||
[system.cpu.toL2Bus]
|
[system.cpu.toL2Bus]
|
||||||
|
@ -489,7 +521,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
[system.cpu.tracer]
|
[system.cpu.tracer]
|
||||||
type=ExeTracer
|
type=ExeTracer
|
||||||
|
@ -497,12 +529,12 @@ type=ExeTracer
|
||||||
[system.cpu.workload]
|
[system.cpu.workload]
|
||||||
type=LiveProcess
|
type=LiveProcess
|
||||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||||
cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
|
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
|
||||||
egid=100
|
egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
|
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
|
||||||
gid=100
|
gid=100
|
||||||
input=cin
|
input=cin
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
|
|
|
@ -1,10 +1,12 @@
|
||||||
|
Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout
|
||||||
|
Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 23 2012 04:16:21
|
gem5 compiled Feb 10 2012 00:18:03
|
||||||
gem5 started Jan 23 2012 09:08:55
|
gem5 started Feb 10 2012 00:18:22
|
||||||
gem5 executing on zizzer
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
|
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
@ -1385,4 +1387,4 @@ info: Increasing stack size by one page.
|
||||||
2000: 760651391
|
2000: 760651391
|
||||||
1000: 4031656975
|
1000: 4031656975
|
||||||
0: 2206428413
|
0: 2206428413
|
||||||
Exiting @ tick 708403313500 because target called exit()
|
Exiting @ tick 708285420500 because target called exit()
|
||||||
|
|
|
@ -1,24 +1,24 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.708403 # Number of seconds simulated
|
sim_seconds 0.708285 # Number of seconds simulated
|
||||||
sim_ticks 708403313500 # Number of ticks simulated
|
sim_ticks 708285420500 # Number of ticks simulated
|
||||||
final_tick 708403313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 708285420500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 118434 # Simulator instruction rate (inst/s)
|
host_inst_rate 74841 # Simulator instruction rate (inst/s)
|
||||||
host_tick_rate 44501063 # Simulator tick rate (ticks/s)
|
host_tick_rate 28116271 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 226576 # Number of bytes of host memory used
|
host_mem_usage 262240 # Number of bytes of host memory used
|
||||||
host_seconds 15918.80 # Real time elapsed on the host
|
host_seconds 25191.30 # Real time elapsed on the host
|
||||||
sim_insts 1885333786 # Number of instructions simulated
|
sim_insts 1885333786 # Number of instructions simulated
|
||||||
system.physmem.bytes_read 94812032 # Number of bytes read from this memory
|
system.physmem.bytes_read 94806144 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read 200960 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read 201024 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written 4230336 # Number of bytes written to this memory
|
system.physmem.bytes_written 4230336 # Number of bytes written to this memory
|
||||||
system.physmem.num_reads 1481438 # Number of read requests responded to by this memory
|
system.physmem.num_reads 1481346 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes 66099 # Number of write requests responded to by this memory
|
system.physmem.num_writes 66099 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||||
system.physmem.bw_read 133839058 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read 133853022 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read 283680 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read 283818 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write 5971649 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write 5972643 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total 139810707 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total 139825665 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||||
|
@ -62,107 +62,106 @@ system.cpu.itb.hits 0 # DT
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 1411 # Number of system calls
|
system.cpu.workload.num_syscalls 1411 # Number of system calls
|
||||||
system.cpu.numCycles 1416806628 # number of cpu cycles simulated
|
system.cpu.numCycles 1416570842 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.BPredUnit.lookups 503033036 # Number of BP lookups
|
system.cpu.BPredUnit.lookups 502965792 # Number of BP lookups
|
||||||
system.cpu.BPredUnit.condPredicted 388160087 # Number of conditional branches predicted
|
system.cpu.BPredUnit.condPredicted 388083906 # Number of conditional branches predicted
|
||||||
system.cpu.BPredUnit.condIncorrect 32894916 # Number of conditional branches incorrect
|
system.cpu.BPredUnit.condIncorrect 32892883 # Number of conditional branches incorrect
|
||||||
system.cpu.BPredUnit.BTBLookups 402481986 # Number of BTB lookups
|
system.cpu.BPredUnit.BTBLookups 402994214 # Number of BTB lookups
|
||||||
system.cpu.BPredUnit.BTBHits 281923865 # Number of BTB hits
|
system.cpu.BPredUnit.BTBHits 282903329 # Number of BTB hits
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.BPredUnit.usedRAS 59796610 # Number of times the RAS was used to get a target.
|
system.cpu.BPredUnit.usedRAS 59754999 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.BPredUnit.RASInCorrect 2840141 # Number of incorrect RAS predictions.
|
system.cpu.BPredUnit.RASInCorrect 2839304 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 410550003 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 410473974 # Number of cycles fetch is stalled on an Icache miss
|
||||||
system.cpu.fetch.Insts 2542460473 # Number of instructions fetch has processed
|
system.cpu.fetch.Insts 2542481038 # Number of instructions fetch has processed
|
||||||
system.cpu.fetch.Branches 503033036 # Number of branches that fetch encountered
|
system.cpu.fetch.Branches 502965792 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 341720475 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 342658328 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.Cycles 682921340 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.fetch.Cycles 682850611 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
system.cpu.fetch.SquashCycles 205013758 # Number of cycles fetch has spent squashing
|
system.cpu.fetch.SquashCycles 204993234 # Number of cycles fetch has spent squashing
|
||||||
system.cpu.fetch.BlockedCycles 105428035 # Number of cycles fetch has spent blocked
|
system.cpu.fetch.BlockedCycles 105359667 # Number of cycles fetch has spent blocked
|
||||||
system.cpu.fetch.MiscStallCycles 2115 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.fetch.MiscStallCycles 2118 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
system.cpu.fetch.PendingTrapStallCycles 34704 # Number of stall cycles due to pending traps
|
system.cpu.fetch.PendingTrapStallCycles 34717 # Number of stall cycles due to pending traps
|
||||||
system.cpu.fetch.CacheLines 384233965 # Number of cache lines fetched
|
system.cpu.fetch.CacheLines 384198016 # Number of cache lines fetched
|
||||||
system.cpu.fetch.IcacheSquashes 12151873 # Number of outstanding Icache misses that were squashed
|
system.cpu.fetch.IcacheSquashes 12176398 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 1365478165 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 1365244569 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.588855 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.589439 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 3.160415 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 3.160393 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::0 682595631 49.99% 49.99% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::0 682433791 49.99% 49.99% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::1 48342952 3.54% 53.53% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::1 48186597 3.53% 53.52% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::2 108702790 7.96% 61.49% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::2 108652804 7.96% 61.47% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::3 62379051 4.57% 66.06% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::3 62364195 4.57% 66.04% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::4 89292584 6.54% 72.60% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::4 89334703 6.54% 72.59% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::5 54148565 3.97% 76.56% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::5 54302238 3.98% 76.56% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::6 35470304 2.60% 79.16% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::6 35506449 2.60% 79.16% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::7 34965610 2.56% 81.72% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::7 34966658 2.56% 81.73% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::8 249580678 18.28% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::8 249497134 18.27% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 1365478165 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 1365244569 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.branchRate 0.355047 # Number of branch fetches per cycle
|
system.cpu.fetch.branchRate 0.355059 # Number of branch fetches per cycle
|
||||||
system.cpu.fetch.rate 1.794501 # Number of inst fetches per cycle
|
system.cpu.fetch.rate 1.794814 # Number of inst fetches per cycle
|
||||||
system.cpu.decode.IdleCycles 455361727 # Number of cycles decode is idle
|
system.cpu.decode.IdleCycles 455297388 # Number of cycles decode is idle
|
||||||
system.cpu.decode.BlockedCycles 85217138 # Number of cycles decode is blocked
|
system.cpu.decode.BlockedCycles 85147033 # Number of cycles decode is blocked
|
||||||
system.cpu.decode.RunCycles 647145530 # Number of cycles decode is running
|
system.cpu.decode.RunCycles 647142661 # Number of cycles decode is running
|
||||||
system.cpu.decode.UnblockCycles 11223736 # Number of cycles decode is unblocking
|
system.cpu.decode.UnblockCycles 11145809 # Number of cycles decode is unblocking
|
||||||
system.cpu.decode.SquashCycles 166530034 # Number of cycles decode is squashing
|
system.cpu.decode.SquashCycles 166511678 # Number of cycles decode is squashing
|
||||||
system.cpu.decode.BranchResolved 68649997 # Number of times decode resolved a branch
|
system.cpu.decode.BranchResolved 68705297 # Number of times decode resolved a branch
|
||||||
system.cpu.decode.BranchMispred 12124 # Number of times decode detected a branch misprediction
|
system.cpu.decode.BranchMispred 11995 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.decode.DecodedInsts 3424361675 # Number of instructions handled by decode
|
system.cpu.decode.DecodedInsts 3424572913 # Number of instructions handled by decode
|
||||||
system.cpu.decode.SquashedInsts 24057 # Number of squashed instructions handled by decode
|
system.cpu.decode.SquashedInsts 23770 # Number of squashed instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 166530034 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 166511678 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 496888956 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 496865002 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 29110139 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 29032521 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 3718079 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 3717307 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 615295356 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 615240410 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 53935601 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 53877651 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 3298153337 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 3297959575 # Number of instructions processed by rename
|
||||||
system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full
|
system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.rename.IQFullEvents 4569845 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 4556255 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LSQFullEvents 42334817 # Number of times rename has blocked due to LSQ full
|
system.cpu.rename.LSQFullEvents 42355939 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers
|
system.cpu.rename.RenamedOperands 3260022737 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenamedOperands 3261061532 # Number of destination operands rename has renamed
|
system.cpu.rename.RenameLookups 15624313135 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.RenameLookups 15624755618 # Number of register rename lookups that rename has made
|
system.cpu.rename.int_rename_lookups 14988978570 # Number of integer rename lookups
|
||||||
system.cpu.rename.int_rename_lookups 14989571898 # Number of integer rename lookups
|
system.cpu.rename.fp_rename_lookups 635334565 # Number of floating rename lookups
|
||||||
system.cpu.rename.fp_rename_lookups 635183720 # Number of floating rename lookups
|
|
||||||
system.cpu.rename.CommittedMaps 1993153599 # Number of HB maps that are committed
|
system.cpu.rename.CommittedMaps 1993153599 # Number of HB maps that are committed
|
||||||
system.cpu.rename.UndoneMaps 1267907933 # Number of HB maps that are undone due to squashing
|
system.cpu.rename.UndoneMaps 1266869138 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.rename.serializingInsts 310582 # count of serializing insts renamed
|
system.cpu.rename.serializingInsts 309495 # count of serializing insts renamed
|
||||||
system.cpu.rename.tempSerializingInsts 306325 # count of temporary serializing insts renamed
|
system.cpu.rename.tempSerializingInsts 305230 # count of temporary serializing insts renamed
|
||||||
system.cpu.rename.skidInsts 155884977 # count of insts added to the skid buffer
|
system.cpu.rename.skidInsts 155871874 # count of insts added to the skid buffer
|
||||||
system.cpu.memDep0.insertedLoads 1045137132 # Number of loads inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedLoads 1045378245 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.insertedStores 527476218 # Number of stores inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedStores 527599628 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.conflictingLoads 35886570 # Number of conflicting loads.
|
system.cpu.memDep0.conflictingLoads 35911477 # Number of conflicting loads.
|
||||||
system.cpu.memDep0.conflictingStores 45267364 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 45240488 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 3077754179 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 3077735106 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 303954 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 301755 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 2619291842 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 2619169948 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 18689867 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 18682763 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 1192085861 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 1192120154 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 2899457281 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 2900187573 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 92624 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.iqSquashedNonSpecRemoved 90425 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.iq.issued_per_cycle::samples 1365478165 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::samples 1365244569 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.918223 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 1.918462 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.900205 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.900067 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 480779837 35.21% 35.21% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 480555764 35.20% 35.20% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 182587607 13.37% 48.58% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 182601458 13.37% 48.57% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 216609244 15.86% 64.44% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 216587645 15.86% 64.44% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 179766275 13.17% 77.61% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 179670065 13.16% 77.60% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 150868799 11.05% 88.66% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 151134600 11.07% 88.67% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::5 89721779 6.57% 95.23% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::5 89532476 6.56% 95.23% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::6 48758870 3.57% 98.80% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::6 48791102 3.57% 98.80% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::7 11536421 0.84% 99.64% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::7 11536059 0.84% 99.65% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::8 4849333 0.36% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::8 4835400 0.35% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::total 1365478165 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::total 1365244569 # Number of insts issued each cycle
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntAlu 2044403 2.26% 2.26% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntAlu 2042243 2.25% 2.25% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntMult 23929 0.03% 2.28% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntMult 23945 0.03% 2.28% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available
|
||||||
|
@ -190,119 +189,119 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # at
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemRead 55649007 61.42% 63.70% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemRead 55656078 61.41% 63.69% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemWrite 32885475 36.30% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemWrite 32910645 36.31% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 1200920026 45.85% 45.85% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 1200490200 45.83% 45.83% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 11234109 0.43% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 11234425 0.43% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.28% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.33% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.32% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.33% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.32% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.26% 46.59% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCmp 6876478 0.26% 46.58% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCvt 5505406 0.21% 46.80% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCvt 5505051 0.21% 46.79% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.80% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.79% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMisc 24362118 0.93% 47.73% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMisc 24362738 0.93% 47.72% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.73% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.72% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.73% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.72% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.73% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.72% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 895924024 34.20% 81.94% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 896045352 34.21% 81.93% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 473094394 18.06% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 473280415 18.07% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 2619291842 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 2619169948 # Type of FU issued
|
||||||
system.cpu.iq.rate 1.848729 # Inst issue rate
|
system.cpu.iq.rate 1.848951 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 90602814 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 90632911 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.034591 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.034604 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 6584849993 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 6584397091 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 4170838685 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 4170852442 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 2409550549 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2409395411 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 128504537 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 128503048 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 99358414 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 99357739 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 57073276 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 57077748 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 2644267181 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 2644176123 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 65627475 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 65626736 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 71974387 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 71999032 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 413748263 # Number of loads squashed
|
system.cpu.iew.lsq.thread0.squashedLoads 413989376 # Number of loads squashed
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 264274 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iew.lsq.thread0.ignoredResponses 268082 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 1389738 # Number of memory ordering violations
|
system.cpu.iew.lsq.thread0.memOrderViolation 1389984 # Number of memory ordering violations
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 250479234 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 250602644 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 88 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 86 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 166530034 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 166511678 # Number of cycles IEW is squashing
|
||||||
system.cpu.iew.iewBlockCycles 16377218 # Number of cycles IEW is blocking
|
system.cpu.iew.iewBlockCycles 16376007 # Number of cycles IEW is blocking
|
||||||
system.cpu.iew.iewUnblockCycles 1473925 # Number of cycles IEW is unblocking
|
system.cpu.iew.iewUnblockCycles 1473970 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iew.iewDispatchedInsts 3078126585 # Number of instructions dispatched to IQ
|
system.cpu.iew.iewDispatchedInsts 3078105405 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iew.iewDispSquashedInsts 12745051 # Number of squashed instructions skipped by dispatch
|
system.cpu.iew.iewDispSquashedInsts 12712072 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iew.iewDispLoadInsts 1045137132 # Number of dispatched load instructions
|
system.cpu.iew.iewDispLoadInsts 1045378245 # Number of dispatched load instructions
|
||||||
system.cpu.iew.iewDispStoreInsts 527476218 # Number of dispatched store instructions
|
system.cpu.iew.iewDispStoreInsts 527599628 # Number of dispatched store instructions
|
||||||
system.cpu.iew.iewDispNonSpecInsts 292477 # Number of dispatched non-speculative instructions
|
system.cpu.iew.iewDispNonSpecInsts 290278 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.iew.iewIQFullEvents 1470662 # Number of times the IQ has become full, causing a stall
|
system.cpu.iew.iewIQFullEvents 1470963 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.iew.iewLSQFullEvents 212 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iew.iewLSQFullEvents 212 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.iew.memOrderViolationEvents 1389738 # Number of memory order violations
|
system.cpu.iew.memOrderViolationEvents 1389984 # Number of memory order violations
|
||||||
system.cpu.iew.predictedTakenIncorrect 34580674 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 34573717 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 8873578 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 8788062 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 43454252 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 43361779 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 2534450261 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 2534356508 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 842463670 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 842568807 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 84841581 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 84813440 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 68452 # number of nop insts executed
|
system.cpu.iew.exec_nop 68544 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 1294415982 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 1294694969 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 344601931 # Number of branches executed
|
system.cpu.iew.exec_branches 344427498 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 451952312 # Number of stores executed
|
system.cpu.iew.exec_stores 452126162 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 1.788847 # Inst execution rate
|
system.cpu.iew.exec_rate 1.789079 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 2495608341 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 2495474043 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 2466623825 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 2466473159 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 1448525550 # num instructions producing a value
|
system.cpu.iew.wb_producers 1448284961 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 2707902616 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 2707735412 # num instructions consuming a value
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.iew.wb_rate 1.740974 # insts written-back per cycle
|
system.cpu.iew.wb_rate 1.741158 # insts written-back per cycle
|
||||||
system.cpu.iew.wb_fanout 0.534925 # average fanout of values written-back
|
system.cpu.iew.wb_fanout 0.534869 # average fanout of values written-back
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.commit.commitCommittedInsts 1885344802 # The number of committed instructions
|
system.cpu.commit.commitCommittedInsts 1885344802 # The number of committed instructions
|
||||||
system.cpu.commit.commitSquashedInsts 1192782047 # The number of squashed insts skipped by commit
|
system.cpu.commit.commitSquashedInsts 1192760864 # The number of squashed insts skipped by commit
|
||||||
system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.commit.branchMispredicts 38420798 # The number of times a branch was mispredicted
|
system.cpu.commit.branchMispredicts 38418907 # The number of times a branch was mispredicted
|
||||||
system.cpu.commit.committed_per_cycle::samples 1198948133 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::samples 1198732893 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.572499 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::mean 1.572781 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::stdev 2.256451 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::stdev 2.256860 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::0 532143962 44.38% 44.38% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::0 532007294 44.38% 44.38% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::1 299077946 24.95% 69.33% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::1 299056293 24.95% 69.33% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::2 106761313 8.90% 78.23% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::2 106726660 8.90% 78.23% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::3 77538501 6.47% 84.70% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::3 77517857 6.47% 84.70% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::4 53400435 4.45% 89.15% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::4 53371752 4.45% 89.15% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::5 23357302 1.95% 91.10% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::5 23357463 1.95% 91.10% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::6 17130441 1.43% 92.53% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::6 17108647 1.43% 92.53% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::7 9348033 0.78% 93.31% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::7 9340003 0.78% 93.31% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::8 80190200 6.69% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::8 80246924 6.69% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::total 1198948133 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::total 1198732893 # Number of insts commited each cycle
|
||||||
system.cpu.commit.count 1885344802 # Number of instructions committed
|
system.cpu.commit.count 1885344802 # Number of instructions committed
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.commit.refs 908385853 # Number of memory references committed
|
system.cpu.commit.refs 908385853 # Number of memory references committed
|
||||||
|
@ -312,50 +311,50 @@ system.cpu.commit.branches 291350232 # Nu
|
||||||
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
|
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
|
||||||
system.cpu.commit.int_insts 1653705623 # Number of committed integer instructions.
|
system.cpu.commit.int_insts 1653705623 # Number of committed integer instructions.
|
||||||
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
|
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
|
||||||
system.cpu.commit.bw_lim_events 80190200 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 80246924 # number cycles where commit BW limit reached
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.rob.rob_reads 4196866437 # The number of ROB reads
|
system.cpu.rob.rob_reads 4196573290 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 6322804382 # The number of ROB writes
|
system.cpu.rob.rob_writes 6322749564 # The number of ROB writes
|
||||||
system.cpu.timesIdled 1340913 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 1340847 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 51328463 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 51326273 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu.committedInsts 1885333786 # Number of Instructions Simulated
|
system.cpu.committedInsts 1885333786 # Number of Instructions Simulated
|
||||||
system.cpu.committedInsts_total 1885333786 # Number of Instructions Simulated
|
system.cpu.committedInsts_total 1885333786 # Number of Instructions Simulated
|
||||||
system.cpu.cpi 0.751488 # CPI: Cycles Per Instruction
|
system.cpu.cpi 0.751363 # CPI: Cycles Per Instruction
|
||||||
system.cpu.cpi_total 0.751488 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 0.751363 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 1.330692 # IPC: Instructions Per Cycle
|
system.cpu.ipc 1.330914 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 1.330692 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 1.330914 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 12567203807 # number of integer regfile reads
|
system.cpu.int_regfile_reads 12567200244 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 2360160094 # number of integer regfile writes
|
system.cpu.int_regfile_writes 2359430733 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 68800597 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 68800397 # number of floating regfile reads
|
||||||
system.cpu.fp_regfile_writes 50187558 # number of floating regfile writes
|
system.cpu.fp_regfile_writes 50191784 # number of floating regfile writes
|
||||||
system.cpu.misc_regfile_reads 3980455481 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 3980708505 # number of misc regfile reads
|
||||||
system.cpu.misc_regfile_writes 13776276 # number of misc regfile writes
|
system.cpu.misc_regfile_writes 13776276 # number of misc regfile writes
|
||||||
system.cpu.icache.replacements 27305 # number of replacements
|
system.cpu.icache.replacements 27241 # number of replacements
|
||||||
system.cpu.icache.tagsinuse 1638.856970 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 1638.335274 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 384199729 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 384162744 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.sampled_refs 28984 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 28920 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.avg_refs 13255.579941 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 13283.635685 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.occ_blocks::0 1638.856970 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 1638.335274 # Average occupied blocks per context
|
||||||
system.cpu.icache.occ_percent::0 0.800223 # Average percentage of cache occupancy
|
system.cpu.icache.occ_percent::0 0.799968 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.ReadReq_hits 384199814 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 384163979 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits 384199814 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 384163979 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits 384199814 # number of overall hits
|
system.cpu.icache.overall_hits 384163979 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses 34151 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 34037 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses 34151 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 34037 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses 34151 # number of overall misses
|
system.cpu.icache.overall_misses 34037 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 301141000 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 300707500 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency 301141000 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 300707500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency 301141000 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 300707500 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses 384233965 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 384198016 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses 384233965 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 384198016 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses 384233965 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 384198016 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 8817.926269 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 8834.723977 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency 8817.926269 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 8834.723977 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency 8817.926269 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 8834.723977 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -365,67 +364,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_mshr_hits 772 # number of ReadReq MSHR hits
|
system.cpu.icache.ReadReq_mshr_hits 775 # number of ReadReq MSHR hits
|
||||||
system.cpu.icache.demand_mshr_hits 772 # number of demand (read+write) MSHR hits
|
system.cpu.icache.demand_mshr_hits 775 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.icache.overall_mshr_hits 772 # number of overall MSHR hits
|
system.cpu.icache.overall_mshr_hits 775 # number of overall MSHR hits
|
||||||
system.cpu.icache.ReadReq_mshr_misses 33379 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 33262 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.demand_mshr_misses 33379 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses 33262 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses 33379 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses 33262 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 180850500 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency 180621500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency 180850500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency 180621500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency 180850500 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency 180621500 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5418.092214 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5430.265769 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 5418.092214 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 5430.265769 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 5418.092214 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 5430.265769 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.replacements 1531788 # number of replacements
|
system.cpu.dcache.replacements 1531781 # number of replacements
|
||||||
system.cpu.dcache.tagsinuse 4094.791932 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 4094.791758 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 1029449306 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 1029515809 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.sampled_refs 1535884 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 1535877 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.avg_refs 670.265011 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 670.311365 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 305577000 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 305571000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.occ_blocks::0 4094.791932 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 4094.791758 # Average occupied blocks per context
|
||||||
system.cpu.dcache.occ_percent::0 0.999705 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_percent::0 0.999705 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.ReadReq_hits 753290045 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 753356755 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits 276118528 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 276118556 # number of WriteReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits 15313 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits 15246 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits 11672 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits 11672 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.demand_hits 1029408573 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 1029475311 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits 1029408573 # number of overall hits
|
system.cpu.dcache.overall_hits 1029475311 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses 1938158 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 1938073 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses 817150 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 817122 # number of WriteReq misses
|
||||||
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
|
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
|
||||||
system.cpu.dcache.demand_misses 2755308 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 2755195 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses 2755308 # number of overall misses
|
system.cpu.dcache.overall_misses 2755195 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency 69348240500 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 69347083500 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency 28488261000 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 28485572000 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency 97836501500 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 97832655500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency 97836501500 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 97832655500 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses 755228203 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 755294828 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses 15316 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses 15249 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses 11672 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses 11672 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses 1032163881 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 1032230506 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses 1032163881 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 1032230506 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.002566 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.002566 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.002951 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.002951 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.000196 # miss rate for LoadLockedReq accesses
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.000197 # miss rate for LoadLockedReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate 0.002669 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.002669 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate 0.002669 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.002669 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 35780.488742 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 35781.461018 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 34862.951722 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 34860.855539 # average WriteReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency 35508.372022 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 35508.432434 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency 35508.372022 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 35508.432434 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 62000 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 62000 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -434,74 +433,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets 15500 # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets 15500 # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks 106544 # number of writebacks
|
system.cpu.dcache.writebacks 106815 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 474971 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits 474897 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 740057 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits 740078 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
|
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits 1215028 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 1214975 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits 1215028 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 1214975 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 1463187 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 1463176 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 77093 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 77044 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses 1540280 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 1540220 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses 1540280 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 1540220 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 50020048000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 50021914000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2484862000 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2483063000 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 52504910000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 52504977000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 52504910000 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 52504977000 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001937 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001937 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000278 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000278 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.001492 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.001492 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.001492 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.001492 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34185.683716 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34187.216029 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32232.005500 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32229.154769 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34087.899603 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 34089.271013 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34087.899603 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 34089.271013 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.replacements 1480006 # number of replacements
|
system.cpu.l2cache.replacements 1480005 # number of replacements
|
||||||
system.cpu.l2cache.tagsinuse 31970.917218 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 31970.457215 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 84924 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 85123 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.sampled_refs 1512726 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 1512725 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 0.056140 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 0.056271 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.occ_blocks::0 29008.328912 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 29003.484666 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 2962.588306 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 2966.972548 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.885264 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.885116 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.090411 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.090545 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.ReadReq_hits 76788 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 76806 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits 106544 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 106815 # number of Writeback hits
|
||||||
system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits
|
system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 6616 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits 6620 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits 83404 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 83426 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits 83404 # number of overall hits
|
system.cpu.l2cache.overall_hits 83426 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses 1415384 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 1415291 # number of ReadReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_misses 4391 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses 4338 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses 1481466 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 1481373 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses 1481466 # number of overall misses
|
system.cpu.l2cache.overall_misses 1481373 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 48555371000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 48556724500 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 2252634000 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 2252633500 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency 50808005000 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 50809358000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency 50808005000 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 50809358000 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses 1492172 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 1492097 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses 106544 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 106815 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_accesses 4395 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses 4342 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses 72698 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 72702 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses 1564870 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 1564799 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 1564870 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 1564799 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.948539 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.948525 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.999090 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.999079 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.908993 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 0.908943 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate 0.946702 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.946686 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate 0.946702 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.946686 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34305.440078 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34308.650659 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34088.465845 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34088.458279 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34295.761766 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 34298.828182 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34295.761766 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34298.828182 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -511,31 +510,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.writebacks 66099 # number of writebacks
|
system.cpu.l2cache.writebacks 66099 # number of writebacks
|
||||||
system.cpu.l2cache.ReadReq_mshr_hits 28 # number of ReadReq MSHR hits
|
system.cpu.l2cache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
|
||||||
system.cpu.l2cache.demand_mshr_hits 28 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_hits 28 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 27 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 1415356 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 1415264 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses 4391 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses 4338 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses 1481438 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 1481346 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses 1481438 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 1481346 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 43973863500 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 43971004500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 136121000 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 134478000 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048597500 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048597500 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 46022461000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 46019602000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 46022461000 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 46019602000 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948521 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948507 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999090 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999079 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908993 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908943 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.946684 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.946669 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.946684 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.946669 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31069.118653 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31069.118200 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.839866 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.839866 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31066.072964 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31066.072342 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31066.072964 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31066.072342 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=false
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=System
|
type=System
|
||||||
children=cpu membus physmem
|
children=cpu membus physmem
|
||||||
|
boot_osflags=a
|
||||||
|
init_param=0
|
||||||
|
kernel=
|
||||||
|
load_addr_mask=1099511627775
|
||||||
mem_mode=atomic
|
mem_mode=atomic
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
|
readfile=
|
||||||
|
symbolfile=
|
||||||
work_begin_ckpt_count=0
|
work_begin_ckpt_count=0
|
||||||
work_begin_cpu_id_exit=-1
|
work_begin_cpu_id_exit=-1
|
||||||
work_begin_exit_count=0
|
work_begin_exit_count=0
|
||||||
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
type=DerivO3CPU
|
type=DerivO3CPU
|
||||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||||
BTBEntries=4096
|
BTBEntries=4096
|
||||||
BTBTagSize=16
|
BTBTagSize=16
|
||||||
LFSTSize=1024
|
LFSTSize=1024
|
||||||
|
@ -52,6 +59,7 @@ decodeWidth=8
|
||||||
defer_registration=false
|
defer_registration=false
|
||||||
dispatchWidth=8
|
dispatchWidth=8
|
||||||
do_checkpoint_insts=true
|
do_checkpoint_insts=true
|
||||||
|
do_quiesce=true
|
||||||
do_statistics_insts=true
|
do_statistics_insts=true
|
||||||
dtb=system.cpu.dtb
|
dtb=system.cpu.dtb
|
||||||
fetchToDecodeDelay=1
|
fetchToDecodeDelay=1
|
||||||
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
||||||
iewToFetchDelay=1
|
iewToFetchDelay=1
|
||||||
iewToRenameDelay=1
|
iewToRenameDelay=1
|
||||||
instShiftAmt=2
|
instShiftAmt=2
|
||||||
|
interrupts=system.cpu.interrupts
|
||||||
issueToExecuteDelay=1
|
issueToExecuteDelay=1
|
||||||
issueWidth=8
|
issueWidth=8
|
||||||
itb=system.cpu.itb
|
itb=system.cpu.itb
|
||||||
|
@ -80,6 +89,7 @@ max_insts_all_threads=0
|
||||||
max_insts_any_thread=0
|
max_insts_any_thread=0
|
||||||
max_loads_all_threads=0
|
max_loads_all_threads=0
|
||||||
max_loads_any_thread=0
|
max_loads_any_thread=0
|
||||||
|
needsTSO=false
|
||||||
numIQEntries=64
|
numIQEntries=64
|
||||||
numPhysFloatRegs=256
|
numPhysFloatRegs=256
|
||||||
numPhysIntRegs=256
|
numPhysIntRegs=256
|
||||||
|
@ -88,6 +98,7 @@ numRobs=1
|
||||||
numThreads=1
|
numThreads=1
|
||||||
phase=0
|
phase=0
|
||||||
predType=tournament
|
predType=tournament
|
||||||
|
profile=0
|
||||||
progress_interval=0
|
progress_interval=0
|
||||||
renameToDecodeDelay=1
|
renameToDecodeDelay=1
|
||||||
renameToFetchDelay=1
|
renameToFetchDelay=1
|
||||||
|
@ -148,7 +159,16 @@ mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
[system.cpu.dtb]
|
[system.cpu.dtb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.dtb.walker
|
||||||
|
|
||||||
|
[system.cpu.dtb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[3]
|
||||||
|
|
||||||
[system.cpu.fuPool]
|
[system.cpu.fuPool]
|
||||||
type=FUPool
|
type=FUPool
|
||||||
|
@ -445,9 +465,21 @@ write_buffers=8
|
||||||
cpu_side=system.cpu.icache_port
|
cpu_side=system.cpu.icache_port
|
||||||
mem_side=system.cpu.toL2Bus.port[0]
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.interrupts]
|
||||||
|
type=ArmInterrupts
|
||||||
|
|
||||||
[system.cpu.itb]
|
[system.cpu.itb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.itb.walker
|
||||||
|
|
||||||
|
[system.cpu.itb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[2]
|
||||||
|
|
||||||
[system.cpu.l2cache]
|
[system.cpu.l2cache]
|
||||||
type=BaseCache
|
type=BaseCache
|
||||||
|
@ -478,7 +510,7 @@ tgts_per_mshr=5
|
||||||
trace_addr=0
|
trace_addr=0
|
||||||
two_queue=false
|
two_queue=false
|
||||||
write_buffers=8
|
write_buffers=8
|
||||||
cpu_side=system.cpu.toL2Bus.port[2]
|
cpu_side=system.cpu.toL2Bus.port[4]
|
||||||
mem_side=system.membus.port[2]
|
mem_side=system.membus.port[2]
|
||||||
|
|
||||||
[system.cpu.toL2Bus]
|
[system.cpu.toL2Bus]
|
||||||
|
@ -489,7 +521,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
[system.cpu.tracer]
|
[system.cpu.tracer]
|
||||||
type=ExeTracer
|
type=ExeTracer
|
||||||
|
@ -497,12 +529,12 @@ type=ExeTracer
|
||||||
[system.cpu.workload]
|
[system.cpu.workload]
|
||||||
type=LiveProcess
|
type=LiveProcess
|
||||||
cmd=vortex lendian.raw
|
cmd=vortex lendian.raw
|
||||||
cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
|
cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
|
||||||
egid=100
|
egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
|
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
|
||||||
gid=100
|
gid=100
|
||||||
input=cin
|
input=cin
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
|
|
|
@ -1,11 +1,13 @@
|
||||||
|
Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout
|
||||||
|
Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 23 2012 04:16:21
|
gem5 compiled Feb 10 2012 00:18:03
|
||||||
gem5 started Jan 23 2012 09:34:51
|
gem5 started Feb 10 2012 00:18:22
|
||||||
gem5 executing on zizzer
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
|
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
Exiting @ tick 31183407000 because target called exit()
|
Exiting @ tick 31189496500 because target called exit()
|
||||||
|
|
|
@ -1,24 +1,24 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.031183 # Number of seconds simulated
|
sim_seconds 0.031189 # Number of seconds simulated
|
||||||
sim_ticks 31183407000 # Number of ticks simulated
|
sim_ticks 31189496500 # Number of ticks simulated
|
||||||
final_tick 31183407000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 31189496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 157932 # Simulator instruction rate (inst/s)
|
host_inst_rate 53036 # Simulator instruction rate (inst/s)
|
||||||
host_tick_rate 48938242 # Simulator tick rate (ticks/s)
|
host_tick_rate 16437569 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 229072 # Number of bytes of host memory used
|
host_mem_usage 264816 # Number of bytes of host memory used
|
||||||
host_seconds 637.20 # Real time elapsed on the host
|
host_seconds 1897.45 # Real time elapsed on the host
|
||||||
sim_insts 100634165 # Number of instructions simulated
|
sim_insts 100634170 # Number of instructions simulated
|
||||||
system.physmem.bytes_read 8651648 # Number of bytes read from this memory
|
system.physmem.bytes_read 8651712 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read 350016 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read 350080 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written 5661184 # Number of bytes written to this memory
|
system.physmem.bytes_written 5661248 # Number of bytes written to this memory
|
||||||
system.physmem.num_reads 135182 # Number of read requests responded to by this memory
|
system.physmem.num_reads 135183 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes 88456 # Number of write requests responded to by this memory
|
system.physmem.num_writes 88457 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||||
system.physmem.bw_read 277443962 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read 277391846 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read 11224431 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read 11224291 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write 181544756 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write 181511362 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total 458988718 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total 458903208 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||||
|
@ -62,143 +62,143 @@ system.cpu.itb.hits 0 # DT
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||||
system.cpu.numCycles 62366815 # number of cpu cycles simulated
|
system.cpu.numCycles 62378994 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.BPredUnit.lookups 17631068 # Number of BP lookups
|
system.cpu.BPredUnit.lookups 17633191 # Number of BP lookups
|
||||||
system.cpu.BPredUnit.condPredicted 11525225 # Number of conditional branches predicted
|
system.cpu.BPredUnit.condPredicted 11526968 # Number of conditional branches predicted
|
||||||
system.cpu.BPredUnit.condIncorrect 822451 # Number of conditional branches incorrect
|
system.cpu.BPredUnit.condIncorrect 822695 # Number of conditional branches incorrect
|
||||||
system.cpu.BPredUnit.BTBLookups 15041021 # Number of BTB lookups
|
system.cpu.BPredUnit.BTBLookups 15043788 # Number of BTB lookups
|
||||||
system.cpu.BPredUnit.BTBHits 9743390 # Number of BTB hits
|
system.cpu.BPredUnit.BTBHits 9743985 # Number of BTB hits
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.BPredUnit.usedRAS 1887340 # Number of times the RAS was used to get a target.
|
system.cpu.BPredUnit.usedRAS 1887457 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.BPredUnit.RASInCorrect 176888 # Number of incorrect RAS predictions.
|
system.cpu.BPredUnit.RASInCorrect 176874 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 12968459 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 12969342 # Number of cycles fetch is stalled on an Icache miss
|
||||||
system.cpu.fetch.Insts 88523933 # Number of instructions fetch has processed
|
system.cpu.fetch.Insts 88531281 # Number of instructions fetch has processed
|
||||||
system.cpu.fetch.Branches 17631068 # Number of branches that fetch encountered
|
system.cpu.fetch.Branches 17633191 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 11630730 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 11631442 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.Cycles 22984896 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.fetch.Cycles 22985471 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
system.cpu.fetch.SquashCycles 2898005 # Number of cycles fetch has spent squashing
|
system.cpu.fetch.SquashCycles 2899094 # Number of cycles fetch has spent squashing
|
||||||
system.cpu.fetch.BlockedCycles 23107334 # Number of cycles fetch has spent blocked
|
system.cpu.fetch.BlockedCycles 23117489 # Number of cycles fetch has spent blocked
|
||||||
system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
system.cpu.fetch.PendingTrapStallCycles 525 # Number of stall cycles due to pending traps
|
system.cpu.fetch.PendingTrapStallCycles 528 # Number of stall cycles due to pending traps
|
||||||
system.cpu.fetch.CacheLines 12208408 # Number of cache lines fetched
|
system.cpu.fetch.CacheLines 12209631 # Number of cache lines fetched
|
||||||
system.cpu.fetch.IcacheSquashes 230644 # Number of outstanding Icache misses that were squashed
|
system.cpu.fetch.IcacheSquashes 231060 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 61059715 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 61072156 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.021356 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.021104 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 3.077680 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 3.077628 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::0 38090584 62.38% 62.38% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::0 38102442 62.39% 62.39% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::1 2437224 3.99% 66.37% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::1 2437370 3.99% 66.38% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::2 2605062 4.27% 70.64% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::2 2604913 4.27% 70.65% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::3 2470326 4.05% 74.69% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::3 2468790 4.04% 74.69% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::4 1717744 2.81% 77.50% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::4 1717886 2.81% 77.50% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::5 1704134 2.79% 80.29% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::5 1703957 2.79% 80.29% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::6 1004081 1.64% 81.93% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::6 1004465 1.64% 81.94% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::7 1295541 2.12% 84.06% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::7 1297144 2.12% 84.06% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::8 9735019 15.94% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::8 9735189 15.94% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 61059715 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 61072156 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.branchRate 0.282700 # Number of branch fetches per cycle
|
system.cpu.fetch.branchRate 0.282678 # Number of branch fetches per cycle
|
||||||
system.cpu.fetch.rate 1.419408 # Number of inst fetches per cycle
|
system.cpu.fetch.rate 1.419248 # Number of inst fetches per cycle
|
||||||
system.cpu.decode.IdleCycles 14872380 # Number of cycles decode is idle
|
system.cpu.decode.IdleCycles 14874533 # Number of cycles decode is idle
|
||||||
system.cpu.decode.BlockedCycles 21838408 # Number of cycles decode is blocked
|
system.cpu.decode.BlockedCycles 21847562 # Number of cycles decode is blocked
|
||||||
system.cpu.decode.RunCycles 21376813 # Number of cycles decode is running
|
system.cpu.decode.RunCycles 21380234 # Number of cycles decode is running
|
||||||
system.cpu.decode.UnblockCycles 1070090 # Number of cycles decode is unblocking
|
system.cpu.decode.UnblockCycles 1066852 # Number of cycles decode is unblocking
|
||||||
system.cpu.decode.SquashCycles 1902024 # Number of cycles decode is squashing
|
system.cpu.decode.SquashCycles 1902975 # Number of cycles decode is squashing
|
||||||
system.cpu.decode.BranchResolved 3467429 # Number of times decode resolved a branch
|
system.cpu.decode.BranchResolved 3467400 # Number of times decode resolved a branch
|
||||||
system.cpu.decode.BranchMispred 98061 # Number of times decode detected a branch misprediction
|
system.cpu.decode.BranchMispred 97940 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.decode.DecodedInsts 120316029 # Number of instructions handled by decode
|
system.cpu.decode.DecodedInsts 120324997 # Number of instructions handled by decode
|
||||||
system.cpu.decode.SquashedInsts 332599 # Number of squashed instructions handled by decode
|
system.cpu.decode.SquashedInsts 332105 # Number of squashed instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 1902024 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 1902975 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 16801594 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 16806585 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 2005674 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 2006065 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 15516104 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 15518837 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 20489827 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 20487124 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 4344492 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 4350570 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 117017437 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 117025506 # Number of instructions processed by rename
|
||||||
system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
|
system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.rename.IQFullEvents 3607 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 3620 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LSQFullEvents 2996198 # Number of times rename has blocked due to LSQ full
|
system.cpu.rename.LSQFullEvents 3001536 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.rename.FullRegisterEvents 60 # Number of times there has been no free registers
|
system.cpu.rename.FullRegisterEvents 62 # Number of times there has been no free registers
|
||||||
system.cpu.rename.RenamedOperands 118959985 # Number of destination operands rename has renamed
|
system.cpu.rename.RenamedOperands 118973415 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenameLookups 538237718 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenameLookups 538271633 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.int_rename_lookups 538236225 # Number of integer rename lookups
|
system.cpu.rename.int_rename_lookups 538269997 # Number of integer rename lookups
|
||||||
system.cpu.rename.fp_rename_lookups 1493 # Number of floating rename lookups
|
system.cpu.rename.fp_rename_lookups 1636 # Number of floating rename lookups
|
||||||
system.cpu.rename.CommittedMaps 99144333 # Number of HB maps that are committed
|
system.cpu.rename.CommittedMaps 99144341 # Number of HB maps that are committed
|
||||||
system.cpu.rename.UndoneMaps 19815652 # Number of HB maps that are undone due to squashing
|
system.cpu.rename.UndoneMaps 19829074 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.rename.serializingInsts 778147 # count of serializing insts renamed
|
system.cpu.rename.serializingInsts 778296 # count of serializing insts renamed
|
||||||
system.cpu.rename.tempSerializingInsts 778546 # count of temporary serializing insts renamed
|
system.cpu.rename.tempSerializingInsts 778691 # count of temporary serializing insts renamed
|
||||||
system.cpu.rename.skidInsts 12135199 # count of insts added to the skid buffer
|
system.cpu.rename.skidInsts 12144889 # count of insts added to the skid buffer
|
||||||
system.cpu.memDep0.insertedLoads 29749057 # Number of loads inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedLoads 29749506 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.insertedStores 22305499 # Number of stores inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedStores 22307130 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.conflictingLoads 2463618 # Number of conflicting loads.
|
system.cpu.memDep0.conflictingLoads 2475389 # Number of conflicting loads.
|
||||||
system.cpu.memDep0.conflictingStores 3436887 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 3455641 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 111737256 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 111742619 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 774255 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 774376 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 107616850 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 107620542 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 306406 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 306039 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 11658627 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 11663320 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 29328565 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 29339036 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 71223 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.iqSquashedNonSpecRemoved 71343 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.iq.issued_per_cycle::samples 61059715 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::samples 61072156 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.762485 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 1.762187 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.902924 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.902803 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 22160160 36.29% 36.29% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 22164835 36.29% 36.29% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 11614525 19.02% 55.31% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 11626045 19.04% 55.33% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 8577298 14.05% 69.36% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 8572984 14.04% 69.37% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 7396039 12.11% 81.47% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 7394656 12.11% 81.47% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 4782616 7.83% 89.31% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 4788181 7.84% 89.32% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::5 3521695 5.77% 95.07% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::5 3517678 5.76% 95.08% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::6 1664317 2.73% 97.80% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::6 1664983 2.73% 97.80% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::7 809749 1.33% 99.13% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::7 808803 1.32% 99.13% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::8 533316 0.87% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::8 533991 0.87% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::total 61059715 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::total 61072156 # Number of insts issued each cycle
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntAlu 88066 3.33% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntAlu 87531 3.32% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntMult 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.32% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemRead 1488278 56.33% 59.66% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemRead 1485029 56.34% 59.66% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemWrite 1065734 40.34% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemWrite 1063128 40.34% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 57002654 52.97% 52.97% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 57005331 52.97% 52.97% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 87399 0.08% 53.05% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 87377 0.08% 53.05% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.05% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.05% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatAdd 39 0.00% 53.05% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatAdd 40 0.00% 53.05% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.05% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.05% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.05% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.05% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.05% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.05% # Type of FU issued
|
||||||
|
@ -224,138 +224,138 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.05% # Ty
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.05% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.05% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.05% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.05% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.05% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.05% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 28992824 26.94% 79.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 28993103 26.94% 79.99% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 21533927 20.01% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 21534684 20.01% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 107616850 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 107620542 # Type of FU issued
|
||||||
system.cpu.iq.rate 1.725547 # Inst issue rate
|
system.cpu.iq.rate 1.725269 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 2642078 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 2635688 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.024551 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.024491 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 279241693 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 279254757 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 124185257 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 124195436 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 105412682 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 105415832 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 206 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 210 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 204 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 218 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 110258821 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 110256122 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 107 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 1870348 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 1866930 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 2440492 # Number of loads squashed
|
system.cpu.iew.lsq.thread0.squashedLoads 2440940 # Number of loads squashed
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 3482 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iew.lsq.thread0.ignoredResponses 3458 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 15956 # Number of memory ordering violations
|
system.cpu.iew.lsq.thread0.memOrderViolation 15970 # Number of memory ordering violations
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 1748305 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 1749935 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 52 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 51 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 52 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 1902024 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 1902975 # Number of cycles IEW is squashing
|
||||||
system.cpu.iew.iewBlockCycles 953128 # Number of cycles IEW is blocking
|
system.cpu.iew.iewBlockCycles 953135 # Number of cycles IEW is blocking
|
||||||
system.cpu.iew.iewUnblockCycles 28578 # Number of cycles IEW is unblocking
|
system.cpu.iew.iewUnblockCycles 28579 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iew.iewDispatchedInsts 112587966 # Number of instructions dispatched to IQ
|
system.cpu.iew.iewDispatchedInsts 112593446 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iew.iewDispSquashedInsts 618611 # Number of squashed instructions skipped by dispatch
|
system.cpu.iew.iewDispSquashedInsts 617881 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iew.iewDispLoadInsts 29749057 # Number of dispatched load instructions
|
system.cpu.iew.iewDispLoadInsts 29749506 # Number of dispatched load instructions
|
||||||
system.cpu.iew.iewDispStoreInsts 22305499 # Number of dispatched store instructions
|
system.cpu.iew.iewDispStoreInsts 22307130 # Number of dispatched store instructions
|
||||||
system.cpu.iew.iewDispNonSpecInsts 756996 # Number of dispatched non-speculative instructions
|
system.cpu.iew.iewDispNonSpecInsts 757118 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.iew.iewIQFullEvents 1135 # Number of times the IQ has become full, causing a stall
|
system.cpu.iew.iewIQFullEvents 1133 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.iew.iewLSQFullEvents 1192 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iew.iewLSQFullEvents 1194 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.iew.memOrderViolationEvents 15956 # Number of memory order violations
|
system.cpu.iew.memOrderViolationEvents 15970 # Number of memory order violations
|
||||||
system.cpu.iew.predictedTakenIncorrect 682416 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 682654 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 198748 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 198883 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 881164 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 881537 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 106274273 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 106278016 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 28622040 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 28622846 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 1342577 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 1342526 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 76455 # number of nop insts executed
|
system.cpu.iew.exec_nop 76451 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 49853649 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 49854993 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 14601408 # Number of branches executed
|
system.cpu.iew.exec_branches 14601868 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 21231609 # Number of stores executed
|
system.cpu.iew.exec_stores 21232147 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 1.704020 # Inst execution rate
|
system.cpu.iew.exec_rate 1.703747 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 105725224 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 105729046 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 105412758 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 105415908 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 52507879 # num instructions producing a value
|
system.cpu.iew.wb_producers 52516965 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 101154765 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 101175097 # num instructions consuming a value
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.iew.wb_rate 1.690206 # insts written-back per cycle
|
system.cpu.iew.wb_rate 1.689926 # insts written-back per cycle
|
||||||
system.cpu.iew.wb_fanout 0.519085 # average fanout of values written-back
|
system.cpu.iew.wb_fanout 0.519070 # average fanout of values written-back
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.commit.commitCommittedInsts 100639717 # The number of committed instructions
|
system.cpu.commit.commitCommittedInsts 100639722 # The number of committed instructions
|
||||||
system.cpu.commit.commitSquashedInsts 11948697 # The number of squashed insts skipped by commit
|
system.cpu.commit.commitSquashedInsts 11954174 # The number of squashed insts skipped by commit
|
||||||
system.cpu.commit.commitNonSpecStalls 703032 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu.commit.commitNonSpecStalls 703033 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.commit.branchMispredicts 788200 # The number of times a branch was mispredicted
|
system.cpu.commit.branchMispredicts 788567 # The number of times a branch was mispredicted
|
||||||
system.cpu.commit.committed_per_cycle::samples 59157692 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::samples 59169182 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.701211 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::mean 1.700881 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::stdev 2.430896 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::stdev 2.430495 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::0 26246617 44.37% 44.37% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::0 26246833 44.36% 44.36% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::1 14635662 24.74% 69.11% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::1 14645427 24.75% 69.11% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::2 4223894 7.14% 76.25% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::2 4228470 7.15% 76.26% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::3 3641491 6.16% 82.40% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::3 3643076 6.16% 82.41% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::4 2268632 3.83% 86.24% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::4 2266929 3.83% 86.25% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::5 1889350 3.19% 89.43% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::5 1888235 3.19% 89.44% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::6 703853 1.19% 90.62% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::6 703093 1.19% 90.62% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::7 498146 0.84% 91.46% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::7 496274 0.84% 91.46% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::8 5050047 8.54% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::8 5050845 8.54% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::total 59157692 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::total 59169182 # Number of insts commited each cycle
|
||||||
system.cpu.commit.count 100639717 # Number of instructions committed
|
system.cpu.commit.count 100639722 # Number of instructions committed
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.commit.refs 47865759 # Number of memory references committed
|
system.cpu.commit.refs 47865761 # Number of memory references committed
|
||||||
system.cpu.commit.loads 27308565 # Number of loads committed
|
system.cpu.commit.loads 27308566 # Number of loads committed
|
||||||
system.cpu.commit.membars 15920 # Number of memory barriers committed
|
system.cpu.commit.membars 15920 # Number of memory barriers committed
|
||||||
system.cpu.commit.branches 13670084 # Number of branches committed
|
system.cpu.commit.branches 13670085 # Number of branches committed
|
||||||
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
|
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
|
||||||
system.cpu.commit.int_insts 91478611 # Number of committed integer instructions.
|
system.cpu.commit.int_insts 91478615 # Number of committed integer instructions.
|
||||||
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
|
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
|
||||||
system.cpu.commit.bw_lim_events 5050047 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 5050845 # number cycles where commit BW limit reached
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.rob.rob_reads 166670760 # The number of ROB reads
|
system.cpu.rob.rob_reads 166686934 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 227084538 # The number of ROB writes
|
system.cpu.rob.rob_writes 227096473 # The number of ROB writes
|
||||||
system.cpu.timesIdled 61622 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 61617 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 1307100 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 1306838 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu.committedInsts 100634165 # Number of Instructions Simulated
|
system.cpu.committedInsts 100634170 # Number of Instructions Simulated
|
||||||
system.cpu.committedInsts_total 100634165 # Number of Instructions Simulated
|
system.cpu.committedInsts_total 100634170 # Number of Instructions Simulated
|
||||||
system.cpu.cpi 0.619738 # CPI: Cycles Per Instruction
|
system.cpu.cpi 0.619859 # CPI: Cycles Per Instruction
|
||||||
system.cpu.cpi_total 0.619738 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 0.619859 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 1.613585 # IPC: Instructions Per Cycle
|
system.cpu.ipc 1.613270 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 1.613585 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 1.613270 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 511657086 # number of integer regfile reads
|
system.cpu.int_regfile_reads 511674990 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 103892124 # number of integer regfile writes
|
system.cpu.int_regfile_writes 103897673 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 166 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 166 # number of floating regfile reads
|
||||||
system.cpu.fp_regfile_writes 126 # number of floating regfile writes
|
system.cpu.fp_regfile_writes 126 # number of floating regfile writes
|
||||||
system.cpu.misc_regfile_reads 146210782 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 146219619 # number of misc regfile reads
|
||||||
system.cpu.misc_regfile_writes 34752 # number of misc regfile writes
|
system.cpu.misc_regfile_writes 34754 # number of misc regfile writes
|
||||||
system.cpu.icache.replacements 26083 # number of replacements
|
system.cpu.icache.replacements 26131 # number of replacements
|
||||||
system.cpu.icache.tagsinuse 1805.405384 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 1805.600642 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 12179175 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 12180358 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.sampled_refs 28115 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 28166 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.avg_refs 433.191357 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 432.448981 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.occ_blocks::0 1805.405384 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 1805.600642 # Average occupied blocks per context
|
||||||
system.cpu.icache.occ_percent::0 0.881546 # Average percentage of cache occupancy
|
system.cpu.icache.occ_percent::0 0.881641 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.ReadReq_hits 12179178 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 12180359 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits 12179178 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 12180359 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits 12179178 # number of overall hits
|
system.cpu.icache.overall_hits 12180359 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses 29230 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 29272 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses 29230 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 29272 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses 29230 # number of overall misses
|
system.cpu.icache.overall_misses 29272 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 357885000 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 357988500 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency 357885000 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 357988500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency 357885000 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 357988500 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses 12208408 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 12209631 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses 12208408 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 12209631 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses 12208408 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 12209631 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.002394 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.002397 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate 0.002394 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.002397 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate 0.002394 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.002397 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 12243.756415 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 12229.724652 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency 12243.756415 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 12229.724652 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency 12243.756415 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 12229.724652 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -365,67 +365,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.writebacks 1 # number of writebacks
|
system.cpu.icache.writebacks 1 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_mshr_hits 1069 # number of ReadReq MSHR hits
|
system.cpu.icache.ReadReq_mshr_hits 1063 # number of ReadReq MSHR hits
|
||||||
system.cpu.icache.demand_mshr_hits 1069 # number of demand (read+write) MSHR hits
|
system.cpu.icache.demand_mshr_hits 1063 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.icache.overall_mshr_hits 1069 # number of overall MSHR hits
|
system.cpu.icache.overall_mshr_hits 1063 # number of overall MSHR hits
|
||||||
system.cpu.icache.ReadReq_mshr_misses 28161 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 28209 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.demand_mshr_misses 28161 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses 28209 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses 28161 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses 28209 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 246973000 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency 247071500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency 246973000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency 247071500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency 246973000 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency 247071500 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.002307 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.002310 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.002307 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate 0.002310 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.002307 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate 0.002310 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8770.036575 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8758.605410 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 8770.036575 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 8758.605410 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 8770.036575 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 8758.605410 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.replacements 157879 # number of replacements
|
system.cpu.dcache.replacements 157892 # number of replacements
|
||||||
system.cpu.dcache.tagsinuse 4072.329363 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 4072.334227 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 44742203 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 44746410 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.sampled_refs 161975 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 161988 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.avg_refs 276.229066 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 276.232869 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 306596000 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 306594000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.occ_blocks::0 4072.329363 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 4072.334227 # Average occupied blocks per context
|
||||||
system.cpu.dcache.occ_percent::0 0.994221 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_percent::0 0.994222 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.ReadReq_hits 26395464 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 26399659 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits 18310275 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 18310286 # number of WriteReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits 18919 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits 18924 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits 17375 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits 17376 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.demand_hits 44705739 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 44709945 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits 44705739 # number of overall hits
|
system.cpu.dcache.overall_hits 44709945 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses 108834 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 108879 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses 1539626 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 1539615 # number of WriteReq misses
|
||||||
system.cpu.dcache.LoadLockedReq_misses 27 # number of LoadLockedReq misses
|
system.cpu.dcache.LoadLockedReq_misses 26 # number of LoadLockedReq misses
|
||||||
system.cpu.dcache.demand_misses 1648460 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 1648494 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses 1648460 # number of overall misses
|
system.cpu.dcache.overall_misses 1648494 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency 2418698500 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 2418798500 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency 52283649500 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 52283607500 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency 386000 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency 349000 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency 54702348000 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 54702406000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency 54702348000 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 54702406000 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses 26504298 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 26508538 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses 18946 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses 18950 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses 17375 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses 17376 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses 46354199 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 46358439 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses 46354199 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 46358439 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.004106 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.004107 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.077563 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.077563 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.001425 # miss rate for LoadLockedReq accesses
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.001372 # miss rate for LoadLockedReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate 0.035562 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.035560 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate 0.035562 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.035560 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 22223.739824 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 22215.473140 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 33958.668859 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 33958.884202 # average WriteReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 14296.296296 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 13423.076923 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency 33183.909831 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 33183.260600 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency 33183.909831 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 33183.260600 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -434,74 +434,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks 123472 # number of writebacks
|
system.cpu.dcache.writebacks 123473 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 53734 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits 53766 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 1432703 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits 1432695 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_hits 27 # number of LoadLockedReq MSHR hits
|
system.cpu.dcache.LoadLockedReq_mshr_hits 26 # number of LoadLockedReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits 1486437 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 1486461 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits 1486437 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 1486461 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 55100 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 55113 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 106923 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 106920 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses 162023 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 162033 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses 162023 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 162033 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1035726000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1035745500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3662471000 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 3662420000 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 4698197000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 4698165500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 4698197000 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 4698165500 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002079 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002079 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005387 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005386 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.003495 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.003495 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.003495 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.003495 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18797.205082 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18793.125034 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34253.350542 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34253.834643 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 28997.099177 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 28995.115193 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 28997.099177 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 28995.115193 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.replacements 114920 # number of replacements
|
system.cpu.l2cache.replacements 114916 # number of replacements
|
||||||
system.cpu.l2cache.tagsinuse 18304.700184 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 18304.706842 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 72415 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 72481 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.sampled_refs 133774 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 133774 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 0.541323 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 0.541817 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.occ_blocks::0 2370.650310 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 2370.559791 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 15934.049874 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 15934.147051 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.072347 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.072344 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.486269 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.486272 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.ReadReq_hits 50510 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 50571 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits 123473 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 123474 # number of Writeback hits
|
||||||
system.cpu.l2cache.UpgradeReq_hits 16 # number of UpgradeReq hits
|
system.cpu.l2cache.UpgradeReq_hits 14 # number of UpgradeReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 4309 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits 4310 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits 54819 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 54881 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits 54819 # number of overall hits
|
system.cpu.l2cache.overall_hits 54881 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses 32664 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 32667 # number of ReadReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_misses 31 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses 30 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses 102598 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 102597 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses 135262 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 135264 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses 135262 # number of overall misses
|
system.cpu.l2cache.overall_misses 135264 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 1118309000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 1118379000 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 3526121000 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 3526118000 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency 4644430000 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 4644497000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency 4644430000 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 4644497000 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses 83174 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 83238 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses 123473 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 123474 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_accesses 47 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses 44 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses 106907 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 106907 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses 190081 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 190145 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 190081 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 190145 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.392719 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.392453 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.659574 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.681818 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.959694 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 0.959685 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate 0.711602 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.711373 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate 0.711602 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.711373 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34236.743816 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34235.742492 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.321020 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.626763 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34336.546850 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 34336.534481 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34336.546850 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34336.534481 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -510,32 +510,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.writebacks 88456 # number of writebacks
|
system.cpu.l2cache.writebacks 88457 # number of writebacks
|
||||||
system.cpu.l2cache.ReadReq_mshr_hits 80 # number of ReadReq MSHR hits
|
system.cpu.l2cache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits
|
||||||
system.cpu.l2cache.demand_mshr_hits 80 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 81 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_hits 80 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 81 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 32584 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 32586 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses 30 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 102598 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 102597 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses 135182 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 135183 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses 135182 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 135183 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1012754000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1012814500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 962000 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 931000 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197891500 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197894500 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 4210645500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 4210709000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 4210645500 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 4210709000 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.391757 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.391480 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.659574 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.681818 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959694 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959685 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.711181 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.710947 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.711181 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.710947 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.328259 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.277236 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31032.258065 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31033.333333 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31169.140724 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31169.473766 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31147.974582 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31148.213903 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31147.974582 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31148.213903 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=false
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=System
|
type=System
|
||||||
children=cpu membus physmem
|
children=cpu membus physmem
|
||||||
|
boot_osflags=a
|
||||||
|
init_param=0
|
||||||
|
kernel=
|
||||||
|
load_addr_mask=1099511627775
|
||||||
mem_mode=atomic
|
mem_mode=atomic
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
|
readfile=
|
||||||
|
symbolfile=
|
||||||
work_begin_ckpt_count=0
|
work_begin_ckpt_count=0
|
||||||
work_begin_cpu_id_exit=-1
|
work_begin_cpu_id_exit=-1
|
||||||
work_begin_exit_count=0
|
work_begin_exit_count=0
|
||||||
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
type=DerivO3CPU
|
type=DerivO3CPU
|
||||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||||
BTBEntries=4096
|
BTBEntries=4096
|
||||||
BTBTagSize=16
|
BTBTagSize=16
|
||||||
LFSTSize=1024
|
LFSTSize=1024
|
||||||
|
@ -52,6 +59,7 @@ decodeWidth=8
|
||||||
defer_registration=false
|
defer_registration=false
|
||||||
dispatchWidth=8
|
dispatchWidth=8
|
||||||
do_checkpoint_insts=true
|
do_checkpoint_insts=true
|
||||||
|
do_quiesce=true
|
||||||
do_statistics_insts=true
|
do_statistics_insts=true
|
||||||
dtb=system.cpu.dtb
|
dtb=system.cpu.dtb
|
||||||
fetchToDecodeDelay=1
|
fetchToDecodeDelay=1
|
||||||
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
||||||
iewToFetchDelay=1
|
iewToFetchDelay=1
|
||||||
iewToRenameDelay=1
|
iewToRenameDelay=1
|
||||||
instShiftAmt=2
|
instShiftAmt=2
|
||||||
|
interrupts=system.cpu.interrupts
|
||||||
issueToExecuteDelay=1
|
issueToExecuteDelay=1
|
||||||
issueWidth=8
|
issueWidth=8
|
||||||
itb=system.cpu.itb
|
itb=system.cpu.itb
|
||||||
|
@ -80,6 +89,7 @@ max_insts_all_threads=0
|
||||||
max_insts_any_thread=0
|
max_insts_any_thread=0
|
||||||
max_loads_all_threads=0
|
max_loads_all_threads=0
|
||||||
max_loads_any_thread=0
|
max_loads_any_thread=0
|
||||||
|
needsTSO=false
|
||||||
numIQEntries=64
|
numIQEntries=64
|
||||||
numPhysFloatRegs=256
|
numPhysFloatRegs=256
|
||||||
numPhysIntRegs=256
|
numPhysIntRegs=256
|
||||||
|
@ -88,6 +98,7 @@ numRobs=1
|
||||||
numThreads=1
|
numThreads=1
|
||||||
phase=0
|
phase=0
|
||||||
predType=tournament
|
predType=tournament
|
||||||
|
profile=0
|
||||||
progress_interval=0
|
progress_interval=0
|
||||||
renameToDecodeDelay=1
|
renameToDecodeDelay=1
|
||||||
renameToFetchDelay=1
|
renameToFetchDelay=1
|
||||||
|
@ -148,7 +159,16 @@ mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
[system.cpu.dtb]
|
[system.cpu.dtb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.dtb.walker
|
||||||
|
|
||||||
|
[system.cpu.dtb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[3]
|
||||||
|
|
||||||
[system.cpu.fuPool]
|
[system.cpu.fuPool]
|
||||||
type=FUPool
|
type=FUPool
|
||||||
|
@ -445,9 +465,21 @@ write_buffers=8
|
||||||
cpu_side=system.cpu.icache_port
|
cpu_side=system.cpu.icache_port
|
||||||
mem_side=system.cpu.toL2Bus.port[0]
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.interrupts]
|
||||||
|
type=ArmInterrupts
|
||||||
|
|
||||||
[system.cpu.itb]
|
[system.cpu.itb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.itb.walker
|
||||||
|
|
||||||
|
[system.cpu.itb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[2]
|
||||||
|
|
||||||
[system.cpu.l2cache]
|
[system.cpu.l2cache]
|
||||||
type=BaseCache
|
type=BaseCache
|
||||||
|
@ -478,7 +510,7 @@ tgts_per_mshr=5
|
||||||
trace_addr=0
|
trace_addr=0
|
||||||
two_queue=false
|
two_queue=false
|
||||||
write_buffers=8
|
write_buffers=8
|
||||||
cpu_side=system.cpu.toL2Bus.port[2]
|
cpu_side=system.cpu.toL2Bus.port[4]
|
||||||
mem_side=system.membus.port[2]
|
mem_side=system.membus.port[2]
|
||||||
|
|
||||||
[system.cpu.toL2Bus]
|
[system.cpu.toL2Bus]
|
||||||
|
@ -489,7 +521,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
[system.cpu.tracer]
|
[system.cpu.tracer]
|
||||||
type=ExeTracer
|
type=ExeTracer
|
||||||
|
@ -497,12 +529,12 @@ type=ExeTracer
|
||||||
[system.cpu.workload]
|
[system.cpu.workload]
|
||||||
type=LiveProcess
|
type=LiveProcess
|
||||||
cmd=bzip2 input.source 1
|
cmd=bzip2 input.source 1
|
||||||
cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
|
cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
|
||||||
egid=100
|
egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
|
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
|
||||||
gid=100
|
gid=100
|
||||||
input=cin
|
input=cin
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
|
|
|
@ -1,10 +1,12 @@
|
||||||
|
Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout
|
||||||
|
Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 23 2012 04:16:21
|
gem5 compiled Feb 10 2012 00:18:03
|
||||||
gem5 started Jan 23 2012 09:36:09
|
gem5 started Feb 10 2012 00:18:20
|
||||||
gem5 executing on zizzer
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
|
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
spec_init
|
spec_init
|
||||||
|
@ -24,4 +26,4 @@ Uncompressing Data
|
||||||
Uncompressed data 1048576 bytes in length
|
Uncompressed data 1048576 bytes in length
|
||||||
Uncompressed data compared correctly
|
Uncompressed data compared correctly
|
||||||
Tested 1MB buffer: OK!
|
Tested 1MB buffer: OK!
|
||||||
Exiting @ tick 483463019500 because target called exit()
|
Exiting @ tick 483300356500 because target called exit()
|
||||||
|
|
|
@ -1,24 +1,24 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.483463 # Number of seconds simulated
|
sim_seconds 0.483300 # Number of seconds simulated
|
||||||
sim_ticks 483463019500 # Number of ticks simulated
|
sim_ticks 483300356500 # Number of ticks simulated
|
||||||
final_tick 483463019500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 483300356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 152421 # Simulator instruction rate (inst/s)
|
host_inst_rate 96252 # Simulator instruction rate (inst/s)
|
||||||
host_tick_rate 42766664 # Simulator tick rate (ticks/s)
|
host_tick_rate 26997552 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 220608 # Number of bytes of host memory used
|
host_mem_usage 256412 # Number of bytes of host memory used
|
||||||
host_seconds 11304.67 # Real time elapsed on the host
|
host_seconds 17901.64 # Real time elapsed on the host
|
||||||
sim_insts 1723073849 # Number of instructions simulated
|
sim_insts 1723073849 # Number of instructions simulated
|
||||||
system.physmem.bytes_read 188174592 # Number of bytes read from this memory
|
system.physmem.bytes_read 188191232 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read 45888 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read 45952 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written 77926272 # Number of bytes written to this memory
|
system.physmem.bytes_written 77928320 # Number of bytes written to this memory
|
||||||
system.physmem.num_reads 2940228 # Number of read requests responded to by this memory
|
system.physmem.num_reads 2940488 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes 1217598 # Number of write requests responded to by this memory
|
system.physmem.num_writes 1217630 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||||
system.physmem.bw_read 389222307 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read 389387737 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read 94915 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read 95080 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write 161183522 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write 161242008 # Write bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total 550405829 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total 550629745 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||||
|
@ -62,141 +62,141 @@ system.cpu.itb.hits 0 # DT
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||||
system.cpu.numCycles 966926040 # number of cpu cycles simulated
|
system.cpu.numCycles 966600714 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.BPredUnit.lookups 298898243 # Number of BP lookups
|
system.cpu.BPredUnit.lookups 298802813 # Number of BP lookups
|
||||||
system.cpu.BPredUnit.condPredicted 243989412 # Number of conditional branches predicted
|
system.cpu.BPredUnit.condPredicted 243899992 # Number of conditional branches predicted
|
||||||
system.cpu.BPredUnit.condIncorrect 18339920 # Number of conditional branches incorrect
|
system.cpu.BPredUnit.condIncorrect 18315213 # Number of conditional branches incorrect
|
||||||
system.cpu.BPredUnit.BTBLookups 264347245 # Number of BTB lookups
|
system.cpu.BPredUnit.BTBLookups 264194846 # Number of BTB lookups
|
||||||
system.cpu.BPredUnit.BTBHits 238745657 # Number of BTB hits
|
system.cpu.BPredUnit.BTBHits 238628617 # Number of BTB hits
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.BPredUnit.usedRAS 17668157 # Number of times the RAS was used to get a target.
|
system.cpu.BPredUnit.usedRAS 17678661 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.BPredUnit.RASInCorrect 3423 # Number of incorrect RAS predictions.
|
system.cpu.BPredUnit.RASInCorrect 3338 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 295953389 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 296004888 # Number of cycles fetch is stalled on an Icache miss
|
||||||
system.cpu.fetch.Insts 2175230772 # Number of instructions fetch has processed
|
system.cpu.fetch.Insts 2174228266 # Number of instructions fetch has processed
|
||||||
system.cpu.fetch.Branches 298898243 # Number of branches that fetch encountered
|
system.cpu.fetch.Branches 298802813 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 256413814 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 256307278 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.Cycles 484717826 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.fetch.Cycles 484507329 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
system.cpu.fetch.SquashCycles 87053301 # Number of cycles fetch has spent squashing
|
system.cpu.fetch.SquashCycles 86919023 # Number of cycles fetch has spent squashing
|
||||||
system.cpu.fetch.BlockedCycles 107577195 # Number of cycles fetch has spent blocked
|
system.cpu.fetch.BlockedCycles 107617273 # Number of cycles fetch has spent blocked
|
||||||
system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps
|
system.cpu.fetch.PendingTrapStallCycles 140 # Number of stall cycles due to pending traps
|
||||||
system.cpu.fetch.CacheLines 285045078 # Number of cache lines fetched
|
system.cpu.fetch.CacheLines 285078339 # Number of cache lines fetched
|
||||||
system.cpu.fetch.IcacheSquashes 5311594 # Number of outstanding Icache misses that were squashed
|
system.cpu.fetch.IcacheSquashes 5300000 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 956547645 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 956319158 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.521914 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.521362 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 3.026495 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 3.026261 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::0 471829873 49.33% 49.33% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::0 471811881 49.34% 49.34% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::1 35367236 3.70% 53.02% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::1 35281645 3.69% 53.03% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::2 65085859 6.80% 59.83% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::2 65131283 6.81% 59.84% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::3 66860371 6.99% 66.82% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::3 66854544 6.99% 66.83% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::4 46850107 4.90% 71.72% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::4 46816923 4.90% 71.72% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::5 59747954 6.25% 77.96% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::5 59777101 6.25% 77.97% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::6 54343246 5.68% 83.64% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::6 54237422 5.67% 83.64% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::7 17692463 1.85% 85.49% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::7 17725648 1.85% 85.50% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::8 138770536 14.51% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::8 138682711 14.50% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 956547645 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 956319158 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.branchRate 0.309122 # Number of branch fetches per cycle
|
system.cpu.fetch.branchRate 0.309127 # Number of branch fetches per cycle
|
||||||
system.cpu.fetch.rate 2.249635 # Number of inst fetches per cycle
|
system.cpu.fetch.rate 2.249355 # Number of inst fetches per cycle
|
||||||
system.cpu.decode.IdleCycles 322987122 # Number of cycles decode is idle
|
system.cpu.decode.IdleCycles 322991638 # Number of cycles decode is idle
|
||||||
system.cpu.decode.BlockedCycles 92097194 # Number of cycles decode is blocked
|
system.cpu.decode.BlockedCycles 92138952 # Number of cycles decode is blocked
|
||||||
system.cpu.decode.RunCycles 459538157 # Number of cycles decode is running
|
system.cpu.decode.RunCycles 459388324 # Number of cycles decode is running
|
||||||
system.cpu.decode.UnblockCycles 13626726 # Number of cycles decode is unblocking
|
system.cpu.decode.UnblockCycles 13611363 # Number of cycles decode is unblocking
|
||||||
system.cpu.decode.SquashCycles 68298446 # Number of cycles decode is squashing
|
system.cpu.decode.SquashCycles 68188881 # Number of cycles decode is squashing
|
||||||
system.cpu.decode.BranchResolved 46874540 # Number of times decode resolved a branch
|
system.cpu.decode.BranchResolved 46868404 # Number of times decode resolved a branch
|
||||||
system.cpu.decode.BranchMispred 671 # Number of times decode detected a branch misprediction
|
system.cpu.decode.BranchMispred 664 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.decode.DecodedInsts 2352694278 # Number of instructions handled by decode
|
system.cpu.decode.DecodedInsts 2351885426 # Number of instructions handled by decode
|
||||||
system.cpu.decode.SquashedInsts 2235 # Number of squashed instructions handled by decode
|
system.cpu.decode.SquashedInsts 2233 # Number of squashed instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 68298446 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 68188881 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 343127088 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 343108382 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 46537686 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 46584354 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 27220 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 25758 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 451783493 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 451644595 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 46773712 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 46767188 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 2295847883 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 2295012184 # Number of instructions processed by rename
|
||||||
system.cpu.rename.ROBFullEvents 19963 # Number of times rename has blocked due to ROB full
|
system.cpu.rename.ROBFullEvents 19840 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.rename.IQFullEvents 2697037 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 2699078 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LSQFullEvents 37730930 # Number of times rename has blocked due to LSQ full
|
system.cpu.rename.LSQFullEvents 37731214 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers
|
system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers
|
||||||
system.cpu.rename.RenamedOperands 2264588148 # Number of destination operands rename has renamed
|
system.cpu.rename.RenamedOperands 2263685405 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenameLookups 10605407368 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenameLookups 10601312044 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.int_rename_lookups 10605405778 # Number of integer rename lookups
|
system.cpu.rename.int_rename_lookups 10601310861 # Number of integer rename lookups
|
||||||
system.cpu.rename.fp_rename_lookups 1590 # Number of floating rename lookups
|
system.cpu.rename.fp_rename_lookups 1183 # Number of floating rename lookups
|
||||||
system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed
|
system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed
|
||||||
system.cpu.rename.UndoneMaps 558268197 # Number of HB maps that are undone due to squashing
|
system.cpu.rename.UndoneMaps 557365454 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.rename.serializingInsts 10043 # count of serializing insts renamed
|
system.cpu.rename.serializingInsts 9613 # count of serializing insts renamed
|
||||||
system.cpu.rename.tempSerializingInsts 10038 # count of temporary serializing insts renamed
|
system.cpu.rename.tempSerializingInsts 9609 # count of temporary serializing insts renamed
|
||||||
system.cpu.rename.skidInsts 98804137 # count of insts added to the skid buffer
|
system.cpu.rename.skidInsts 98574159 # count of insts added to the skid buffer
|
||||||
system.cpu.memDep0.insertedLoads 618742816 # Number of loads inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedLoads 618665433 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.insertedStores 222099567 # Number of stores inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedStores 221947140 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.conflictingLoads 74239442 # Number of conflicting loads.
|
system.cpu.memDep0.conflictingLoads 73974093 # Number of conflicting loads.
|
||||||
system.cpu.memDep0.conflictingStores 61602093 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 60832432 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 2187718033 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 2187079584 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 2090 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 2062 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 2018498325 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 2018219576 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 3274725 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 3314512 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 458502719 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 457863024 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 1049949895 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 1047846495 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 1587 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.iqSquashedNonSpecRemoved 1559 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.iq.issued_per_cycle::samples 956547645 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::samples 956319158 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::mean 2.110191 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 2.110404 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.840946 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.840875 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 262039584 27.39% 27.39% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 261846751 27.38% 27.38% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 150878554 15.77% 43.17% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 150992981 15.79% 43.17% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 168430661 17.61% 60.78% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 168342829 17.60% 60.77% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 136432052 14.26% 75.04% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 136328017 14.26% 75.03% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 124835406 13.05% 88.09% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 124939866 13.06% 88.09% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::5 73540708 7.69% 95.78% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::5 73493141 7.69% 95.78% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::6 29241453 3.06% 98.83% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::6 29213551 3.05% 98.83% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::7 10225405 1.07% 99.90% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::7 10245765 1.07% 99.90% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::8 923822 0.10% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::8 916257 0.10% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::total 956547645 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::total 956319158 # Number of insts issued each cycle
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntAlu 901388 3.68% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntAlu 899945 3.67% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntMult 177 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntMult 187 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.67% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemRead 19016870 77.70% 81.38% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemRead 19005921 77.47% 81.14% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemWrite 4557312 18.62% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemWrite 4627423 18.86% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 1238993791 61.38% 61.38% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 1238740250 61.38% 61.38% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 1017752 0.05% 61.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 1017622 0.05% 61.43% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.43% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.43% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued
|
||||||
|
@ -218,91 +218,91 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Ty
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCvt 14 0.00% 61.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.43% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.43% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMisc 13 0.00% 61.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.43% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 2 0.00% 61.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 583952461 28.93% 90.36% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 583895352 28.93% 90.36% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 194534287 9.64% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 194566336 9.64% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 2018498325 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 2018219576 # Type of FU issued
|
||||||
system.cpu.iq.rate 2.087542 # Inst issue rate
|
system.cpu.iq.rate 2.087956 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 24475747 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 24533476 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.012126 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.012156 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 5021294480 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 5020606045 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 2646401011 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 2645122896 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1958335598 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1958251270 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 287 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 253 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 294 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 2042973928 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 2042752922 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 144 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 130 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 55719619 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 55694024 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 132816045 # Number of loads squashed
|
system.cpu.iew.lsq.thread0.squashedLoads 132738662 # Number of loads squashed
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 210497 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iew.lsq.thread0.ignoredResponses 211257 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 180679 # Number of memory ordering violations
|
system.cpu.iew.lsq.thread0.memOrderViolation 180594 # Number of memory ordering violations
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 47252521 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 47100094 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 451790 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 451914 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 68298446 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 68188881 # Number of cycles IEW is squashing
|
||||||
system.cpu.iew.iewBlockCycles 22155006 # Number of cycles IEW is blocking
|
system.cpu.iew.iewBlockCycles 22161421 # Number of cycles IEW is blocking
|
||||||
system.cpu.iew.iewUnblockCycles 1213609 # Number of cycles IEW is unblocking
|
system.cpu.iew.iewUnblockCycles 1213363 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iew.iewDispatchedInsts 2187738627 # Number of instructions dispatched to IQ
|
system.cpu.iew.iewDispatchedInsts 2187099355 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iew.iewDispSquashedInsts 7300026 # Number of squashed instructions skipped by dispatch
|
system.cpu.iew.iewDispSquashedInsts 7278228 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iew.iewDispLoadInsts 618742816 # Number of dispatched load instructions
|
system.cpu.iew.iewDispLoadInsts 618665433 # Number of dispatched load instructions
|
||||||
system.cpu.iew.iewDispStoreInsts 222099567 # Number of dispatched store instructions
|
system.cpu.iew.iewDispStoreInsts 221947140 # Number of dispatched store instructions
|
||||||
system.cpu.iew.iewDispNonSpecInsts 2027 # Number of dispatched non-speculative instructions
|
system.cpu.iew.iewDispNonSpecInsts 1999 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.iew.iewIQFullEvents 219640 # Number of times the IQ has become full, causing a stall
|
system.cpu.iew.iewIQFullEvents 219629 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.iew.iewLSQFullEvents 61277 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iew.iewLSQFullEvents 61218 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.iew.memOrderViolationEvents 180679 # Number of memory order violations
|
system.cpu.iew.memOrderViolationEvents 180594 # Number of memory order violations
|
||||||
system.cpu.iew.predictedTakenIncorrect 18953795 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 18897487 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 1821941 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 1819209 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 20775736 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 20716696 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 1986087052 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 1985947715 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 570299160 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 570245268 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 32411273 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 32271861 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 18504 # number of nop insts executed
|
system.cpu.iew.exec_nop 17709 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 761501875 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 761448250 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 238650211 # Number of branches executed
|
system.cpu.iew.exec_branches 238637230 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 191202715 # Number of stores executed
|
system.cpu.iew.exec_stores 191202982 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 2.054022 # Inst execution rate
|
system.cpu.iew.exec_rate 2.054569 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 1967277607 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 1967185295 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 1958335722 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 1958251378 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 1288034280 # num instructions producing a value
|
system.cpu.iew.wb_producers 1288041557 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 2036866160 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 2036752533 # num instructions consuming a value
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.iew.wb_rate 2.025321 # insts written-back per cycle
|
system.cpu.iew.wb_rate 2.025916 # insts written-back per cycle
|
||||||
system.cpu.iew.wb_fanout 0.632361 # average fanout of values written-back
|
system.cpu.iew.wb_fanout 0.632400 # average fanout of values written-back
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions
|
system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions
|
||||||
system.cpu.commit.commitSquashedInsts 464746992 # The number of squashed insts skipped by commit
|
system.cpu.commit.commitSquashedInsts 464107908 # The number of squashed insts skipped by commit
|
||||||
system.cpu.commit.commitNonSpecStalls 503 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu.commit.commitNonSpecStalls 503 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.commit.branchMispredicts 18339818 # The number of times a branch was mispredicted
|
system.cpu.commit.branchMispredicts 18315306 # The number of times a branch was mispredicted
|
||||||
system.cpu.commit.committed_per_cycle::samples 888249200 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::samples 888130278 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.939854 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::mean 1.940114 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::stdev 2.672088 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::stdev 2.672278 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::0 383075847 43.13% 43.13% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::0 382955223 43.12% 43.12% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::1 200735352 22.60% 65.73% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::1 200739073 22.60% 65.72% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::2 81917807 9.22% 74.95% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::2 81923550 9.22% 74.95% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::3 38649475 4.35% 79.30% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::3 38679338 4.36% 79.30% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::4 19675094 2.22% 81.51% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::4 19675426 2.22% 81.52% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::5 31029952 3.49% 85.01% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::5 30976281 3.49% 85.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::6 22284246 2.51% 87.52% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::6 22277703 2.51% 87.51% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::7 12052552 1.36% 88.87% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::7 12029119 1.35% 88.87% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::8 98828875 11.13% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::8 98874565 11.13% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::total 888249200 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::total 888130278 # Number of insts commited each cycle
|
||||||
system.cpu.commit.count 1723073867 # Number of instructions committed
|
system.cpu.commit.count 1723073867 # Number of instructions committed
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.commit.refs 660773817 # Number of memory references committed
|
system.cpu.commit.refs 660773817 # Number of memory references committed
|
||||||
|
@ -312,50 +312,50 @@ system.cpu.commit.branches 213462365 # Nu
|
||||||
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
||||||
system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions.
|
system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions.
|
||||||
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
||||||
system.cpu.commit.bw_lim_events 98828875 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 98874565 # number cycles where commit BW limit reached
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.rob.rob_reads 2977240585 # The number of ROB reads
|
system.cpu.rob.rob_reads 2976436889 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 4444170390 # The number of ROB writes
|
system.cpu.rob.rob_writes 4442782654 # The number of ROB writes
|
||||||
system.cpu.timesIdled 920776 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 920078 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 10378395 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 10281556 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu.committedInsts 1723073849 # Number of Instructions Simulated
|
system.cpu.committedInsts 1723073849 # Number of Instructions Simulated
|
||||||
system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated
|
system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated
|
||||||
system.cpu.cpi 0.561163 # CPI: Cycles Per Instruction
|
system.cpu.cpi 0.560975 # CPI: Cycles Per Instruction
|
||||||
system.cpu.cpi_total 0.561163 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 0.560975 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 1.782012 # IPC: Instructions Per Cycle
|
system.cpu.ipc 1.782612 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 1.782012 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 1.782612 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 9942029327 # number of integer regfile reads
|
system.cpu.int_regfile_reads 9941434858 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 1939848996 # number of integer regfile writes
|
system.cpu.int_regfile_writes 1939754373 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 117 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 96 # number of floating regfile reads
|
||||||
system.cpu.fp_regfile_writes 59 # number of floating regfile writes
|
system.cpu.fp_regfile_writes 31 # number of floating regfile writes
|
||||||
system.cpu.misc_regfile_reads 2913839911 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 2912823996 # number of misc regfile reads
|
||||||
system.cpu.misc_regfile_writes 126 # number of misc regfile writes
|
system.cpu.misc_regfile_writes 126 # number of misc regfile writes
|
||||||
system.cpu.icache.replacements 10 # number of replacements
|
system.cpu.icache.replacements 10 # number of replacements
|
||||||
system.cpu.icache.tagsinuse 609.858480 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 609.966952 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 285044064 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 285077321 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.sampled_refs 744 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.avg_refs 383123.741935 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 382141.180965 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.occ_blocks::0 609.858480 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 609.966952 # Average occupied blocks per context
|
||||||
system.cpu.icache.occ_percent::0 0.297782 # Average percentage of cache occupancy
|
system.cpu.icache.occ_percent::0 0.297835 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.ReadReq_hits 285044064 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 285077321 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits 285044064 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 285077321 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits 285044064 # number of overall hits
|
system.cpu.icache.overall_hits 285077321 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses 1014 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 1018 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses 1014 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 1018 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses 1014 # number of overall misses
|
system.cpu.icache.overall_misses 1018 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 35191500 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 35270500 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency 35191500 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 35270500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency 35191500 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 35270500 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses 285045078 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 285078339 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses 285045078 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 285078339 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses 285045078 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 285078339 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 34705.621302 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 34646.856582 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency 34705.621302 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 34646.856582 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency 34705.621302 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 34646.856582 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -365,169 +365,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits
|
system.cpu.icache.ReadReq_mshr_hits 272 # number of ReadReq MSHR hits
|
||||||
system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits
|
system.cpu.icache.demand_mshr_hits 272 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits
|
system.cpu.icache.overall_mshr_hits 272 # number of overall MSHR hits
|
||||||
system.cpu.icache.ReadReq_mshr_misses 744 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 746 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.demand_mshr_misses 744 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses 746 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses 744 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses 746 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 25627000 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency 25653000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency 25627000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency 25653000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency 25627000 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency 25653000 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34444.892473 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34387.399464 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 34444.892473 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 34387.399464 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 34444.892473 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 34387.399464 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.replacements 9570827 # number of replacements
|
system.cpu.dcache.replacements 9570609 # number of replacements
|
||||||
system.cpu.dcache.tagsinuse 4087.732038 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 4087.729265 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 666909210 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 666885051 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.sampled_refs 9574923 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 9574705 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.avg_refs 69.651653 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 69.650715 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 3484303000 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 3484295000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.occ_blocks::0 4087.732038 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 4087.729265 # Average occupied blocks per context
|
||||||
system.cpu.dcache.occ_percent::0 0.997981 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_percent::0 0.997981 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.ReadReq_hits 499513800 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 499489564 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits 167395288 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 167395365 # number of WriteReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits 60 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits 60 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits 62 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits 62 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.demand_hits 666909088 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 666884929 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits 666909088 # number of overall hits
|
system.cpu.dcache.overall_hits 666884929 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses 10448466 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 10445560 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses 5190759 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 5190682 # number of WriteReq misses
|
||||||
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
|
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
|
||||||
system.cpu.dcache.demand_misses 15639225 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 15636242 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses 15639225 # number of overall misses
|
system.cpu.dcache.overall_misses 15636242 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency 184465722500 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 184478558500 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency 128555474171 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 128511717246 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency 313021196671 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 312990275746 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency 313021196671 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 312990275746 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses 509962266 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 509935124 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses 63 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses 63 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses 62 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses 62 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses 682548313 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 682521171 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses 682548313 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 682521171 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.020489 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.020484 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.030076 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.030076 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.047619 # miss rate for LoadLockedReq accesses
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.047619 # miss rate for LoadLockedReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate 0.022913 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.022910 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate 0.022913 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.022910 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 17654.813874 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 17660.954367 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 24766.219000 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 24758.156490 # average WriteReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency 20015.134808 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 20016.975674 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency 20015.134808 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 20016.975674 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 266703683 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 266779202 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 225500 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 90656 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 90534 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2941.930848 # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2946.729428 # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets 16333.333333 # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets 16107.142857 # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks 3128328 # number of writebacks
|
system.cpu.dcache.writebacks 3128454 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 2766203 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits 2763491 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 3298099 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits 3298046 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
|
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits 6064302 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 6061537 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits 6064302 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 6061537 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 7682263 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 7682069 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 1892660 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 1892636 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses 9574923 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 9574705 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses 9574923 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 9574705 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 92044930000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 92052400500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 45262385908 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 45263240996 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 137307315908 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 137315641496 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 137307315908 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 137315641496 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.015064 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.015065 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010966 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010966 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.014028 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.014028 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.014028 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.014028 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11981.486445 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11982.761480 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23914.694614 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23915.449667 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 14340.304972 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 14341.501017 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 14340.304972 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 14341.501017 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.replacements 2927819 # number of replacements
|
system.cpu.l2cache.replacements 2928111 # number of replacements
|
||||||
system.cpu.l2cache.tagsinuse 26780.774124 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 26779.513847 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 7851022 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 7850665 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.sampled_refs 2955142 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 2955434 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 2.656733 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 2.656349 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 102041743500 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 102043879500 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.occ_blocks::0 15984.490640 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 15980.141778 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 10796.283484 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 10799.372069 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.487808 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.487675 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.329476 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.329571 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.ReadReq_hits 5655252 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 5654844 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits 3128328 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 3128454 # number of Writeback hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 980176 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits 980108 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits 6635428 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 6634952 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits 6635428 # number of overall hits
|
system.cpu.l2cache.overall_hits 6634952 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses 2027753 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 2027970 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses 912486 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 912529 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses 2940239 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 2940499 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses 2940239 # number of overall misses
|
system.cpu.l2cache.overall_misses 2940499 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 69614113000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 69622687500 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 31648901500 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 31651212500 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency 101263014500 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 101273900000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency 101263014500 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 101273900000 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses 7683005 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 7682814 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses 3128328 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 3128454 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses 1892662 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 1892637 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses 9575667 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 9575451 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 9575667 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 9575451 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.263927 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.263962 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.482118 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 0.482147 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate 0.307053 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.307087 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate 0.307053 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.307087 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34330.666999 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34331.221616 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34684.259813 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.157951 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34440.402464 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 34441.059154 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34440.402464 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34441.059154 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 56231500 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 56425000 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 6603 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 6634 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8516.053309 # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8505.426590 # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.writebacks 1217598 # number of writebacks
|
system.cpu.l2cache.writebacks 1217630 # number of writebacks
|
||||||
system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
|
system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
|
||||||
system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 2027742 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 2027959 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 912486 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 912529 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses 2940228 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 2940488 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses 2940228 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 2940488 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 63235914500 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 63243262500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28815026500 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28812389000 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 92050941000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 92055651500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 92050941000 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 92055651500 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263926 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263960 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482118 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482147 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.307052 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.307086 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.307052 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.307086 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.384778 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.671160 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31578.595726 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31574.217367 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31307.415955 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31306.249677 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31307.415955 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31306.249677 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=false
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=System
|
type=System
|
||||||
children=cpu membus physmem
|
children=cpu membus physmem
|
||||||
|
boot_osflags=a
|
||||||
|
init_param=0
|
||||||
|
kernel=
|
||||||
|
load_addr_mask=1099511627775
|
||||||
mem_mode=atomic
|
mem_mode=atomic
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
|
readfile=
|
||||||
|
symbolfile=
|
||||||
work_begin_ckpt_count=0
|
work_begin_ckpt_count=0
|
||||||
work_begin_cpu_id_exit=-1
|
work_begin_cpu_id_exit=-1
|
||||||
work_begin_exit_count=0
|
work_begin_exit_count=0
|
||||||
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
type=DerivO3CPU
|
type=DerivO3CPU
|
||||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||||
BTBEntries=4096
|
BTBEntries=4096
|
||||||
BTBTagSize=16
|
BTBTagSize=16
|
||||||
LFSTSize=1024
|
LFSTSize=1024
|
||||||
|
@ -52,6 +59,7 @@ decodeWidth=8
|
||||||
defer_registration=false
|
defer_registration=false
|
||||||
dispatchWidth=8
|
dispatchWidth=8
|
||||||
do_checkpoint_insts=true
|
do_checkpoint_insts=true
|
||||||
|
do_quiesce=true
|
||||||
do_statistics_insts=true
|
do_statistics_insts=true
|
||||||
dtb=system.cpu.dtb
|
dtb=system.cpu.dtb
|
||||||
fetchToDecodeDelay=1
|
fetchToDecodeDelay=1
|
||||||
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
||||||
iewToFetchDelay=1
|
iewToFetchDelay=1
|
||||||
iewToRenameDelay=1
|
iewToRenameDelay=1
|
||||||
instShiftAmt=2
|
instShiftAmt=2
|
||||||
|
interrupts=system.cpu.interrupts
|
||||||
issueToExecuteDelay=1
|
issueToExecuteDelay=1
|
||||||
issueWidth=8
|
issueWidth=8
|
||||||
itb=system.cpu.itb
|
itb=system.cpu.itb
|
||||||
|
@ -80,6 +89,7 @@ max_insts_all_threads=0
|
||||||
max_insts_any_thread=0
|
max_insts_any_thread=0
|
||||||
max_loads_all_threads=0
|
max_loads_all_threads=0
|
||||||
max_loads_any_thread=0
|
max_loads_any_thread=0
|
||||||
|
needsTSO=false
|
||||||
numIQEntries=64
|
numIQEntries=64
|
||||||
numPhysFloatRegs=256
|
numPhysFloatRegs=256
|
||||||
numPhysIntRegs=256
|
numPhysIntRegs=256
|
||||||
|
@ -88,6 +98,7 @@ numRobs=1
|
||||||
numThreads=1
|
numThreads=1
|
||||||
phase=0
|
phase=0
|
||||||
predType=tournament
|
predType=tournament
|
||||||
|
profile=0
|
||||||
progress_interval=0
|
progress_interval=0
|
||||||
renameToDecodeDelay=1
|
renameToDecodeDelay=1
|
||||||
renameToFetchDelay=1
|
renameToFetchDelay=1
|
||||||
|
@ -148,7 +159,16 @@ mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
[system.cpu.dtb]
|
[system.cpu.dtb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.dtb.walker
|
||||||
|
|
||||||
|
[system.cpu.dtb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[3]
|
||||||
|
|
||||||
[system.cpu.fuPool]
|
[system.cpu.fuPool]
|
||||||
type=FUPool
|
type=FUPool
|
||||||
|
@ -445,9 +465,21 @@ write_buffers=8
|
||||||
cpu_side=system.cpu.icache_port
|
cpu_side=system.cpu.icache_port
|
||||||
mem_side=system.cpu.toL2Bus.port[0]
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.interrupts]
|
||||||
|
type=ArmInterrupts
|
||||||
|
|
||||||
[system.cpu.itb]
|
[system.cpu.itb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.itb.walker
|
||||||
|
|
||||||
|
[system.cpu.itb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[2]
|
||||||
|
|
||||||
[system.cpu.l2cache]
|
[system.cpu.l2cache]
|
||||||
type=BaseCache
|
type=BaseCache
|
||||||
|
@ -478,7 +510,7 @@ tgts_per_mshr=5
|
||||||
trace_addr=0
|
trace_addr=0
|
||||||
two_queue=false
|
two_queue=false
|
||||||
write_buffers=8
|
write_buffers=8
|
||||||
cpu_side=system.cpu.toL2Bus.port[2]
|
cpu_side=system.cpu.toL2Bus.port[4]
|
||||||
mem_side=system.membus.port[2]
|
mem_side=system.membus.port[2]
|
||||||
|
|
||||||
[system.cpu.toL2Bus]
|
[system.cpu.toL2Bus]
|
||||||
|
@ -489,7 +521,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
[system.cpu.tracer]
|
[system.cpu.tracer]
|
||||||
type=ExeTracer
|
type=ExeTracer
|
||||||
|
@ -497,12 +529,12 @@ type=ExeTracer
|
||||||
[system.cpu.workload]
|
[system.cpu.workload]
|
||||||
type=LiveProcess
|
type=LiveProcess
|
||||||
cmd=twolf smred
|
cmd=twolf smred
|
||||||
cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
|
cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
|
||||||
egid=100
|
egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
|
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
|
||||||
gid=100
|
gid=100
|
||||||
input=cin
|
input=cin
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
|
|
|
@ -1,12 +1,14 @@
|
||||||
|
Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simout
|
||||||
|
Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 23 2012 04:16:21
|
gem5 compiled Feb 10 2012 00:18:03
|
||||||
gem5 started Jan 23 2012 09:47:07
|
gem5 started Feb 10 2012 00:18:20
|
||||||
gem5 executing on zizzer
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
|
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
|
||||||
Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav
|
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
|
||||||
Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2
|
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
|
||||||
|
@ -23,4 +25,4 @@ info: Increasing stack size by one page.
|
||||||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||||
122 123 124 Exiting @ tick 105874925000 because target called exit()
|
122 123 124 Exiting @ tick 105850842000 because target called exit()
|
||||||
|
|
|
@ -1,23 +1,23 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.105875 # Number of seconds simulated
|
sim_seconds 0.105851 # Number of seconds simulated
|
||||||
sim_ticks 105874925000 # Number of ticks simulated
|
sim_ticks 105850842000 # Number of ticks simulated
|
||||||
final_tick 105874925000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 105850842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 103612 # Simulator instruction rate (inst/s)
|
host_inst_rate 46914 # Simulator instruction rate (inst/s)
|
||||||
host_tick_rate 58144234 # Simulator tick rate (ticks/s)
|
host_tick_rate 26320721 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 224188 # Number of bytes of host memory used
|
host_mem_usage 259812 # Number of bytes of host memory used
|
||||||
host_seconds 1820.90 # Real time elapsed on the host
|
host_seconds 4021.58 # Real time elapsed on the host
|
||||||
sim_insts 188667572 # Number of instructions simulated
|
sim_insts 188667627 # Number of instructions simulated
|
||||||
system.physmem.bytes_read 240192 # Number of bytes read from this memory
|
system.physmem.bytes_read 239936 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read 128512 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read 128320 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
||||||
system.physmem.num_reads 3753 # Number of read requests responded to by this memory
|
system.physmem.num_reads 3749 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes 0 # Number of write requests responded to by this memory
|
system.physmem.num_writes 0 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||||
system.physmem.bw_read 2268639 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read 2266737 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read 1213810 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read 1212272 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total 2268639 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total 2266737 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||||
|
@ -61,105 +61,105 @@ system.cpu.itb.hits 0 # DT
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||||
system.cpu.numCycles 211749851 # number of cpu cycles simulated
|
system.cpu.numCycles 211701685 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.BPredUnit.lookups 102127285 # Number of BP lookups
|
system.cpu.BPredUnit.lookups 102100879 # Number of BP lookups
|
||||||
system.cpu.BPredUnit.condPredicted 80698368 # Number of conditional branches predicted
|
system.cpu.BPredUnit.condPredicted 80677195 # Number of conditional branches predicted
|
||||||
system.cpu.BPredUnit.condIncorrect 9933568 # Number of conditional branches incorrect
|
system.cpu.BPredUnit.condIncorrect 9930193 # Number of conditional branches incorrect
|
||||||
system.cpu.BPredUnit.BTBLookups 84243150 # Number of BTB lookups
|
system.cpu.BPredUnit.BTBLookups 84233443 # Number of BTB lookups
|
||||||
system.cpu.BPredUnit.BTBHits 79257318 # Number of BTB hits
|
system.cpu.BPredUnit.BTBHits 79245701 # Number of BTB hits
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.BPredUnit.usedRAS 4698618 # Number of times the RAS was used to get a target.
|
system.cpu.BPredUnit.usedRAS 4698090 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.BPredUnit.RASInCorrect 111511 # Number of incorrect RAS predictions.
|
system.cpu.BPredUnit.RASInCorrect 111402 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 44551125 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 44542965 # Number of cycles fetch is stalled on an Icache miss
|
||||||
system.cpu.fetch.Insts 416786863 # Number of instructions fetch has processed
|
system.cpu.fetch.Insts 416708415 # Number of instructions fetch has processed
|
||||||
system.cpu.fetch.Branches 102127285 # Number of branches that fetch encountered
|
system.cpu.fetch.Branches 102100879 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 83955936 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 83943791 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.Cycles 108810185 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.fetch.Cycles 108793327 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
system.cpu.fetch.SquashCycles 33218375 # Number of cycles fetch has spent squashing
|
system.cpu.fetch.SquashCycles 33207424 # Number of cycles fetch has spent squashing
|
||||||
system.cpu.fetch.BlockedCycles 35074253 # Number of cycles fetch has spent blocked
|
system.cpu.fetch.BlockedCycles 35058719 # Number of cycles fetch has spent blocked
|
||||||
system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps
|
system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps
|
||||||
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
|
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
|
||||||
system.cpu.fetch.CacheLines 40624886 # Number of cache lines fetched
|
system.cpu.fetch.CacheLines 40619675 # Number of cache lines fetched
|
||||||
system.cpu.fetch.IcacheSquashes 2204416 # Number of outstanding Icache misses that were squashed
|
system.cpu.fetch.IcacheSquashes 2204435 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 211691341 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 211643202 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.135529 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.135620 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 2.646861 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 2.646860 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::0 103083318 48.70% 48.70% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::0 103052143 48.69% 48.69% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::1 4611723 2.18% 50.87% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::1 4614041 2.18% 50.87% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::2 32955553 15.57% 66.44% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::2 32953123 15.57% 66.44% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::3 18242297 8.62% 75.06% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::3 18235328 8.62% 75.06% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::4 9176940 4.34% 79.39% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::4 9171108 4.33% 79.39% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::5 12529739 5.92% 85.31% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::5 12530200 5.92% 85.31% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::6 8472403 4.00% 89.31% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::6 8476968 4.01% 89.32% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::7 4322449 2.04% 91.36% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::7 4316297 2.04% 91.36% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::8 18296919 8.64% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::8 18293994 8.64% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 211691341 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 211643202 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.branchRate 0.482302 # Number of branch fetches per cycle
|
system.cpu.fetch.branchRate 0.482287 # Number of branch fetches per cycle
|
||||||
system.cpu.fetch.rate 1.968298 # Number of inst fetches per cycle
|
system.cpu.fetch.rate 1.968376 # Number of inst fetches per cycle
|
||||||
system.cpu.decode.IdleCycles 53244805 # Number of cycles decode is idle
|
system.cpu.decode.IdleCycles 53231519 # Number of cycles decode is idle
|
||||||
system.cpu.decode.BlockedCycles 33622636 # Number of cycles decode is blocked
|
system.cpu.decode.BlockedCycles 33609414 # Number of cycles decode is blocked
|
||||||
system.cpu.decode.RunCycles 100506105 # Number of cycles decode is running
|
system.cpu.decode.RunCycles 100494512 # Number of cycles decode is running
|
||||||
system.cpu.decode.UnblockCycles 1219607 # Number of cycles decode is unblocking
|
system.cpu.decode.UnblockCycles 1217161 # Number of cycles decode is unblocking
|
||||||
system.cpu.decode.SquashCycles 23098188 # Number of cycles decode is squashing
|
system.cpu.decode.SquashCycles 23090596 # Number of cycles decode is squashing
|
||||||
system.cpu.decode.BranchResolved 14186059 # Number of times decode resolved a branch
|
system.cpu.decode.BranchResolved 14181130 # Number of times decode resolved a branch
|
||||||
system.cpu.decode.BranchMispred 166456 # Number of times decode detected a branch misprediction
|
system.cpu.decode.BranchMispred 166488 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.decode.DecodedInsts 422686981 # Number of instructions handled by decode
|
system.cpu.decode.DecodedInsts 422617374 # Number of instructions handled by decode
|
||||||
system.cpu.decode.SquashedInsts 695509 # Number of squashed instructions handled by decode
|
system.cpu.decode.SquashedInsts 695976 # Number of squashed instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 23098188 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 23090596 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 62205667 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 62189594 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 461892 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 455687 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 28663713 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 28663702 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 92688664 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 92677243 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 4573217 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 4566380 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 388586256 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 388527700 # Number of instructions processed by rename
|
||||||
system.cpu.rename.IQFullEvents 22473 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 20997 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LSQFullEvents 2248529 # Number of times rename has blocked due to LSQ full
|
system.cpu.rename.LSQFullEvents 2241803 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.rename.RenamedOperands 666261253 # Number of destination operands rename has renamed
|
system.cpu.rename.RenamedOperands 666137382 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenameLookups 1656600047 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenameLookups 1656361753 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.int_rename_lookups 1638859233 # Number of integer rename lookups
|
system.cpu.rename.int_rename_lookups 1638646831 # Number of integer rename lookups
|
||||||
system.cpu.rename.fp_rename_lookups 17740814 # Number of floating rename lookups
|
system.cpu.rename.fp_rename_lookups 17714922 # Number of floating rename lookups
|
||||||
system.cpu.rename.CommittedMaps 298061848 # Number of HB maps that are committed
|
system.cpu.rename.CommittedMaps 298061936 # Number of HB maps that are committed
|
||||||
system.cpu.rename.UndoneMaps 368199405 # Number of HB maps that are undone due to squashing
|
system.cpu.rename.UndoneMaps 368075446 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.rename.serializingInsts 2723713 # count of serializing insts renamed
|
system.cpu.rename.serializingInsts 2723266 # count of serializing insts renamed
|
||||||
system.cpu.rename.tempSerializingInsts 2675909 # count of temporary serializing insts renamed
|
system.cpu.rename.tempSerializingInsts 2675408 # count of temporary serializing insts renamed
|
||||||
system.cpu.rename.skidInsts 23519864 # count of insts added to the skid buffer
|
system.cpu.rename.skidInsts 23504222 # count of insts added to the skid buffer
|
||||||
system.cpu.memDep0.insertedLoads 46897665 # Number of loads inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedLoads 46900559 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.insertedStores 16902365 # Number of stores inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedStores 16903337 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.conflictingLoads 3883401 # Number of conflicting loads.
|
system.cpu.memDep0.conflictingLoads 3858030 # Number of conflicting loads.
|
||||||
system.cpu.memDep0.conflictingStores 2525721 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 2525525 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 332696460 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 332647611 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 2225712 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 2225423 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 261853052 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 261830951 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 956132 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 960204 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 143515224 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 143464205 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 342118821 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 342029155 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 589705 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.iqSquashedNonSpecRemoved 589405 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.iq.issued_per_cycle::samples 211691341 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::samples 211643202 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.236957 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 1.237134 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.489139 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.489338 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 97854722 46.23% 46.23% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 97826086 46.22% 46.22% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 37874169 17.89% 64.12% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 37864076 17.89% 64.11% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 34110087 16.11% 80.23% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 34104807 16.11% 80.23% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 22786114 10.76% 90.99% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 22781361 10.76% 90.99% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 11453676 5.41% 96.40% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 11447248 5.41% 96.40% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::5 4761165 2.25% 98.65% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::5 4765675 2.25% 98.65% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::6 2318956 1.10% 99.75% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::6 2321089 1.10% 99.75% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::7 393514 0.19% 99.93% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::7 393603 0.19% 99.93% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::8 138938 0.07% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::8 139257 0.07% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::total 211691341 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::total 211643202 # Number of insts issued each cycle
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntAlu 398184 18.25% 18.25% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntAlu 397917 18.24% 18.24% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntMult 5522 0.25% 18.50% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntMult 5522 0.25% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 18.50% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.50% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.50% # attempts to use FU when none available
|
||||||
|
@ -179,22 +179,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.50% # at
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 18.50% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.50% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.50% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 54 0.00% 18.51% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAdd 50 0.00% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.51% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.51% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.51% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.51% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 18.51% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMisc 46 0.00% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.51% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.51% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.51% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.50% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemRead 1324595 60.71% 79.22% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemRead 1324685 60.73% 79.23% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemWrite 453293 20.78% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemWrite 453082 20.77% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 204944335 78.27% 78.27% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 204918446 78.26% 78.26% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 928862 0.35% 78.62% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 928788 0.35% 78.62% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued
|
||||||
|
@ -213,147 +213,147 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.62% # Ty
|
||||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAdd 33072 0.01% 78.63% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAdd 33078 0.01% 78.63% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.63% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.63% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCmp 166569 0.06% 78.70% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCmp 166576 0.06% 78.69% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCvt 257495 0.10% 78.80% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCvt 257183 0.10% 78.79% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatDiv 76397 0.03% 78.83% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatDiv 76398 0.03% 78.82% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMisc 468208 0.18% 79.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMisc 467924 0.18% 79.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 207568 0.08% 79.08% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 207596 0.08% 79.08% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71821 0.03% 79.11% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71825 0.03% 79.11% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 79.11% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 79.11% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 40739224 15.56% 94.67% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 40744644 15.56% 94.67% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 13959176 5.33% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 13958168 5.33% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 261853052 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 261830951 # Type of FU issued
|
||||||
system.cpu.iq.rate 1.236615 # Inst issue rate
|
system.cpu.iq.rate 1.236792 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 2181696 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 2181302 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.008332 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.008331 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 734785745 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 734699293 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 476212492 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 476117347 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 242882419 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 242859396 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 3749528 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 3747317 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 2237188 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 2232204 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 1845400 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 1844998 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 262148601 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 262127165 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 1886147 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 1885088 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 1588917 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 1590290 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 17045968 # Number of loads squashed
|
system.cpu.iew.lsq.thread0.squashedLoads 17048851 # Number of loads squashed
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 31330 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iew.lsq.thread0.ignoredResponses 31549 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 12732 # Number of memory ordering violations
|
system.cpu.iew.lsq.thread0.memOrderViolation 12762 # Number of memory ordering violations
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 4255519 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 4256480 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 19 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 23098188 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 23090596 # Number of cycles IEW is squashing
|
||||||
system.cpu.iew.iewBlockCycles 13857 # Number of cycles IEW is blocking
|
system.cpu.iew.iewBlockCycles 13781 # Number of cycles IEW is blocking
|
||||||
system.cpu.iew.iewUnblockCycles 833 # Number of cycles IEW is unblocking
|
system.cpu.iew.iewUnblockCycles 840 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iew.iewDispatchedInsts 334975630 # Number of instructions dispatched to IQ
|
system.cpu.iew.iewDispatchedInsts 334926486 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iew.iewDispSquashedInsts 3751995 # Number of squashed instructions skipped by dispatch
|
system.cpu.iew.iewDispSquashedInsts 3752435 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iew.iewDispLoadInsts 46897665 # Number of dispatched load instructions
|
system.cpu.iew.iewDispLoadInsts 46900559 # Number of dispatched load instructions
|
||||||
system.cpu.iew.iewDispStoreInsts 16902365 # Number of dispatched store instructions
|
system.cpu.iew.iewDispStoreInsts 16903337 # Number of dispatched store instructions
|
||||||
system.cpu.iew.iewDispNonSpecInsts 2201836 # Number of dispatched non-speculative instructions
|
system.cpu.iew.iewDispNonSpecInsts 2201532 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.iew.iewIQFullEvents 328 # Number of times the IQ has become full, causing a stall
|
system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.iew.memOrderViolationEvents 12732 # Number of memory order violations
|
system.cpu.iew.memOrderViolationEvents 12762 # Number of memory order violations
|
||||||
system.cpu.iew.predictedTakenIncorrect 9997150 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 9994816 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 1695546 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 1695108 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 11692696 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 11689924 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 249230612 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 249206258 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 38607191 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 38606621 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 12622440 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 12624693 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 53458 # number of nop insts executed
|
system.cpu.iew.exec_nop 53452 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 52205543 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 52203623 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 52589382 # Number of branches executed
|
system.cpu.iew.exec_branches 52584405 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 13598352 # Number of stores executed
|
system.cpu.iew.exec_stores 13597002 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 1.177005 # Inst execution rate
|
system.cpu.iew.exec_rate 1.177158 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 246260336 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 246234772 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 244727819 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 244704394 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 148531018 # num instructions producing a value
|
system.cpu.iew.wb_producers 148512928 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 247826872 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 247801271 # num instructions consuming a value
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.iew.wb_rate 1.155740 # insts written-back per cycle
|
system.cpu.iew.wb_rate 1.155893 # insts written-back per cycle
|
||||||
system.cpu.iew.wb_fanout 0.599334 # average fanout of values written-back
|
system.cpu.iew.wb_fanout 0.599323 # average fanout of values written-back
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.commit.commitCommittedInsts 188681960 # The number of committed instructions
|
system.cpu.commit.commitCommittedInsts 188682015 # The number of committed instructions
|
||||||
system.cpu.commit.commitSquashedInsts 146293697 # The number of squashed insts skipped by commit
|
system.cpu.commit.commitSquashedInsts 146244510 # The number of squashed insts skipped by commit
|
||||||
system.cpu.commit.commitNonSpecStalls 1636007 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu.commit.commitNonSpecStalls 1636018 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.commit.branchMispredicts 9795278 # The number of times a branch was mispredicted
|
system.cpu.commit.branchMispredicts 9791900 # The number of times a branch was mispredicted
|
||||||
system.cpu.commit.committed_per_cycle::samples 188593154 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::samples 188552607 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.000471 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::mean 1.000686 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::stdev 1.681076 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::stdev 1.681539 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::0 105401505 55.89% 55.89% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::0 105375521 55.89% 55.89% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::1 40855723 21.66% 77.55% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::1 40844225 21.66% 77.55% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::2 19482895 10.33% 87.88% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::2 19484606 10.33% 87.88% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::3 8763575 4.65% 92.53% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::3 8759294 4.65% 92.53% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::4 4920568 2.61% 95.14% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::4 4914501 2.61% 95.13% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::5 2013461 1.07% 96.21% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::5 2011973 1.07% 96.20% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::6 1707502 0.91% 97.11% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::6 1708688 0.91% 97.11% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::7 1008267 0.53% 97.65% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::7 1009693 0.54% 97.64% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::8 4439658 2.35% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::8 4444106 2.36% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::total 188593154 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::total 188552607 # Number of insts commited each cycle
|
||||||
system.cpu.commit.count 188681960 # Number of instructions committed
|
system.cpu.commit.count 188682015 # Number of instructions committed
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.commit.refs 42498543 # Number of memory references committed
|
system.cpu.commit.refs 42498565 # Number of memory references committed
|
||||||
system.cpu.commit.loads 29851697 # Number of loads committed
|
system.cpu.commit.loads 29851708 # Number of loads committed
|
||||||
system.cpu.commit.membars 22408 # Number of memory barriers committed
|
system.cpu.commit.membars 22408 # Number of memory barriers committed
|
||||||
system.cpu.commit.branches 40283895 # Number of branches committed
|
system.cpu.commit.branches 40283906 # Number of branches committed
|
||||||
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
|
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
|
||||||
system.cpu.commit.int_insts 150115073 # Number of committed integer instructions.
|
system.cpu.commit.int_insts 150115117 # Number of committed integer instructions.
|
||||||
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
|
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
|
||||||
system.cpu.commit.bw_lim_events 4439658 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 4444106 # number cycles where commit BW limit reached
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.rob.rob_reads 519123952 # The number of ROB reads
|
system.cpu.rob.rob_reads 519029825 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 693113124 # The number of ROB writes
|
system.cpu.rob.rob_writes 693007050 # The number of ROB writes
|
||||||
system.cpu.timesIdled 1721 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 58510 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 58483 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu.committedInsts 188667572 # Number of Instructions Simulated
|
system.cpu.committedInsts 188667627 # Number of Instructions Simulated
|
||||||
system.cpu.committedInsts_total 188667572 # Number of Instructions Simulated
|
system.cpu.committedInsts_total 188667627 # Number of Instructions Simulated
|
||||||
system.cpu.cpi 1.122344 # CPI: Cycles Per Instruction
|
system.cpu.cpi 1.122088 # CPI: Cycles Per Instruction
|
||||||
system.cpu.cpi_total 1.122344 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 1.122088 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 0.890993 # IPC: Instructions Per Cycle
|
system.cpu.ipc 0.891196 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 0.890993 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 0.891196 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 1112090730 # number of integer regfile reads
|
system.cpu.int_regfile_reads 1111988877 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 407417013 # number of integer regfile writes
|
system.cpu.int_regfile_writes 407368356 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 2928432 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 2928539 # number of floating regfile reads
|
||||||
system.cpu.fp_regfile_writes 2499453 # number of floating regfile writes
|
system.cpu.fp_regfile_writes 2498508 # number of floating regfile writes
|
||||||
system.cpu.misc_regfile_reads 503028333 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 502946356 # number of misc regfile reads
|
||||||
system.cpu.misc_regfile_writes 824460 # number of misc regfile writes
|
system.cpu.misc_regfile_writes 824482 # number of misc regfile writes
|
||||||
system.cpu.icache.replacements 1929 # number of replacements
|
system.cpu.icache.replacements 1934 # number of replacements
|
||||||
system.cpu.icache.tagsinuse 1329.893683 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 1329.301324 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 40620654 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 40615441 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.sampled_refs 3638 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 3640 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.avg_refs 11165.655305 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 11158.088187 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.occ_blocks::0 1329.893683 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 1329.301324 # Average occupied blocks per context
|
||||||
system.cpu.icache.occ_percent::0 0.649362 # Average percentage of cache occupancy
|
system.cpu.icache.occ_percent::0 0.649073 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.ReadReq_hits 40620654 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 40615441 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits 40620654 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 40615441 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits 40620654 # number of overall hits
|
system.cpu.icache.overall_hits 40615441 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses 4232 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 4234 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses 4232 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 4234 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses 4232 # number of overall misses
|
system.cpu.icache.overall_misses 4234 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 101343500 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 101275500 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency 101343500 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 101275500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency 101343500 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 101275500 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses 40624886 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 40619675 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses 40624886 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 40619675 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses 40624886 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 40619675 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000104 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000104 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate 0.000104 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000104 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate 0.000104 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000104 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 23946.951796 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 23919.579594 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency 23946.951796 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 23919.579594 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency 23946.951796 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 23919.579594 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -366,64 +366,64 @@ system.cpu.icache.writebacks 0 # nu
|
||||||
system.cpu.icache.ReadReq_mshr_hits 594 # number of ReadReq MSHR hits
|
system.cpu.icache.ReadReq_mshr_hits 594 # number of ReadReq MSHR hits
|
||||||
system.cpu.icache.demand_mshr_hits 594 # number of demand (read+write) MSHR hits
|
system.cpu.icache.demand_mshr_hits 594 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.icache.overall_mshr_hits 594 # number of overall MSHR hits
|
system.cpu.icache.overall_mshr_hits 594 # number of overall MSHR hits
|
||||||
system.cpu.icache.ReadReq_mshr_misses 3638 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 3640 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.demand_mshr_misses 3638 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses 3640 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses 3638 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses 3640 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 74666000 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency 74572500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency 74666000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency 74572500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency 74666000 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency 74572500 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000090 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000090 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000090 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate 0.000090 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000090 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate 0.000090 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 20523.914239 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 20486.950549 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 20523.914239 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 20486.950549 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 20523.914239 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 20486.950549 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.replacements 55 # number of replacements
|
system.cpu.dcache.replacements 53 # number of replacements
|
||||||
system.cpu.dcache.tagsinuse 1403.749083 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 1403.723956 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 48644661 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 48643693 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.sampled_refs 1849 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 1846 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.avg_refs 26308.632234 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 26350.862947 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.occ_blocks::0 1403.749083 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 1403.723956 # Average occupied blocks per context
|
||||||
system.cpu.dcache.occ_percent::0 0.342712 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_percent::0 0.342706 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.ReadReq_hits 36235521 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 36234545 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits 12356728 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 12356727 # number of WriteReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits 27793 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits 27791 # number of LoadLockedReq hits
|
||||||
system.cpu.dcache.StoreCondReq_hits 24619 # number of StoreCondReq hits
|
system.cpu.dcache.StoreCondReq_hits 24630 # number of StoreCondReq hits
|
||||||
system.cpu.dcache.demand_hits 48592249 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 48591272 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits 48592249 # number of overall hits
|
system.cpu.dcache.overall_hits 48591272 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses 1802 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 1808 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses 7559 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 7560 # number of WriteReq misses
|
||||||
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
|
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
|
||||||
system.cpu.dcache.demand_misses 9361 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 9368 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses 9361 # number of overall misses
|
system.cpu.dcache.overall_misses 9368 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency 59198500 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 59529000 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency 237194000 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 237156500 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency 296392500 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 296685500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency 296392500 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 296685500 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses 36237323 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 36236353 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.LoadLockedReq_accesses 27795 # number of LoadLockedReq accesses(hits+misses)
|
system.cpu.dcache.LoadLockedReq_accesses 27793 # number of LoadLockedReq accesses(hits+misses)
|
||||||
system.cpu.dcache.StoreCondReq_accesses 24619 # number of StoreCondReq accesses(hits+misses)
|
system.cpu.dcache.StoreCondReq_accesses 24630 # number of StoreCondReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses 48601610 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 48600640 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses 48601610 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 48600640 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.000050 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.000050 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate 0.000193 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.000193 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate 0.000193 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.000193 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 32851.553829 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 32925.331858 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 31379.018389 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 31369.907407 # average WriteReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency 31662.482641 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 31670.100342 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency 31662.482641 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 31670.100342 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -432,70 +432,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks 19 # number of writebacks
|
system.cpu.dcache.writebacks 18 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 1044 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits 1053 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 6468 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits 6469 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
|
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits 7512 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 7522 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits 7512 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 7522 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 758 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 755 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 1091 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 1091 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses 1849 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 1846 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses 1849 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 1846 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 24153000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 24116500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 38344000 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 38344000 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 62497000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 62460500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 62497000 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 62460500 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.000038 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.000038 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.000038 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.000038 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31864.116095 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31942.384106 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35145.737855 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35145.737855 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 33800.432666 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 33835.590466 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 33800.432666 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 33835.590466 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.replacements 0 # number of replacements
|
system.cpu.l2cache.replacements 0 # number of replacements
|
||||||
system.cpu.l2cache.tagsinuse 1924.111202 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 1923.480613 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 1711 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 1714 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.sampled_refs 2681 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 2676 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 0.638195 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 0.640508 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.occ_blocks::0 1920.073953 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 1919.476269 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 4.037248 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 4.004344 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.058596 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.058578 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.000123 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.000122 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.ReadReq_hits 1711 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 1714 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits 19 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 18 # number of Writeback hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits 1720 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 1723 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits 1720 # number of overall hits
|
system.cpu.l2cache.overall_hits 1723 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses 2685 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 2681 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses 1082 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 1082 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses 3767 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 3763 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses 3767 # number of overall misses
|
system.cpu.l2cache.overall_misses 3763 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 92055500 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 91922000 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 37184500 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 37184000 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency 129240000 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 129106000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency 129240000 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 129106000 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses 4396 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 4395 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses 19 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 18 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses 1091 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 1091 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses 5487 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 5486 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 5487 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 5486 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.610783 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.610011 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.991751 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 0.991751 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate 0.686532 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.685928 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate 0.686532 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.685928 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34285.102421 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34286.460276 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.451017 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34365.988909 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34308.468277 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 34309.327664 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34308.468277 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34309.327664 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -508,24 +508,24 @@ system.cpu.l2cache.writebacks 0 # nu
|
||||||
system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits
|
system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits
|
||||||
system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 2671 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 2667 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 1082 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 1082 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses 3753 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 3749 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses 3753 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 3749 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 83018000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 82895000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 33590000 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 33590000 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 116608000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 116485000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 116608000 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 116485000 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.607598 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.606826 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991751 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991751 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.683980 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.683376 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.683980 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.683376 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.242980 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.739783 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31044.362292 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31044.362292 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.610179 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.952254 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.610179 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.952254 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=false
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=System
|
type=System
|
||||||
children=cpu membus physmem
|
children=cpu membus physmem
|
||||||
|
boot_osflags=a
|
||||||
|
init_param=0
|
||||||
|
kernel=
|
||||||
|
load_addr_mask=1099511627775
|
||||||
mem_mode=atomic
|
mem_mode=atomic
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
|
readfile=
|
||||||
|
symbolfile=
|
||||||
work_begin_ckpt_count=0
|
work_begin_ckpt_count=0
|
||||||
work_begin_cpu_id_exit=-1
|
work_begin_cpu_id_exit=-1
|
||||||
work_begin_exit_count=0
|
work_begin_exit_count=0
|
||||||
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
type=DerivO3CPU
|
type=DerivO3CPU
|
||||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||||
BTBEntries=4096
|
BTBEntries=4096
|
||||||
BTBTagSize=16
|
BTBTagSize=16
|
||||||
LFSTSize=1024
|
LFSTSize=1024
|
||||||
|
@ -52,6 +59,7 @@ decodeWidth=8
|
||||||
defer_registration=false
|
defer_registration=false
|
||||||
dispatchWidth=8
|
dispatchWidth=8
|
||||||
do_checkpoint_insts=true
|
do_checkpoint_insts=true
|
||||||
|
do_quiesce=true
|
||||||
do_statistics_insts=true
|
do_statistics_insts=true
|
||||||
dtb=system.cpu.dtb
|
dtb=system.cpu.dtb
|
||||||
fetchToDecodeDelay=1
|
fetchToDecodeDelay=1
|
||||||
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
||||||
iewToFetchDelay=1
|
iewToFetchDelay=1
|
||||||
iewToRenameDelay=1
|
iewToRenameDelay=1
|
||||||
instShiftAmt=2
|
instShiftAmt=2
|
||||||
|
interrupts=system.cpu.interrupts
|
||||||
issueToExecuteDelay=1
|
issueToExecuteDelay=1
|
||||||
issueWidth=8
|
issueWidth=8
|
||||||
itb=system.cpu.itb
|
itb=system.cpu.itb
|
||||||
|
@ -89,6 +98,7 @@ numRobs=1
|
||||||
numThreads=1
|
numThreads=1
|
||||||
phase=0
|
phase=0
|
||||||
predType=tournament
|
predType=tournament
|
||||||
|
profile=0
|
||||||
progress_interval=0
|
progress_interval=0
|
||||||
renameToDecodeDelay=1
|
renameToDecodeDelay=1
|
||||||
renameToFetchDelay=1
|
renameToFetchDelay=1
|
||||||
|
@ -149,7 +159,14 @@ mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
[system.cpu.dtb]
|
[system.cpu.dtb]
|
||||||
type=X86TLB
|
type=X86TLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.dtb.walker
|
||||||
|
|
||||||
|
[system.cpu.dtb.walker]
|
||||||
|
type=X86PagetableWalker
|
||||||
|
system=system
|
||||||
|
port=system.cpu.toL2Bus.port[3]
|
||||||
|
|
||||||
[system.cpu.fuPool]
|
[system.cpu.fuPool]
|
||||||
type=FUPool
|
type=FUPool
|
||||||
|
@ -446,9 +463,25 @@ write_buffers=8
|
||||||
cpu_side=system.cpu.icache_port
|
cpu_side=system.cpu.icache_port
|
||||||
mem_side=system.cpu.toL2Bus.port[0]
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.interrupts]
|
||||||
|
type=X86LocalApic
|
||||||
|
int_latency=1000
|
||||||
|
pio_addr=2305843009213693952
|
||||||
|
pio_latency=1000
|
||||||
|
system=system
|
||||||
|
int_port=system.membus.port[4]
|
||||||
|
pio=system.membus.port[3]
|
||||||
|
|
||||||
[system.cpu.itb]
|
[system.cpu.itb]
|
||||||
type=X86TLB
|
type=X86TLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.itb.walker
|
||||||
|
|
||||||
|
[system.cpu.itb.walker]
|
||||||
|
type=X86PagetableWalker
|
||||||
|
system=system
|
||||||
|
port=system.cpu.toL2Bus.port[2]
|
||||||
|
|
||||||
[system.cpu.l2cache]
|
[system.cpu.l2cache]
|
||||||
type=BaseCache
|
type=BaseCache
|
||||||
|
@ -479,7 +512,7 @@ tgts_per_mshr=5
|
||||||
trace_addr=0
|
trace_addr=0
|
||||||
two_queue=false
|
two_queue=false
|
||||||
write_buffers=8
|
write_buffers=8
|
||||||
cpu_side=system.cpu.toL2Bus.port[2]
|
cpu_side=system.cpu.toL2Bus.port[4]
|
||||||
mem_side=system.membus.port[2]
|
mem_side=system.membus.port[2]
|
||||||
|
|
||||||
[system.cpu.toL2Bus]
|
[system.cpu.toL2Bus]
|
||||||
|
@ -490,7 +523,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
[system.cpu.tracer]
|
[system.cpu.tracer]
|
||||||
type=ExeTracer
|
type=ExeTracer
|
||||||
|
@ -498,7 +531,7 @@ type=ExeTracer
|
||||||
[system.cpu.workload]
|
[system.cpu.workload]
|
||||||
type=LiveProcess
|
type=LiveProcess
|
||||||
cmd=twolf smred
|
cmd=twolf smred
|
||||||
cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
|
cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
|
||||||
egid=100
|
egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
|
@ -522,7 +555,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||||
|
|
||||||
[system.physmem]
|
[system.physmem]
|
||||||
type=PhysicalMemory
|
type=PhysicalMemory
|
||||||
|
|
|
@ -1,14 +1,14 @@
|
||||||
Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/simout
|
Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
|
||||||
Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/simerr
|
Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 28 2012 12:11:40
|
gem5 compiled Feb 9 2012 12:45:55
|
||||||
gem5 started Jan 28 2012 12:12:43
|
gem5 started Feb 9 2012 12:46:40
|
||||||
gem5 executing on ribera.cs.wisc.edu
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
|
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
|
||||||
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav
|
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
|
||||||
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2
|
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
|
||||||
|
@ -26,4 +26,4 @@ info: Increasing stack size by one page.
|
||||||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||||
122 123 124 Exiting @ tick 96605044000 because target called exit()
|
122 123 124 Exiting @ tick 96266258000 because target called exit()
|
||||||
|
|
|
@ -1,261 +1,261 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.096605 # Number of seconds simulated
|
sim_seconds 0.096266 # Number of seconds simulated
|
||||||
sim_ticks 96605044000 # Number of ticks simulated
|
sim_ticks 96266258000 # Number of ticks simulated
|
||||||
final_tick 96605044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 96266258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 67425 # Simulator instruction rate (inst/s)
|
host_inst_rate 60515 # Simulator instruction rate (inst/s)
|
||||||
host_tick_rate 29425038 # Simulator tick rate (ticks/s)
|
host_tick_rate 26316743 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 253272 # Number of bytes of host memory used
|
host_mem_usage 262352 # Number of bytes of host memory used
|
||||||
host_seconds 3283.09 # Real time elapsed on the host
|
host_seconds 3657.99 # Real time elapsed on the host
|
||||||
sim_insts 221363017 # Number of instructions simulated
|
sim_insts 221363017 # Number of instructions simulated
|
||||||
system.physmem.bytes_read 339456 # Number of bytes read from this memory
|
system.physmem.bytes_read 339712 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read 214848 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read 214912 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
||||||
system.physmem.num_reads 5304 # Number of read requests responded to by this memory
|
system.physmem.num_reads 5308 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes 0 # Number of write requests responded to by this memory
|
system.physmem.num_writes 0 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||||
system.physmem.bw_read 3513854 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read 3528879 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read 2223983 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read 2232475 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total 3513854 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total 3528879 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||||
system.cpu.numCycles 193210089 # number of cpu cycles simulated
|
system.cpu.numCycles 192532517 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.BPredUnit.lookups 25792325 # Number of BP lookups
|
system.cpu.BPredUnit.lookups 25728486 # Number of BP lookups
|
||||||
system.cpu.BPredUnit.condPredicted 25792325 # Number of conditional branches predicted
|
system.cpu.BPredUnit.condPredicted 25728486 # Number of conditional branches predicted
|
||||||
system.cpu.BPredUnit.condIncorrect 2895497 # Number of conditional branches incorrect
|
system.cpu.BPredUnit.condIncorrect 2892788 # Number of conditional branches incorrect
|
||||||
system.cpu.BPredUnit.BTBLookups 23600664 # Number of BTB lookups
|
system.cpu.BPredUnit.BTBLookups 23533152 # Number of BTB lookups
|
||||||
system.cpu.BPredUnit.BTBHits 20878395 # Number of BTB hits
|
system.cpu.BPredUnit.BTBHits 20839978 # Number of BTB hits
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 30964428 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 30657479 # Number of cycles fetch is stalled on an Icache miss
|
||||||
system.cpu.fetch.Insts 261331282 # Number of instructions fetch has processed
|
system.cpu.fetch.Insts 260466955 # Number of instructions fetch has processed
|
||||||
system.cpu.fetch.Branches 25792325 # Number of branches that fetch encountered
|
system.cpu.fetch.Branches 25728486 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 20878395 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 20839978 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.Cycles 70767464 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.fetch.Cycles 70644215 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
system.cpu.fetch.SquashCycles 26891019 # Number of cycles fetch has spent squashing
|
system.cpu.fetch.SquashCycles 26785814 # Number of cycles fetch has spent squashing
|
||||||
system.cpu.fetch.BlockedCycles 67713706 # Number of cycles fetch has spent blocked
|
system.cpu.fetch.BlockedCycles 67566342 # Number of cycles fetch has spent blocked
|
||||||
system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.fetch.MiscStallCycles 136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
system.cpu.fetch.PendingTrapStallCycles 1189 # Number of stall cycles due to pending traps
|
system.cpu.fetch.PendingTrapStallCycles 1120 # Number of stall cycles due to pending traps
|
||||||
system.cpu.fetch.CacheLines 28829274 # Number of cache lines fetched
|
system.cpu.fetch.CacheLines 28758661 # Number of cache lines fetched
|
||||||
system.cpu.fetch.IcacheSquashes 550737 # Number of outstanding Icache misses that were squashed
|
system.cpu.fetch.IcacheSquashes 555177 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 193129824 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 192452166 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.258996 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.262310 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 3.335178 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 3.335029 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::0 124221202 64.32% 64.32% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::0 123644733 64.25% 64.25% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::1 4112630 2.13% 66.45% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::1 4091160 2.13% 66.37% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::2 3244602 1.68% 68.13% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::2 3200074 1.66% 68.04% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::3 4465272 2.31% 70.44% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::3 4567374 2.37% 70.41% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::4 4293373 2.22% 72.66% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::4 4265123 2.22% 72.63% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::5 4464358 2.31% 74.98% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::5 4442159 2.31% 74.93% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::6 5413333 2.80% 77.78% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::6 5459285 2.84% 77.77% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::7 3013911 1.56% 79.34% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::7 3091960 1.61% 79.38% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::8 39901143 20.66% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::8 39690298 20.62% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 193129824 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 192452166 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.branchRate 0.133494 # Number of branch fetches per cycle
|
system.cpu.fetch.branchRate 0.133632 # Number of branch fetches per cycle
|
||||||
system.cpu.fetch.rate 1.352576 # Number of inst fetches per cycle
|
system.cpu.fetch.rate 1.352847 # Number of inst fetches per cycle
|
||||||
system.cpu.decode.IdleCycles 44734521 # Number of cycles decode is idle
|
system.cpu.decode.IdleCycles 44411978 # Number of cycles decode is idle
|
||||||
system.cpu.decode.BlockedCycles 57786241 # Number of cycles decode is blocked
|
system.cpu.decode.BlockedCycles 57625858 # Number of cycles decode is blocked
|
||||||
system.cpu.decode.RunCycles 57127863 # Number of cycles decode is running
|
system.cpu.decode.RunCycles 56973408 # Number of cycles decode is running
|
||||||
system.cpu.decode.UnblockCycles 9798304 # Number of cycles decode is unblocking
|
system.cpu.decode.UnblockCycles 9858048 # Number of cycles decode is unblocking
|
||||||
system.cpu.decode.SquashCycles 23682895 # Number of cycles decode is squashing
|
system.cpu.decode.SquashCycles 23582874 # Number of cycles decode is squashing
|
||||||
system.cpu.decode.DecodedInsts 423946385 # Number of instructions handled by decode
|
system.cpu.decode.DecodedInsts 423042956 # Number of instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 23682895 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 23582874 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 53367953 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 52998252 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 14712731 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 14705836 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 23142 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 23082 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 57547510 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 57546904 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 43795593 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 43595218 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 411406798 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 410638323 # Number of instructions processed by rename
|
||||||
system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
|
system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.rename.IQFullEvents 18855699 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 18885984 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LSQFullEvents 22517657 # Number of times rename has blocked due to LSQ full
|
system.cpu.rename.LSQFullEvents 22330558 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.rename.RenamedOperands 437782007 # Number of destination operands rename has renamed
|
system.cpu.rename.RenamedOperands 437009036 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenameLookups 1065797846 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenameLookups 1063910767 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.int_rename_lookups 1054993887 # Number of integer rename lookups
|
system.cpu.rename.int_rename_lookups 1053088723 # Number of integer rename lookups
|
||||||
system.cpu.rename.fp_rename_lookups 10803959 # Number of floating rename lookups
|
system.cpu.rename.fp_rename_lookups 10822044 # Number of floating rename lookups
|
||||||
system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed
|
system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed
|
||||||
system.cpu.rename.UndoneMaps 203418598 # Number of HB maps that are undone due to squashing
|
system.cpu.rename.UndoneMaps 202645627 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.rename.serializingInsts 1777 # count of serializing insts renamed
|
system.cpu.rename.serializingInsts 1783 # count of serializing insts renamed
|
||||||
system.cpu.rename.tempSerializingInsts 1771 # count of temporary serializing insts renamed
|
system.cpu.rename.tempSerializingInsts 1777 # count of temporary serializing insts renamed
|
||||||
system.cpu.rename.skidInsts 94869536 # count of insts added to the skid buffer
|
system.cpu.rename.skidInsts 94569707 # count of insts added to the skid buffer
|
||||||
system.cpu.memDep0.insertedLoads 104184220 # Number of loads inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedLoads 103994638 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.insertedStores 37252864 # Number of stores inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedStores 37171273 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.conflictingLoads 66898151 # Number of conflicting loads.
|
system.cpu.memDep0.conflictingLoads 66711674 # Number of conflicting loads.
|
||||||
system.cpu.memDep0.conflictingStores 21504625 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 21456392 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 396406110 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 395555693 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 2683 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 2683 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 287681996 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 287296212 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 245770 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 238230 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 174447554 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 173600960 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 349871098 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 348497721 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 1437 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.iqSquashedNonSpecRemoved 1437 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.iq.issued_per_cycle::samples 193129824 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::samples 192452166 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.489578 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 1.492819 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.482432 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.482262 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 60692059 31.43% 31.43% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 60170871 31.27% 31.27% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 53894832 27.91% 59.33% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 53695201 27.90% 59.17% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 35675096 18.47% 77.80% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 36000837 18.71% 77.87% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 21030275 10.89% 88.69% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 20815986 10.82% 88.69% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 13671463 7.08% 95.77% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 13514067 7.02% 95.71% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::5 5219808 2.70% 98.47% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::5 5325466 2.77% 98.48% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::6 2207559 1.14% 99.62% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::6 2181156 1.13% 99.61% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::7 593955 0.31% 99.93% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::7 607811 0.32% 99.93% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::8 144777 0.07% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::8 140771 0.07% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::total 193129824 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::total 192452166 # Number of insts issued each cycle
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntAlu 112792 4.13% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntAlu 103783 3.80% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntMult 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.13% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.80% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemRead 2307770 84.43% 88.56% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemRead 2313613 84.82% 88.62% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemWrite 312724 11.44% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemWrite 310319 11.38% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 1204873 0.42% 0.42% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 1202882 0.42% 0.42% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 186986858 65.00% 65.42% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 186701896 64.99% 65.40% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.42% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.40% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.42% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.40% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatAdd 1646787 0.57% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatAdd 1648118 0.57% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.99% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 73289266 25.48% 91.46% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 73212241 25.48% 91.46% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 24554212 8.54% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 24531075 8.54% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 287681996 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 287296212 # Type of FU issued
|
||||||
system.cpu.iq.rate 1.488959 # Inst issue rate
|
system.cpu.iq.rate 1.492196 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 2733286 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 2727715 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.009501 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.009494 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 765968498 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 764505561 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 565842765 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 564134434 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 278370688 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 277997574 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 5504374 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 5504974 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 5354879 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 5363501 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 2643921 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 2644368 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 286442288 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 286052729 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 2768121 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 2768316 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 18982398 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 18967849 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 47534630 # Number of loads squashed
|
system.cpu.iew.lsq.thread0.squashedLoads 47345048 # Number of loads squashed
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 34246 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iew.lsq.thread0.ignoredResponses 33748 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 347654 # Number of memory ordering violations
|
system.cpu.iew.lsq.thread0.memOrderViolation 344727 # Number of memory ordering violations
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 16737148 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 16655557 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 48277 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 48770 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 23682895 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 23582874 # Number of cycles IEW is squashing
|
||||||
system.cpu.iew.iewBlockCycles 506655 # Number of cycles IEW is blocking
|
system.cpu.iew.iewBlockCycles 506702 # Number of cycles IEW is blocking
|
||||||
system.cpu.iew.iewUnblockCycles 213138 # Number of cycles IEW is unblocking
|
system.cpu.iew.iewUnblockCycles 199063 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iew.iewDispatchedInsts 396408793 # Number of instructions dispatched to IQ
|
system.cpu.iew.iewDispatchedInsts 395558376 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iew.iewDispSquashedInsts 134440 # Number of squashed instructions skipped by dispatch
|
system.cpu.iew.iewDispSquashedInsts 136305 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iew.iewDispLoadInsts 104184220 # Number of dispatched load instructions
|
system.cpu.iew.iewDispLoadInsts 103994638 # Number of dispatched load instructions
|
||||||
system.cpu.iew.iewDispStoreInsts 37252864 # Number of dispatched store instructions
|
system.cpu.iew.iewDispStoreInsts 37171273 # Number of dispatched store instructions
|
||||||
system.cpu.iew.iewDispNonSpecInsts 1768 # Number of dispatched non-speculative instructions
|
system.cpu.iew.iewDispNonSpecInsts 1768 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.iew.iewIQFullEvents 119463 # Number of times the IQ has become full, causing a stall
|
system.cpu.iew.iewIQFullEvents 106766 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.iew.iewLSQFullEvents 15480 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iew.iewLSQFullEvents 14420 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.iew.memOrderViolationEvents 347654 # Number of memory order violations
|
system.cpu.iew.memOrderViolationEvents 344727 # Number of memory order violations
|
||||||
system.cpu.iew.predictedTakenIncorrect 2501516 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 2499729 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 594763 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 593078 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 3096279 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 3092807 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 283823488 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 283409034 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 71745820 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 71642320 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 3858508 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 3887178 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 95800830 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 95673519 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 15659373 # Number of branches executed
|
system.cpu.iew.exec_branches 15642768 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 24055010 # Number of stores executed
|
system.cpu.iew.exec_stores 24031199 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 1.468989 # Inst execution rate
|
system.cpu.iew.exec_rate 1.472006 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 282310074 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 281921944 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 281014609 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 280641942 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 227952457 # num instructions producing a value
|
system.cpu.iew.wb_producers 227553614 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 378837228 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 378165457 # num instructions consuming a value
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.iew.wb_rate 1.454451 # insts written-back per cycle
|
system.cpu.iew.wb_rate 1.457634 # insts written-back per cycle
|
||||||
system.cpu.iew.wb_fanout 0.601716 # average fanout of values written-back
|
system.cpu.iew.wb_fanout 0.601730 # average fanout of values written-back
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
|
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
|
||||||
system.cpu.commit.commitSquashedInsts 175071707 # The number of squashed insts skipped by commit
|
system.cpu.commit.commitSquashedInsts 174222633 # The number of squashed insts skipped by commit
|
||||||
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.commit.branchMispredicts 2895631 # The number of times a branch was mispredicted
|
system.cpu.commit.branchMispredicts 2892920 # The number of times a branch was mispredicted
|
||||||
system.cpu.commit.committed_per_cycle::samples 169446929 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::samples 168869292 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.306386 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::mean 1.310854 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::stdev 1.743043 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::stdev 1.745147 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::0 63655929 37.57% 37.57% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::0 63124360 37.38% 37.38% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::1 62181133 36.70% 74.26% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::1 62150025 36.80% 74.18% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::2 15647987 9.23% 83.50% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::2 15630374 9.26% 83.44% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::3 11995121 7.08% 90.58% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::3 11975959 7.09% 90.53% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::4 5411057 3.19% 93.77% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::4 5416595 3.21% 93.74% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::5 2989620 1.76% 95.53% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::5 2994905 1.77% 95.51% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::6 2014905 1.19% 96.72% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::6 2021663 1.20% 96.71% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::7 1190627 0.70% 97.43% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::7 1189804 0.70% 97.41% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::8 4360550 2.57% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::8 4365607 2.59% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::total 169446929 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::total 168869292 # Number of insts commited each cycle
|
||||||
system.cpu.commit.count 221363017 # Number of instructions committed
|
system.cpu.commit.count 221363017 # Number of instructions committed
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.commit.refs 77165306 # Number of memory references committed
|
system.cpu.commit.refs 77165306 # Number of memory references committed
|
||||||
|
@ -265,50 +265,50 @@ system.cpu.commit.branches 12326943 # Nu
|
||||||
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
|
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
|
||||||
system.cpu.commit.int_insts 220339606 # Number of committed integer instructions.
|
system.cpu.commit.int_insts 220339606 # Number of committed integer instructions.
|
||||||
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
||||||
system.cpu.commit.bw_lim_events 4360550 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 4365607 # number cycles where commit BW limit reached
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.rob.rob_reads 561521103 # The number of ROB reads
|
system.cpu.rob.rob_reads 560089335 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 816599274 # The number of ROB writes
|
system.cpu.rob.rob_writes 814800236 # The number of ROB writes
|
||||||
system.cpu.timesIdled 1748 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 1747 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 80265 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 80351 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu.committedInsts 221363017 # Number of Instructions Simulated
|
system.cpu.committedInsts 221363017 # Number of Instructions Simulated
|
||||||
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
|
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
|
||||||
system.cpu.cpi 0.872820 # CPI: Cycles Per Instruction
|
system.cpu.cpi 0.869759 # CPI: Cycles Per Instruction
|
||||||
system.cpu.cpi_total 0.872820 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 0.869759 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 1.145711 # IPC: Instructions Per Cycle
|
system.cpu.ipc 1.149744 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 1.145711 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 1.149744 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 530797158 # number of integer regfile reads
|
system.cpu.int_regfile_reads 530367480 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 288957450 # number of integer regfile writes
|
system.cpu.int_regfile_writes 288604591 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 3607584 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 3608788 # number of floating regfile reads
|
||||||
system.cpu.fp_regfile_writes 2298041 # number of floating regfile writes
|
system.cpu.fp_regfile_writes 2298113 # number of floating regfile writes
|
||||||
system.cpu.misc_regfile_reads 149916629 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 149639402 # number of misc regfile reads
|
||||||
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
|
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
|
||||||
system.cpu.icache.replacements 4194 # number of replacements
|
system.cpu.icache.replacements 4205 # number of replacements
|
||||||
system.cpu.icache.tagsinuse 1596.157530 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 1597.649860 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 28821740 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 28751182 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.sampled_refs 6159 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 6167 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.avg_refs 4679.613574 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 4662.101832 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.occ_blocks::0 1596.157530 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 1597.649860 # Average occupied blocks per context
|
||||||
system.cpu.icache.occ_percent::0 0.779374 # Average percentage of cache occupancy
|
system.cpu.icache.occ_percent::0 0.780102 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.ReadReq_hits 28821740 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 28751182 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits 28821740 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 28751182 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits 28821740 # number of overall hits
|
system.cpu.icache.overall_hits 28751182 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses 7534 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 7479 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses 7534 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 7479 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses 7534 # number of overall misses
|
system.cpu.icache.overall_misses 7479 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 174012500 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 173725000 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency 174012500 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 173725000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency 174012500 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 173725000 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses 28829274 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 28758661 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses 28829274 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 28758661 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses 28829274 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 28758661 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000261 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000260 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate 0.000261 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000260 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate 0.000261 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000260 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 23096.960446 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 23228.372777 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency 23096.960446 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 23228.372777 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency 23096.960446 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 23228.372777 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -318,59 +318,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_mshr_hits 1131 # number of ReadReq MSHR hits
|
system.cpu.icache.ReadReq_mshr_hits 1119 # number of ReadReq MSHR hits
|
||||||
system.cpu.icache.demand_mshr_hits 1131 # number of demand (read+write) MSHR hits
|
system.cpu.icache.demand_mshr_hits 1119 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.icache.overall_mshr_hits 1131 # number of overall MSHR hits
|
system.cpu.icache.overall_mshr_hits 1119 # number of overall MSHR hits
|
||||||
system.cpu.icache.ReadReq_mshr_misses 6403 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 6360 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.demand_mshr_misses 6403 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses 6360 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses 6403 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses 6360 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 125261500 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency 125233500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency 125261500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency 125233500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency 125261500 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency 125233500 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000222 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000221 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000222 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate 0.000221 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000222 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate 0.000221 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 19562.939247 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 19690.801887 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 19562.939247 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 19690.801887 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 19562.939247 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 19690.801887 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.replacements 57 # number of replacements
|
system.cpu.dcache.replacements 56 # number of replacements
|
||||||
system.cpu.dcache.tagsinuse 1416.139533 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 1415.486536 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 73025896 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 72938173 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.sampled_refs 1980 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 1987 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.avg_refs 36881.765657 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 36707.686462 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.occ_blocks::0 1416.139533 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 1415.486536 # Average occupied blocks per context
|
||||||
system.cpu.dcache.occ_percent::0 0.345737 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_percent::0 0.345578 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.ReadReq_hits 52511655 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 52423955 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits 20513921 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 20513973 # number of WriteReq hits
|
||||||
system.cpu.dcache.demand_hits 73025576 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 72937928 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.overall_hits 73025576 # number of overall hits
|
system.cpu.dcache.overall_hits 72937928 # number of overall hits
|
||||||
system.cpu.dcache.ReadReq_misses 756 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 771 # number of ReadReq misses
|
||||||
system.cpu.dcache.WriteReq_misses 1809 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 1757 # number of WriteReq misses
|
||||||
system.cpu.dcache.demand_misses 2565 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 2528 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.overall_misses 2565 # number of overall misses
|
system.cpu.dcache.overall_misses 2528 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency 24125500 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 24605500 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency 68553000 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 66582500 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency 92678500 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 91188000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency 92678500 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 91188000 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses 52512411 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 52424726 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.demand_accesses 73028141 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 72940456 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.overall_accesses 73028141 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 72940456 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.000088 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.000086 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_miss_rate 0.000035 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.000035 # miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_miss_rate 0.000035 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.000035 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 31912.037037 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 31913.748379 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 37895.522388 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 37895.560615 # average WriteReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency 36131.968811 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 36071.202532 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency 36131.968811 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 36071.202532 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -379,72 +379,72 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.writebacks 14 # number of writebacks
|
system.cpu.dcache.writebacks 13 # number of writebacks
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 336 # number of ReadReq MSHR hits
|
system.cpu.dcache.ReadReq_mshr_hits 344 # number of ReadReq MSHR hits
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 2 # number of WriteReq MSHR hits
|
system.cpu.dcache.WriteReq_mshr_hits 2 # number of WriteReq MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_hits 338 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 346 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_hits 338 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 346 # number of overall MSHR hits
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 1807 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 1755 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.demand_mshr_misses 2227 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 2182 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses 2227 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 2182 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 13927500 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 14039500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 63059000 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 61244500 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 76986500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 75284000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 76986500 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 75284000 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000086 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.000030 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.000030 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.000030 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.000030 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 33160.714286 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32879.391101 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34897.066962 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34897.150997 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34569.600359 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 34502.291476 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34569.600359 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 34502.291476 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.replacements 0 # number of replacements
|
system.cpu.l2cache.replacements 0 # number of replacements
|
||||||
system.cpu.l2cache.tagsinuse 2497.262524 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 2496.824684 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 2830 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 2842 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.sampled_refs 3752 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 3755 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 0.754264 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 0.756858 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.occ_blocks::0 2495.282024 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 2494.880189 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 1.980500 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 1.944495 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.076150 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.076138 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.000060 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.000059 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.ReadReq_hits 2828 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 2840 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits 14 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 13 # number of Writeback hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits 2836 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 2848 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits 2836 # number of overall hits
|
system.cpu.l2cache.overall_hits 2848 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses 3749 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 3753 # number of ReadReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_misses 245 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses 193 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses 1555 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 1555 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses 5304 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 5308 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses 5304 # number of overall misses
|
system.cpu.l2cache.overall_misses 5308 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 128398000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 128533500 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 53104500 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 53066500 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency 181502500 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 181600000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency 181502500 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 181600000 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses 6577 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 6593 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_accesses 14 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 13 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_accesses 245 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses 193 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_accesses 1563 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 1563 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.demand_accesses 8140 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 8156 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 8140 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 8156 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.570017 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.569240 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.994882 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 0.994882 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate 0.651597 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.650809 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate 0.651597 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.650809 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34248.599627 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34248.201439 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34150.803859 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34126.366559 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34219.928356 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 34212.509420 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34219.928356 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34212.509420 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
@ -456,28 +456,28 @@ system.cpu.l2cache.cache_copies 0 # nu
|
||||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 3749 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 3753 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses 245 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses 193 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 1555 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 1555 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses 5304 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 5308 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses 5304 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 5308 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 116287000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 116413500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7595000 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5983000 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48232500 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48232500 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 164519500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 164646000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 164519500 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 164646000 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.570017 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.569240 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994882 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994882 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.651597 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.650809 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.651597 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.650809 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.138170 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.784972 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31017.684887 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31017.684887 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.005279 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.462698 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.005279 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.462698 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
[root]
|
[root]
|
||||||
type=Root
|
type=Root
|
||||||
children=system
|
children=system
|
||||||
|
full_system=false
|
||||||
time_sync_enable=false
|
time_sync_enable=false
|
||||||
time_sync_period=100000000000
|
time_sync_period=100000000000
|
||||||
time_sync_spin_threshold=100000000
|
time_sync_spin_threshold=100000000
|
||||||
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
||||||
[system]
|
[system]
|
||||||
type=System
|
type=System
|
||||||
children=cpu membus physmem
|
children=cpu membus physmem
|
||||||
|
boot_osflags=a
|
||||||
|
init_param=0
|
||||||
|
kernel=
|
||||||
|
load_addr_mask=1099511627775
|
||||||
mem_mode=atomic
|
mem_mode=atomic
|
||||||
memories=system.physmem
|
memories=system.physmem
|
||||||
num_work_ids=16
|
num_work_ids=16
|
||||||
physmem=system.physmem
|
physmem=system.physmem
|
||||||
|
readfile=
|
||||||
|
symbolfile=
|
||||||
work_begin_ckpt_count=0
|
work_begin_ckpt_count=0
|
||||||
work_begin_cpu_id_exit=-1
|
work_begin_cpu_id_exit=-1
|
||||||
work_begin_exit_count=0
|
work_begin_exit_count=0
|
||||||
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
||||||
|
|
||||||
[system.cpu]
|
[system.cpu]
|
||||||
type=DerivO3CPU
|
type=DerivO3CPU
|
||||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||||
BTBEntries=4096
|
BTBEntries=4096
|
||||||
BTBTagSize=16
|
BTBTagSize=16
|
||||||
LFSTSize=1024
|
LFSTSize=1024
|
||||||
|
@ -52,6 +59,7 @@ decodeWidth=8
|
||||||
defer_registration=false
|
defer_registration=false
|
||||||
dispatchWidth=8
|
dispatchWidth=8
|
||||||
do_checkpoint_insts=true
|
do_checkpoint_insts=true
|
||||||
|
do_quiesce=true
|
||||||
do_statistics_insts=true
|
do_statistics_insts=true
|
||||||
dtb=system.cpu.dtb
|
dtb=system.cpu.dtb
|
||||||
fetchToDecodeDelay=1
|
fetchToDecodeDelay=1
|
||||||
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
||||||
iewToFetchDelay=1
|
iewToFetchDelay=1
|
||||||
iewToRenameDelay=1
|
iewToRenameDelay=1
|
||||||
instShiftAmt=2
|
instShiftAmt=2
|
||||||
|
interrupts=system.cpu.interrupts
|
||||||
issueToExecuteDelay=1
|
issueToExecuteDelay=1
|
||||||
issueWidth=8
|
issueWidth=8
|
||||||
itb=system.cpu.itb
|
itb=system.cpu.itb
|
||||||
|
@ -80,6 +89,7 @@ max_insts_all_threads=0
|
||||||
max_insts_any_thread=0
|
max_insts_any_thread=0
|
||||||
max_loads_all_threads=0
|
max_loads_all_threads=0
|
||||||
max_loads_any_thread=0
|
max_loads_any_thread=0
|
||||||
|
needsTSO=false
|
||||||
numIQEntries=64
|
numIQEntries=64
|
||||||
numPhysFloatRegs=256
|
numPhysFloatRegs=256
|
||||||
numPhysIntRegs=256
|
numPhysIntRegs=256
|
||||||
|
@ -88,6 +98,7 @@ numRobs=1
|
||||||
numThreads=1
|
numThreads=1
|
||||||
phase=0
|
phase=0
|
||||||
predType=tournament
|
predType=tournament
|
||||||
|
profile=0
|
||||||
progress_interval=0
|
progress_interval=0
|
||||||
renameToDecodeDelay=1
|
renameToDecodeDelay=1
|
||||||
renameToFetchDelay=1
|
renameToFetchDelay=1
|
||||||
|
@ -148,7 +159,16 @@ mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
[system.cpu.dtb]
|
[system.cpu.dtb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.dtb.walker
|
||||||
|
|
||||||
|
[system.cpu.dtb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[3]
|
||||||
|
|
||||||
[system.cpu.fuPool]
|
[system.cpu.fuPool]
|
||||||
type=FUPool
|
type=FUPool
|
||||||
|
@ -445,9 +465,21 @@ write_buffers=8
|
||||||
cpu_side=system.cpu.icache_port
|
cpu_side=system.cpu.icache_port
|
||||||
mem_side=system.cpu.toL2Bus.port[0]
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.interrupts]
|
||||||
|
type=ArmInterrupts
|
||||||
|
|
||||||
[system.cpu.itb]
|
[system.cpu.itb]
|
||||||
type=ArmTLB
|
type=ArmTLB
|
||||||
|
children=walker
|
||||||
size=64
|
size=64
|
||||||
|
walker=system.cpu.itb.walker
|
||||||
|
|
||||||
|
[system.cpu.itb.walker]
|
||||||
|
type=ArmTableWalker
|
||||||
|
max_backoff=100000
|
||||||
|
min_backoff=0
|
||||||
|
sys=system
|
||||||
|
port=system.cpu.toL2Bus.port[2]
|
||||||
|
|
||||||
[system.cpu.l2cache]
|
[system.cpu.l2cache]
|
||||||
type=BaseCache
|
type=BaseCache
|
||||||
|
@ -478,7 +510,7 @@ tgts_per_mshr=5
|
||||||
trace_addr=0
|
trace_addr=0
|
||||||
two_queue=false
|
two_queue=false
|
||||||
write_buffers=8
|
write_buffers=8
|
||||||
cpu_side=system.cpu.toL2Bus.port[2]
|
cpu_side=system.cpu.toL2Bus.port[4]
|
||||||
mem_side=system.membus.port[2]
|
mem_side=system.membus.port[2]
|
||||||
|
|
||||||
[system.cpu.toL2Bus]
|
[system.cpu.toL2Bus]
|
||||||
|
@ -489,7 +521,7 @@ clock=1000
|
||||||
header_cycles=1
|
header_cycles=1
|
||||||
use_default_range=false
|
use_default_range=false
|
||||||
width=64
|
width=64
|
||||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
[system.cpu.tracer]
|
[system.cpu.tracer]
|
||||||
type=ExeTracer
|
type=ExeTracer
|
||||||
|
@ -502,7 +534,7 @@ egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
|
executable=tests/test-progs/hello/bin/arm/linux/hello
|
||||||
gid=100
|
gid=100
|
||||||
input=cin
|
input=cin
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
|
|
|
@ -1,11 +1,13 @@
|
||||||
|
Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout
|
||||||
|
Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr
|
||||||
gem5 Simulator System. http://gem5.org
|
gem5 Simulator System. http://gem5.org
|
||||||
gem5 is copyrighted software; use the --copyright option for details.
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
gem5 compiled Jan 23 2012 04:16:21
|
gem5 compiled Feb 10 2012 00:18:03
|
||||||
gem5 started Jan 23 2012 04:24:50
|
gem5 started Feb 10 2012 07:27:01
|
||||||
gem5 executing on zizzer
|
gem5 executing on ribera.cs.wisc.edu
|
||||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing
|
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
Hello world!
|
Hello world!
|
||||||
Exiting @ tick 10001500 because target called exit()
|
Exiting @ tick 10000500 because target called exit()
|
||||||
|
|
|
@ -1,13 +1,13 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
sim_seconds 0.000010 # Number of seconds simulated
|
sim_seconds 0.000010 # Number of seconds simulated
|
||||||
sim_ticks 10001500 # Number of ticks simulated
|
sim_ticks 10000500 # Number of ticks simulated
|
||||||
final_tick 10001500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 10000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 15723 # Simulator instruction rate (inst/s)
|
host_inst_rate 48981 # Simulator instruction rate (inst/s)
|
||||||
host_tick_rate 27400304 # Simulator tick rate (ticks/s)
|
host_tick_rate 85336508 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 218472 # Number of bytes of host memory used
|
host_mem_usage 252096 # Number of bytes of host memory used
|
||||||
host_seconds 0.37 # Real time elapsed on the host
|
host_seconds 0.12 # Real time elapsed on the host
|
||||||
sim_insts 5739 # Number of instructions simulated
|
sim_insts 5739 # Number of instructions simulated
|
||||||
system.physmem.bytes_read 25856 # Number of bytes read from this memory
|
system.physmem.bytes_read 25856 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory
|
||||||
|
@ -15,9 +15,9 @@ system.physmem.bytes_written 0 # Nu
|
||||||
system.physmem.num_reads 404 # Number of read requests responded to by this memory
|
system.physmem.num_reads 404 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes 0 # Number of write requests responded to by this memory
|
system.physmem.num_writes 0 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||||
system.physmem.bw_read 2585212218 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read 2585470726 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read 1785332200 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read 1785510724 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_total 2585212218 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total 2585470726 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||||
|
@ -61,7 +61,7 @@ system.cpu.itb.hits 0 # DT
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||||
system.cpu.numCycles 20004 # number of cpu cycles simulated
|
system.cpu.numCycles 20002 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.BPredUnit.lookups 2398 # Number of BP lookups
|
system.cpu.BPredUnit.lookups 2398 # Number of BP lookups
|
||||||
|
@ -72,8 +72,8 @@ system.cpu.BPredUnit.BTBHits 703 # Nu
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
system.cpu.BPredUnit.usedRAS 246 # Number of times the RAS was used to get a target.
|
system.cpu.BPredUnit.usedRAS 246 # Number of times the RAS was used to get a target.
|
||||||
system.cpu.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions.
|
system.cpu.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 6120 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 6118 # Number of cycles fetch is stalled on an Icache miss
|
||||||
system.cpu.fetch.Insts 12134 # Number of instructions fetch has processed
|
system.cpu.fetch.Insts 12133 # Number of instructions fetch has processed
|
||||||
system.cpu.fetch.Branches 2398 # Number of branches that fetch encountered
|
system.cpu.fetch.Branches 2398 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.Cycles 2694 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.fetch.Cycles 2694 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
|
@ -81,28 +81,28 @@ system.cpu.fetch.SquashCycles 1578 # Nu
|
||||||
system.cpu.fetch.BlockedCycles 1626 # Number of cycles fetch has spent blocked
|
system.cpu.fetch.BlockedCycles 1626 # Number of cycles fetch has spent blocked
|
||||||
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
system.cpu.fetch.PendingTrapStallCycles 19 # Number of stall cycles due to pending traps
|
system.cpu.fetch.PendingTrapStallCycles 19 # Number of stall cycles due to pending traps
|
||||||
system.cpu.fetch.CacheLines 1920 # Number of cache lines fetched
|
system.cpu.fetch.CacheLines 1919 # Number of cache lines fetched
|
||||||
system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed
|
system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 11510 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 11508 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 1.338054 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 1.338286 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 2.716635 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 2.716814 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::0 8816 76.59% 76.59% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::0 8814 76.59% 76.59% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::1 262 2.28% 78.87% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::1 262 2.28% 78.87% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::2 169 1.47% 80.34% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::2 169 1.47% 80.34% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::3 225 1.95% 82.29% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::3 225 1.96% 82.29% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::4 227 1.97% 84.27% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::4 227 1.97% 84.26% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::5 313 2.72% 86.99% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::5 313 2.72% 86.98% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::6 109 0.95% 87.93% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::6 109 0.95% 87.93% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::7 113 0.98% 88.91% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::7 113 0.98% 88.91% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::8 1276 11.09% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::8 1276 11.09% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 11510 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 11508 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.branchRate 0.119876 # Number of branch fetches per cycle
|
system.cpu.fetch.branchRate 0.119888 # Number of branch fetches per cycle
|
||||||
system.cpu.fetch.rate 0.606579 # Number of inst fetches per cycle
|
system.cpu.fetch.rate 0.606589 # Number of inst fetches per cycle
|
||||||
system.cpu.decode.IdleCycles 6265 # Number of cycles decode is idle
|
system.cpu.decode.IdleCycles 6263 # Number of cycles decode is idle
|
||||||
system.cpu.decode.BlockedCycles 1809 # Number of cycles decode is blocked
|
system.cpu.decode.BlockedCycles 1809 # Number of cycles decode is blocked
|
||||||
system.cpu.decode.RunCycles 2491 # Number of cycles decode is running
|
system.cpu.decode.RunCycles 2491 # Number of cycles decode is running
|
||||||
system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking
|
system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking
|
||||||
|
@ -112,7 +112,7 @@ system.cpu.decode.BranchMispred 168 # Nu
|
||||||
system.cpu.decode.DecodedInsts 13387 # Number of instructions handled by decode
|
system.cpu.decode.DecodedInsts 13387 # Number of instructions handled by decode
|
||||||
system.cpu.decode.SquashedInsts 587 # Number of squashed instructions handled by decode
|
system.cpu.decode.SquashedInsts 587 # Number of squashed instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 887 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 887 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 6541 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 6539 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 230 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 230 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 1411 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 1411 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 2270 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 2270 # Number of cycles rename is running
|
||||||
|
@ -139,11 +139,11 @@ system.cpu.iq.iqSquashedInstsIssued 95 # Nu
|
||||||
system.cpu.iq.iqSquashedInstsExamined 4802 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 4802 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 13397 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 13397 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.iq.issued_per_cycle::samples 11510 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::samples 11508 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::mean 0.756386 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 0.756517 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.438063 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.438154 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 8025 69.72% 69.72% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 8023 69.72% 69.72% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 1281 11.13% 80.85% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 1281 11.13% 80.85% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 772 6.71% 87.56% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 772 6.71% 87.56% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 541 4.70% 92.26% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 541 4.70% 92.26% # Number of insts issued each cycle
|
||||||
|
@ -155,7 +155,7 @@ system.cpu.iq.issued_per_cycle::8 11 0.10% 100.00% # Nu
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::total 11510 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::total 11508 # Number of insts issued each cycle
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntAlu 2 0.99% 0.99% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntAlu 2 0.99% 0.99% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 0.99% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IntMult 0 0.00% 0.99% # attempts to use FU when none available
|
||||||
|
@ -225,10 +225,10 @@ system.cpu.iq.FU_type_0::MemWrite 1222 14.04% 100.00% # Ty
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 8706 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 8706 # Type of FU issued
|
||||||
system.cpu.iq.rate 0.435213 # Inst issue rate
|
system.cpu.iq.rate 0.435256 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 203 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 203 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.023317 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.023317 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 29184 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 29182 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 15632 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 15632 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7824 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 7824 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
||||||
|
@ -269,26 +269,26 @@ system.cpu.iew.exec_nop 1 # nu
|
||||||
system.cpu.iew.exec_refs 3178 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 3178 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 1354 # Number of branches executed
|
system.cpu.iew.exec_branches 1354 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 1169 # Number of stores executed
|
system.cpu.iew.exec_stores 1169 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 0.414017 # Inst execution rate
|
system.cpu.iew.exec_rate 0.414059 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 7957 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 7957 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 7840 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 7840 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 3690 # num instructions producing a value
|
system.cpu.iew.wb_producers 3690 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 7291 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 7291 # num instructions consuming a value
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.iew.wb_rate 0.391922 # insts written-back per cycle
|
system.cpu.iew.wb_rate 0.391961 # insts written-back per cycle
|
||||||
system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back
|
system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions
|
system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions
|
||||||
system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit
|
system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit
|
||||||
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted
|
system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted
|
||||||
system.cpu.commit.committed_per_cycle::samples 10624 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::samples 10622 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::mean 0.540192 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::mean 0.540294 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::stdev 1.352731 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::stdev 1.352838 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::0 8288 78.01% 78.01% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::0 8286 78.01% 78.01% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::1 1088 10.24% 88.25% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::1 1088 10.24% 88.25% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::2 420 3.95% 92.21% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::2 420 3.95% 92.20% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::3 282 2.65% 94.86% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::3 282 2.65% 94.86% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::4 183 1.72% 96.58% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::4 183 1.72% 96.58% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::5 168 1.58% 98.16% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::5 168 1.58% 98.16% # Number of insts commited each cycle
|
||||||
|
@ -298,7 +298,7 @@ system.cpu.commit.committed_per_cycle::8 93 0.88% 100.00% # Nu
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::total 10624 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::total 10622 # Number of insts commited each cycle
|
||||||
system.cpu.commit.count 5739 # Number of instructions committed
|
system.cpu.commit.count 5739 # Number of instructions committed
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.commit.refs 2139 # Number of memory references committed
|
system.cpu.commit.refs 2139 # Number of memory references committed
|
||||||
|
@ -310,44 +310,44 @@ system.cpu.commit.int_insts 4985 # Nu
|
||||||
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
||||||
system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.rob.rob_reads 21207 # The number of ROB reads
|
system.cpu.rob.rob_reads 21205 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 22566 # The number of ROB writes
|
system.cpu.rob.rob_writes 22566 # The number of ROB writes
|
||||||
system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu.committedInsts 5739 # Number of Instructions Simulated
|
system.cpu.committedInsts 5739 # Number of Instructions Simulated
|
||||||
system.cpu.committedInsts_total 5739 # Number of Instructions Simulated
|
system.cpu.committedInsts_total 5739 # Number of Instructions Simulated
|
||||||
system.cpu.cpi 3.485625 # CPI: Cycles Per Instruction
|
system.cpu.cpi 3.485276 # CPI: Cycles Per Instruction
|
||||||
system.cpu.cpi_total 3.485625 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 3.485276 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 0.286893 # IPC: Instructions Per Cycle
|
system.cpu.ipc 0.286921 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 0.286893 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 0.286921 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 37816 # number of integer regfile reads
|
system.cpu.int_regfile_reads 37816 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 7658 # number of integer regfile writes
|
system.cpu.int_regfile_writes 7658 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||||
system.cpu.misc_regfile_reads 14993 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 14992 # number of misc regfile reads
|
||||||
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
||||||
system.cpu.icache.replacements 2 # number of replacements
|
system.cpu.icache.replacements 2 # number of replacements
|
||||||
system.cpu.icache.tagsinuse 148.864335 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 148.855822 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 1560 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 1559 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.sampled_refs 297 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 297 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.avg_refs 5.252525 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 5.249158 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.occ_blocks::0 148.864335 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 148.855822 # Average occupied blocks per context
|
||||||
system.cpu.icache.occ_percent::0 0.072688 # Average percentage of cache occupancy
|
system.cpu.icache.occ_percent::0 0.072684 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.ReadReq_hits 1560 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 1559 # number of ReadReq hits
|
||||||
system.cpu.icache.demand_hits 1560 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 1559 # number of demand (read+write) hits
|
||||||
system.cpu.icache.overall_hits 1560 # number of overall hits
|
system.cpu.icache.overall_hits 1559 # number of overall hits
|
||||||
system.cpu.icache.ReadReq_misses 360 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 360 # number of ReadReq misses
|
||||||
system.cpu.icache.demand_misses 360 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 360 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses 360 # number of overall misses
|
system.cpu.icache.overall_misses 360 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 12552000 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 12552000 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency 12552000 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 12552000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency 12552000 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 12552000 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses 1920 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 1919 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses 1920 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 1919 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.overall_accesses 1920 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 1919 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.187500 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.187598 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_miss_rate 0.187500 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.187598 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate 0.187500 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.187598 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 34866.666667 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 34866.666667 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency 34866.666667 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 34866.666667 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency 34866.666667 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 34866.666667 # average overall miss latency
|
||||||
|
@ -371,9 +371,9 @@ system.cpu.icache.ReadReq_mshr_miss_latency 9945000 #
|
||||||
system.cpu.icache.demand_mshr_miss_latency 9945000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency 9945000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency 9945000 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency 9945000 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.154688 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.154768 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.154688 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate 0.154768 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.154688 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate 0.154768 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 33484.848485 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 33484.848485 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency
|
||||||
|
@ -382,13 +382,13 @@ system.cpu.icache.mshr_cap_events 0 # nu
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.replacements 0 # number of replacements
|
system.cpu.dcache.replacements 0 # number of replacements
|
||||||
system.cpu.dcache.tagsinuse 89.089443 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 89.085552 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.avg_refs 15.136364 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 15.136364 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.occ_blocks::0 89.089443 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 89.085552 # Average occupied blocks per context
|
||||||
system.cpu.dcache.occ_percent::0 0.021750 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_percent::0 0.021749 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.ReadReq_hits 1702 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 1702 # number of ReadReq hits
|
||||||
system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits
|
||||||
system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
|
system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
|
||||||
|
@ -458,12 +458,12 @@ system.cpu.dcache.mshr_cap_events 0 # nu
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.replacements 0 # number of replacements
|
system.cpu.l2cache.replacements 0 # number of replacements
|
||||||
system.cpu.l2cache.tagsinuse 188.120549 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 188.110462 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 0.116022 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 0.116022 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.occ_blocks::0 188.120549 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 188.110462 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.005741 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.005741 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.ReadReq_hits 42 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 42 # number of ReadReq hits
|
||||||
system.cpu.l2cache.demand_hits 42 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 42 # number of demand (read+write) hits
|
||||||
|
|
Loading…
Reference in a new issue