491 lines
55 KiB
Plaintext
491 lines
55 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.488026 # Number of seconds simulated
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sim_ticks 488026375000 # Number of ticks simulated
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final_tick 488026375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 87795 # Simulator instruction rate (inst/s)
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host_tick_rate 28022613 # Simulator tick rate (ticks/s)
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host_mem_usage 289796 # Number of bytes of host memory used
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host_seconds 17415.45 # Real time elapsed on the host
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sim_insts 1528988756 # Number of instructions simulated
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system.physmem.bytes_read 37539712 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 347136 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 26338560 # Number of bytes written to this memory
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system.physmem.num_reads 586558 # Number of read requests responded to by this memory
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system.physmem.num_writes 411540 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 76921482 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 711306 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 53969542 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 130891024 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.workload.num_syscalls 551 # Number of system calls
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system.cpu.numCycles 976052751 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 244909233 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 244909233 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 16551670 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 235577670 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 217623896 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 203635164 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 1335786629 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 244909233 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 217623896 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 434745893 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 118311552 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 217882141 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 29891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 232496 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 193900404 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 4295951 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 958022628 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.604337 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.317097 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 527271952 55.04% 55.04% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 32005205 3.34% 58.38% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 38652146 4.03% 62.41% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 32799855 3.42% 65.84% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 21637734 2.26% 68.10% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 36320351 3.79% 71.89% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 49291435 5.15% 77.03% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 36948107 3.86% 80.89% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 183095843 19.11% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 958022628 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.250918 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.368560 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 263275556 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 173167084 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 371540300 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 48542645 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 101497043 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 2434504159 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 101497043 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 300930740 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 38821666 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 14830 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 381234584 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 135523765 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 2382098494 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 2610 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 23187923 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 93850518 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 43 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 2215803805 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 5602953970 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 5602704256 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 249714 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 788504778 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 1415 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 315035024 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 575221657 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 225407627 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 224840659 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 66447324 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 2274732306 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 12754 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 1918512611 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 1302000 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 743201845 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 1165991477 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 12201 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 958022628 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.002575 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.809760 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 277706841 28.99% 28.99% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 160285139 16.73% 45.72% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 161386173 16.85% 62.56% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 150309706 15.69% 78.25% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 108022954 11.28% 89.53% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 60994203 6.37% 95.90% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 28856033 3.01% 98.91% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 9365653 0.98% 99.89% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 1095926 0.11% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 958022628 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 2261253 14.71% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 10108961 65.75% 80.46% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 3003496 19.54% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 2434143 0.13% 0.13% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 1271908482 66.30% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.42% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 462991606 24.13% 90.56% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 181178380 9.44% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 1918512611 # Type of FU issued
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system.cpu.iq.rate 1.965583 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 15373710 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.008013 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 4811718392 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 3018136915 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 1871298739 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.fp_inst_queue_reads 5168 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 82228 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.int_alu_accesses 1931450456 # Number of integer alu accesses
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system.cpu.iq.fp_alu_accesses 1722 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.forwLoads 171083363 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread0.squashedLoads 191119497 # Number of loads squashed
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system.cpu.iew.lsq.thread0.ignoredResponses 436651 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread0.memOrderViolation 282394 # Number of memory ordering violations
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system.cpu.iew.lsq.thread0.squashedStores 76247769 # Number of stores squashed
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system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread0.rescheduledLoads 6215 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewSquashCycles 101497043 # Number of cycles IEW is squashing
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system.cpu.iew.iewBlockCycles 7669372 # Number of cycles IEW is blocking
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system.cpu.iew.iewUnblockCycles 1230820 # Number of cycles IEW is unblocking
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system.cpu.iew.iewDispatchedInsts 2274745060 # Number of instructions dispatched to IQ
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system.cpu.iew.iewDispSquashedInsts 1222472 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispLoadInsts 575221657 # Number of dispatched load instructions
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system.cpu.iew.iewDispStoreInsts 225407954 # Number of dispatched store instructions
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system.cpu.iew.iewDispNonSpecInsts 6105 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewIQFullEvents 878634 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewLSQFullEvents 17249 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.memOrderViolationEvents 282394 # Number of memory order violations
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system.cpu.iew.predictedTakenIncorrect 15676996 # Number of branches that were predicted taken incorrectly
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system.cpu.iew.predictedNotTakenIncorrect 2334571 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.branchMispredicts 18011567 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewExecutedInsts 1885150488 # Number of executed instructions
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system.cpu.iew.iewExecLoadInsts 454035777 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 33362123 # Number of squashed instructions skipped in execute
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system.cpu.iew.exec_swp 0 # number of swp insts executed
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system.cpu.iew.exec_nop 0 # number of nop insts executed
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system.cpu.iew.exec_refs 627868559 # number of memory reference insts executed
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system.cpu.iew.exec_branches 176458351 # Number of branches executed
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system.cpu.iew.exec_stores 173832782 # Number of stores executed
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system.cpu.iew.exec_rate 1.931402 # Inst execution rate
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system.cpu.iew.wb_sent 1879040223 # cumulative count of insts sent to commit
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system.cpu.iew.wb_count 1871298858 # cumulative count of insts written-back
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system.cpu.iew.wb_producers 1436941600 # num instructions producing a value
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system.cpu.iew.wb_consumers 2126368380 # num instructions consuming a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.wb_rate 1.917211 # insts written-back per cycle
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system.cpu.iew.wb_fanout 0.675773 # average fanout of values written-back
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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|
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
|
|
system.cpu.commit.commitSquashedInsts 745779287 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 16577287 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 856525585 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.785106 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.285139 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 331592690 38.71% 38.71% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 211839945 24.73% 63.45% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 76804588 8.97% 72.41% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 92775414 10.83% 83.24% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 33678704 3.93% 87.18% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 28505123 3.33% 90.50% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 15688691 1.83% 92.34% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 11282624 1.32% 93.65% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 54357806 6.35% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 856525585 # Number of insts commited each cycle
|
|
system.cpu.commit.count 1528988756 # Number of instructions committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 533262345 # Number of memory references committed
|
|
system.cpu.commit.loads 384102160 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 149758588 # Number of branches committed
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 54357806 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 3076935822 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 4651204201 # The number of ROB writes
|
|
system.cpu.timesIdled 418807 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 18030123 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
|
|
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.638365 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.638365 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.566502 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.566502 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 3175693593 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1742205758 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 120 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 1036377940 # number of misc regfile reads
|
|
system.cpu.icache.replacements 10111 # number of replacements
|
|
system.cpu.icache.tagsinuse 973.820201 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 193659156 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 11601 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 16693.315749 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::0 973.820201 # Average occupied blocks per context
|
|
system.cpu.icache.occ_percent::0 0.475498 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits 193665655 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits 193665655 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits 193665655 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses 234749 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses 234749 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses 234749 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency 1699920500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency 1699920500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency 1699920500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses 193900404 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses 193900404 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses 193900404 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate 0.001211 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate 0.001211 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate 0.001211 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency 7241.438728 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency 7241.438728 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency 7241.438728 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks 4 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits 2040 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits 2040 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits 2040 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses 232709 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses 232709 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses 232709 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 952455000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency 952455000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency 952455000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.001200 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate 0.001200 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate 0.001200 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4092.901435 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 4092.901435 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 4092.901435 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 2529316 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4087.520068 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 427611101 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 2533412 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 168.788614 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 2115074000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::0 4087.520068 # Average occupied blocks per context
|
|
system.cpu.dcache.occ_percent::0 0.997930 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits 278887188 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits 148162157 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits 427049345 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits 427049345 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses 2665882 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses 998044 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses 3663926 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses 3663926 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency 39487902000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency 20586128000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency 60074030000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency 60074030000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses 281553070 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses 430713271 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses 430713271 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate 0.009468 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate 0.006691 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate 0.008507 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate 0.008507 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 14812.321776 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 20626.473382 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency 16396.081689 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency 16396.081689 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks 2229932 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits 902993 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits 909446 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits 909446 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses 1762889 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses 991591 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses 2754480 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses 2754480 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 14966916500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 17535799000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency 32502715500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency 32502715500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.006261 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006648 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.006395 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.006395 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8489.993698 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17684.508028 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 11799.946088 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 11799.946088 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 575774 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 21621.732877 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 3195554 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 594946 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 5.371166 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 268816776000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::0 7838.250700 # Average occupied blocks per context
|
|
system.cpu.l2cache.occ_blocks::1 13783.482177 # Average occupied blocks per context
|
|
system.cpu.l2cache.occ_percent::0 0.239204 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::1 0.420638 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits 1434280 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits 2229936 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits 1289 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits 524029 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits 1958309 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits 1958309 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses 339456 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses 219771 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses 247125 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses 586581 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses 586581 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency 11594725000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 9650000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency 8467808500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency 20062533500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency 20062533500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses 1773736 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses 2229936 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses 221060 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses 771154 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses 2544890 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses 2544890 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.191379 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.994169 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.320461 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate 0.230494 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate 0.230494 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34156.783206 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 43.909342 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34265.284775 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency 34202.494626 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency 34202.494626 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks 411540 # number of writebacks
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses 339456 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 219771 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 247125 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses 586581 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses 586581 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 10530013500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6813351000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7661828500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency 18191842000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency 18191842000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191379 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994169 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320461 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.230494 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.230494 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.260358 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.047586 # average UpgradeReq mshr miss latency
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|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31003.858371 # average ReadExReq mshr miss latency
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|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.350245 # average overall mshr miss latency
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|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.350245 # average overall mshr miss latency
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|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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|
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---------- End Simulation Statistics ----------
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