x86: Changes to decoder, corrects 9376

The changes made by the changeset 9376 were not quite correct. The patch made
changes to the code which resulted in decoder not getting initialized correctly
when the state was restored from a checkpoint.

This patch adds a startup function to each ISA object. For x86, this function
sets the required state in the decoder. For other ISAs, the function is empty
right now.

src/arch/alpha/isa.hh

@@ -106,6 +106,8 @@ namespace AlphaISA
         const Params *params() const;
 
         ISA(Params *p);
+
+        void startup(ThreadContext *tc) {}
     };
 }
 

src/arch/arm/isa.hh

@@ -193,6 +193,8 @@ namespace ArmISA
             updateRegMap(tmp_cpsr);
         }
 
+        void startup(ThreadContext *tc) {}
+
         typedef ArmISAParams Params;
 
         const Params *params() const;

src/arch/mips/isa.hh

@@ -157,6 +157,8 @@ namespace MipsISA
         static std::string miscRegNames[NumMiscRegs];
 
       public:
+        void startup(ThreadContext *tc) {}
+
         const Params *params() const;
 
         ISA(Params *p);

src/arch/power/isa.hh

@@ -98,6 +98,8 @@ class ISA : public SimObject
         return reg;
     }
 
+    void startup(ThreadContext *tc) {}
+
     const Params *params() const;
 
     ISA(Params *p);

src/arch/sparc/isa.hh

@@ -171,6 +171,8 @@ class ISA : public SimObject
 
     void unserialize(Checkpoint *cp, const std::string & section);
 
+    void startup(ThreadContext *tc) {}
+
   protected:
 
     bool isHyperPriv() { return hpstate.hpriv; }

src/arch/x86/isa.cc

@@ -387,6 +387,12 @@ ISA::unserialize(Checkpoint * cp, const std::string & section)
                      NULL);
 }
 
+void
+ISA::startup(ThreadContext *tc)
+{
+    tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]);
+}
+
 }
 
 X86ISA::ISA *

src/arch/x86/isa.hh

@@ -87,6 +87,7 @@ namespace X86ISA
 
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
+        void startup(ThreadContext *tc);
     };
 }
 

src/cpu/o3/cpu.cc

@@ -678,6 +678,9 @@ template <class Impl>
 void
 FullO3CPU<Impl>::startup()
 {
+    for (int tid = 0; tid < numThreads; ++tid)
+        isa[tid]->startup(threadContexts[tid]);
+
     fetch.startupStage();
     decode.startupStage();
     iew.startupStage();

src/cpu/simple/base.cc

@@ -515,6 +515,13 @@ BaseSimpleCPU::advancePC(Fault fault)
     }
 }
 
+void
+BaseSimpleCPU::startup()
+{
+    BaseCPU::startup();
+    thread->startup();
+}
+
 /*Fault
 BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
 {

src/cpu/simple/base.hh

@@ -172,6 +172,8 @@ class BaseSimpleCPU : public BaseCPU
     virtual void regStats();
     virtual void resetStats();
 
+    virtual void startup();
+
     // number of simulated instructions
     Counter numInst;
     Counter startNumInst;

src/cpu/simple_thread.cc

@@ -142,6 +142,12 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
     ::unserialize(*tc, cp, section);
 }
 
+void
+SimpleThread::startup()
+{
+    isa->startup(tc);
+}
+
 void
 SimpleThread::dumpFuncProfile()
 {

src/cpu/simple_thread.hh

@@ -150,6 +150,7 @@ class SimpleThread : public ThreadState
 
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);
+    void startup();
 
     /***************************************************************
      *  SimpleThread functions to provide CPU with access to various