diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 739b77286..1832f0222 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -106,6 +106,8 @@ namespace AlphaISA
         const Params *params() const;
 
         ISA(Params *p);
+
+        void startup(ThreadContext *tc) {}
     };
 }
 
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index f5fe5f834..12ecc4921 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -193,6 +193,8 @@ namespace ArmISA
             updateRegMap(tmp_cpsr);
         }
 
+        void startup(ThreadContext *tc) {}
+
         typedef ArmISAParams Params;
 
         const Params *params() const;
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 2169c0de0..5ae779a6c 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -157,6 +157,8 @@ namespace MipsISA
         static std::string miscRegNames[NumMiscRegs];
 
       public:
+        void startup(ThreadContext *tc) {}
+
         const Params *params() const;
 
         ISA(Params *p);
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index a989d33a7..f4e053d85 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -98,6 +98,8 @@ class ISA : public SimObject
         return reg;
     }
 
+    void startup(ThreadContext *tc) {}
+
     const Params *params() const;
 
     ISA(Params *p);
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 3dd9f6109..dac8a2095 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -171,6 +171,8 @@ class ISA : public SimObject
 
     void unserialize(Checkpoint *cp, const std::string & section);
 
+    void startup(ThreadContext *tc) {}
+
   protected:
 
     bool isHyperPriv() { return hpstate.hpriv; }
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 381dc5999..f65bc2392 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -387,6 +387,12 @@ ISA::unserialize(Checkpoint * cp, const std::string & section)
                      NULL);
 }
 
+void
+ISA::startup(ThreadContext *tc)
+{
+    tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]);
+}
+
 }
 
 X86ISA::ISA *
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 7c5330ca3..e87d747bc 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -87,6 +87,7 @@ namespace X86ISA
 
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
+        void startup(ThreadContext *tc);
     };
 }
 
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 18c536090..393b9a189 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -678,6 +678,9 @@ template <class Impl>
 void
 FullO3CPU<Impl>::startup()
 {
+    for (int tid = 0; tid < numThreads; ++tid)
+        isa[tid]->startup(threadContexts[tid]);
+
     fetch.startupStage();
     decode.startupStage();
     iew.startupStage();
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 13e08a6cb..4db1c6c10 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -515,6 +515,13 @@ BaseSimpleCPU::advancePC(Fault fault)
     }
 }
 
+void
+BaseSimpleCPU::startup()
+{
+    BaseCPU::startup();
+    thread->startup();
+}
+
 /*Fault
 BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
 {
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 18b97c42f..7e84dcc16 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -172,6 +172,8 @@ class BaseSimpleCPU : public BaseCPU
     virtual void regStats();
     virtual void resetStats();
 
+    virtual void startup();
+
     // number of simulated instructions
     Counter numInst;
     Counter startNumInst;
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 9cf8da7b4..77569aa68 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -142,6 +142,12 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
     ::unserialize(*tc, cp, section);
 }
 
+void
+SimpleThread::startup()
+{
+    isa->startup(tc);
+}
+
 void
 SimpleThread::dumpFuncProfile()
 {
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 6f1173b7f..d752ed105 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -150,6 +150,7 @@ class SimpleThread : public ThreadState
 
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);
+    void startup();
 
     /***************************************************************
      *  SimpleThread functions to provide CPU with access to various