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ARM: Combine some redundant cases in one of the data decode functions.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:18 -05:00
parent fcee2b3f31
commit 22f15ab94e
1 changed files with 2 additions and 10 deletions
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12
src/arch/arm/isa/formats/data.isa
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@ -1135,11 +1135,6 @@ def format Thumb16Misc() {{
return new AddImm(machInst, INTREG_SP, INTREG_SP, return new AddImm(machInst, INTREG_SP, INTREG_SP,
bits(machInst, 6, 0) << 2, true); bits(machInst, 6, 0) << 2, true);
} }
case 0x1:
return new Cbz(machInst,
(bits(machInst, 9) << 6) |
(bits(machInst, 7, 3) << 1),
(IntRegIndex)(uint32_t)bits(machInst, 2, 0));
case 0x2: case 0x2:
{ {
const IntRegIndex rd = const IntRegIndex rd =
@ -1157,6 +1152,7 @@ def format Thumb16Misc() {{
return new Uxtb(machInst, rd, 0, rm); return new Uxtb(machInst, rd, 0, rm);
} }
} }
case 0x1:
case 0x3: case 0x3:
return new Cbz(machInst, return new Cbz(machInst,
(bits(machInst, 9) << 6) | (bits(machInst, 9) << 6) |
@ -1182,11 +1178,6 @@ def format Thumb16Misc() {{
return new Cps(machInst, mods); return new Cps(machInst, mods);
} }
} }
case 0x9:
return new Cbnz(machInst,
(bits(machInst, 9) << 6) |
(bits(machInst, 7, 3) << 1),
(IntRegIndex)(uint32_t)bits(machInst, 2, 0));
case 0xa: case 0xa:
{ {
IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
@ -1203,6 +1194,7 @@ def format Thumb16Misc() {{
} }
} }
break; break;
case 0x9:
case 0xb: case 0xb:
return new Cbnz(machInst, return new Cbnz(machInst,
(bits(machInst, 9) << 6) | (bits(machInst, 9) << 6) |