mem, alpha: Move Alpha-specific request flags
Move Alpha-specific memory request flags to an architecture-specific header and map them to the architecture specific flag bit range.
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23b9792681
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@ -147,7 +147,7 @@ DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
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// on VPTE loads (instead of locking the registers until IPR_VA is
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// on VPTE loads (instead of locking the registers until IPR_VA is
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// read, like the EV5). The EV6 approach is cleaner and seems to
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// read, like the EV5). The EV6 approach is cleaner and seems to
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// work with EV5 PAL code, but not the other way around.
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// work with EV5 PAL code, but not the other way around.
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if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
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if (reqFlags.noneSet(AlphaRequestFlags::VPTE | Request::PREFETCH)) {
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// set VA register with faulting address
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// set VA register with faulting address
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tc->setMiscRegNoEffect(IPR_VA, vaddr);
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tc->setMiscRegNoEffect(IPR_VA, vaddr);
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@ -171,8 +171,8 @@ output decoder {{
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{
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{
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memAccessFlags.clear();
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memAccessFlags.clear();
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if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL);
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if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL);
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if (HW_LDST_ALT) memAccessFlags.set(Request::ALTMODE);
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if (HW_LDST_ALT) memAccessFlags.set(AlphaRequestFlags::ALTMODE);
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if (HW_LDST_VPTE) memAccessFlags.set(Request::VPTE);
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if (HW_LDST_VPTE) memAccessFlags.set(AlphaRequestFlags::VPTE);
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if (HW_LDST_LOCK) memAccessFlags.set(Request::LLSC);
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if (HW_LDST_LOCK) memAccessFlags.set(Request::LLSC);
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}
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}
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@ -466,7 +466,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
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}
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}
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if (PcPAL(req->getPC())) {
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if (PcPAL(req->getPC())) {
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mode = (req->getFlags() & Request::ALTMODE) ?
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mode = (req->getFlags() & AlphaRequestFlags::ALTMODE) ?
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(mode_type)ALT_MODE_AM(
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(mode_type)ALT_MODE_AM(
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tc->readMiscRegNoEffect(IPR_ALT_MODE))
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tc->readMiscRegNoEffect(IPR_ALT_MODE))
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: mode_kernel;
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: mode_kernel;
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@ -523,7 +523,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
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if (write) { write_misses++; } else { read_misses++; }
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if (write) { write_misses++; } else { read_misses++; }
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uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
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uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
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MM_STAT_DTB_MISS_MASK;
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MM_STAT_DTB_MISS_MASK;
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return (req->getFlags() & Request::VPTE) ?
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return (req->getFlags() & AlphaRequestFlags::VPTE) ?
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(Fault)(std::make_shared<PDtbMissFault>(req->getVaddr(),
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(Fault)(std::make_shared<PDtbMissFault>(req->getVaddr(),
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req->getFlags(),
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req->getFlags(),
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flags)) :
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flags)) :
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@ -51,6 +51,22 @@ enum annotes
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ITOUCH_ANNOTE = 0xffffffff
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ITOUCH_ANNOTE = 0xffffffff
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};
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};
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/**
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* Alpha-specific memory request flags
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*
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* These flags map to the architecture-specific lower 8 bits of the
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* flags field in Request.
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*/
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struct AlphaRequestFlags
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{
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typedef uint8_t ArchFlagsType;
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/** The request is an ALPHA VPTE pal access (hw_ld). */
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static const ArchFlagsType VPTE = 0x01;
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/** Use the alternate mode bits in ALPHA. */
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static const ArchFlagsType ALTMODE = 0x02;
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};
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} // namespace AlphaISA
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} // namespace AlphaISA
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#endif // __ARCH_ALPHA_TYPES_HH__
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#endif // __ARCH_ALPHA_TYPES_HH__
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@ -101,10 +101,6 @@ class Request
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static const FlagsType INST_FETCH = 0x00000100;
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static const FlagsType INST_FETCH = 0x00000100;
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/** The virtual address is also the physical address. */
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/** The virtual address is also the physical address. */
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static const FlagsType PHYSICAL = 0x00000200;
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static const FlagsType PHYSICAL = 0x00000200;
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/** The request is an ALPHA VPTE pal access (hw_ld). */
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static const FlagsType VPTE = 0x00000400;
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/** Use the alternate mode bits in ALPHA. */
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static const FlagsType ALTMODE = 0x00000800;
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/** The request is to an uncacheable address. */
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/** The request is to an uncacheable address. */
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static const FlagsType UNCACHEABLE = 0x00001000;
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static const FlagsType UNCACHEABLE = 0x00001000;
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/** This request is to a memory mapped register. */
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/** This request is to a memory mapped register. */
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