diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 2928f8d65..8bb781c13 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -147,7 +147,7 @@ DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
         // on VPTE loads (instead of locking the registers until IPR_VA is
         // read, like the EV5).  The EV6 approach is cleaner and seems to
         // work with EV5 PAL code, but not the other way around.
-        if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
+        if (reqFlags.noneSet(AlphaRequestFlags::VPTE | Request::PREFETCH)) {
             // set VA register with faulting address
             tc->setMiscRegNoEffect(IPR_VA, vaddr);
 
diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa
index 53e0d6193..3913fa82d 100644
--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -171,8 +171,8 @@ output decoder {{
     {
         memAccessFlags.clear();
         if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL);
-        if (HW_LDST_ALT)  memAccessFlags.set(Request::ALTMODE);
-        if (HW_LDST_VPTE) memAccessFlags.set(Request::VPTE);
+        if (HW_LDST_ALT)  memAccessFlags.set(AlphaRequestFlags::ALTMODE);
+        if (HW_LDST_VPTE) memAccessFlags.set(AlphaRequestFlags::VPTE);
         if (HW_LDST_LOCK) memAccessFlags.set(Request::LLSC);
     }
 
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 44326df40..bcf61f3bf 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -466,7 +466,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
     }
 
     if (PcPAL(req->getPC())) {
-        mode = (req->getFlags() & Request::ALTMODE) ?
+        mode = (req->getFlags() & AlphaRequestFlags::ALTMODE) ?
             (mode_type)ALT_MODE_AM(
                 tc->readMiscRegNoEffect(IPR_ALT_MODE))
             : mode_kernel;
@@ -523,7 +523,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
                 if (write) { write_misses++; } else { read_misses++; }
                 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
                     MM_STAT_DTB_MISS_MASK;
-                return (req->getFlags() & Request::VPTE) ?
+                return (req->getFlags() & AlphaRequestFlags::VPTE) ?
                     (Fault)(std::make_shared<PDtbMissFault>(req->getVaddr(),
                                                             req->getFlags(),
                                                             flags)) :
diff --git a/src/arch/alpha/types.hh b/src/arch/alpha/types.hh
index b1411d46e..aaa0f0b2a 100644
--- a/src/arch/alpha/types.hh
+++ b/src/arch/alpha/types.hh
@@ -51,6 +51,22 @@ enum annotes
     ITOUCH_ANNOTE = 0xffffffff
 };
 
+/**
+ * Alpha-specific memory request flags
+ *
+ * These flags map to the architecture-specific lower 8 bits of the
+ * flags field in Request.
+ */
+struct AlphaRequestFlags
+{
+    typedef uint8_t ArchFlagsType;
+
+    /** The request is an ALPHA VPTE pal access (hw_ld). */
+    static const ArchFlagsType VPTE    = 0x01;
+    /** Use the alternate mode bits in ALPHA. */
+    static const ArchFlagsType ALTMODE = 0x02;
+};
+
 } // namespace AlphaISA
 
 #endif // __ARCH_ALPHA_TYPES_HH__
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 82ede7e60..029636100 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -101,10 +101,6 @@ class Request
     static const FlagsType INST_FETCH                  = 0x00000100;
     /** The virtual address is also the physical address. */
     static const FlagsType PHYSICAL                    = 0x00000200;
-    /** The request is an ALPHA VPTE pal access (hw_ld). */
-    static const FlagsType VPTE                        = 0x00000400;
-    /** Use the alternate mode bits in ALPHA. */
-    static const FlagsType ALTMODE                     = 0x00000800;
     /** The request is to an uncacheable address. */
     static const FlagsType UNCACHEABLE                 = 0x00001000;
     /** This request is to a memory mapped register. */