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Automated merge with ssh://hg@m5sim.org/m5

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This commit is contained in:
Derek Hower 2009-08-09 13:59:14 -05:00
commit 1c3efb48ad
3 changed files with 19 additions and 15 deletions
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15
src/mem/protocol/MOESI_CMP_directory-dir.sm
View file

@ -101,7 +101,7 @@ machine(Directory, "Directory protocol")
}
structure(TBE, desc="...") {
Address address, desc="Address for this entry";
Address PhysicalAddress, desc="Physical address for this entry";
int Len, desc="Length of request";
DataBlock DataBlk, desc="DataBlk";
MachineID Requestor, desc="original requestor";
@ -245,9 +245,9 @@ machine(Directory, "Directory protocol")
} else if (in_msg.Type == CoherenceRequestType:PUTO_SHARERS) {
trigger(Event:PUTO_SHARERS, in_msg.Address);
} else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
trigger(Event:DMA_READ, in_msg.Address);
trigger(Event:DMA_READ, makeLineAddress(in_msg.Address));
} else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
trigger(Event:DMA_WRITE, in_msg.Address);
trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address));
} else {
error("Invalid message");
}
@ -527,12 +527,15 @@ machine(Directory, "Directory protocol")
}
action(l_writeDMADataToMemoryFromTBE, "\ll", desc="Write data from a DMA_WRITE to memory") {
directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(address), TBEs[address].Len);
directory[address].DataBlk.copyPartial(TBEs[address].DataBlk,
addressOffset(TBEs[address].PhysicalAddress),
TBEs[address].Len);
}
action(v_allocateTBE, "v", desc="Allocate TBE entry") {
peek (requestQueue_in, RequestMsg) {
TBEs.allocate(address);
TBEs[address].PhysicalAddress := in_msg.Address;
TBEs[address].Len := in_msg.Len;
TBEs[address].DataBlk := in_msg.DataBlk;
TBEs[address].Requestor := in_msg.Requestor;
@ -695,7 +698,7 @@ machine(Directory, "Directory protocol")
}
transition({MM, MO, MI, MIS, OS, OSS}, {GETS, GETX, PUTO, PUTO_SHARERS, PUTX, DMA_READ}) {
transition({MM, MO, MI, MIS, OS, OSS, XI_M, XI_U, OI_D}, {GETS, GETX, PUTO, PUTO_SHARERS, PUTX, DMA_READ, DMA_WRITE}) {
zz_recycleRequest;
}
@ -710,7 +713,7 @@ machine(Directory, "Directory protocol")
j_popIncomingUnblockQueue;
}
transition({IS, SS, OO}, {GETX, PUTO, PUTO_SHARERS, PUTX, DMA_READ}) {
transition({IS, SS, OO}, {GETX, PUTO, PUTO_SHARERS, PUTX, DMA_READ, DMA_WRITE}) {
zz_recycleRequest;
}

17
src/mem/protocol/MOESI_CMP_directory-dma.sm
View file

@ -83,9 +83,9 @@ machine(DMA, "DMA Controller")
if (dmaRequestQueue_in.isReady()) {
peek(dmaRequestQueue_in, SequencerMsg) {
if (in_msg.Type == SequencerRequestType:LD ) {
trigger(Event:ReadRequest, in_msg.PhysicalAddress);
trigger(Event:ReadRequest, in_msg.LineAddress);
} else if (in_msg.Type == SequencerRequestType:ST) {
trigger(Event:WriteRequest, in_msg.PhysicalAddress);
trigger(Event:WriteRequest, in_msg.LineAddress);
} else {
error("Invalid request type");
}
@ -97,11 +97,12 @@ machine(DMA, "DMA Controller")
if (dmaResponseQueue_in.isReady()) {
peek( dmaResponseQueue_in, ResponseMsg) {
if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
trigger(Event:DMA_Ack, in_msg.Address);
} else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
trigger(Event:Data, in_msg.Address);
trigger(Event:DMA_Ack, makeLineAddress(in_msg.Address));
} else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE ||
in_msg.Type == CoherenceResponseType:DATA) {
trigger(Event:Data, makeLineAddress(in_msg.Address));
} else if (in_msg.Type == CoherenceResponseType:ACK) {
trigger(Event:Inv_Ack, in_msg.Address);
trigger(Event:Inv_Ack, makeLineAddress(in_msg.Address));
} else {
error("Invalid response type");
}
@ -125,7 +126,7 @@ machine(DMA, "DMA Controller")
action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
peek(dmaRequestQueue_in, SequencerMsg) {
enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
out_msg.Address := address;
out_msg.Address := in_msg.PhysicalAddress;
out_msg.Type := CoherenceRequestType:DMA_READ;
out_msg.DataBlk := in_msg.DataBlk;
out_msg.Len := in_msg.Len;
@ -139,7 +140,7 @@ machine(DMA, "DMA Controller")
action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
peek(dmaRequestQueue_in, SequencerMsg) {
enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
out_msg.Address := address;
out_msg.Address := in_msg.PhysicalAddress;
out_msg.Type := CoherenceRequestType:DMA_WRITE;
out_msg.DataBlk := in_msg.DataBlk;
out_msg.Len := in_msg.Len;

2
src/mem/ruby/config/cfg.rb
View file

@ -11,7 +11,7 @@ end
def assert(condition,message)
unless condition
raise AssertionFailure, "Assertion failed: #{message}"
raise AssertionFailure, "\n\nAssertion failed: \n\n #{message}\n\n"
end
end