Regression: Use CPU clock and 32-byte width for L1-L2 bus

This patch changes the CoherentBus between the L1s and L2 to use the
CPU clock and also four times the width compared to the default
bus. The parameters are not intending to fit every single scenario,
but rather serve as a better startingpoint than what we previously
had.

Note that the scripts that do not use the addTwoLevelCacheHiearchy are
not affected by this change.

A separate patch will update the stats.

configs/common/CacheConfig.py

@@ -36,14 +36,22 @@ from O3_ARM_v7a import *
 
 def config_cache(options, system):
     if options.l2cache:
+        # Provide a clock for the L2 and the L1-to-L2 bus here as they
+        # are not connected using addTwoLevelCacheHierarchy. Use the
+        # same clock as the CPUs, and set the L1-to-L2 bus width to 32
+        # bytes (256 bits).
         if options.cpu_type == "arm_detailed":
-            system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc,
-                                block_size=options.cacheline_size)
+            system.l2 = O3_ARM_v7aL2(clock = options.clock,
+                                     size = options.l2_size,
+                                     assoc = options.l2_assoc,
+                                     block_size=options.cacheline_size)
         else:
-            system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
-                                block_size=options.cacheline_size)
+            system.l2 = L2Cache(clock = options.clock,
+                                size = options.l2_size,
+                                assoc = options.l2_assoc,
+                                block_size = options.cacheline_size)
 
-        system.tol2bus = CoherentBus()
+        system.tol2bus = CoherentBus(clock = options.clock, width = 32)
         system.l2.cpu_side = system.tol2bus.master
         system.l2.mem_side = system.membus.slave
 
@@ -51,11 +59,11 @@ def config_cache(options, system):
         if options.caches:
             if options.cpu_type == "arm_detailed":
                 icache = O3_ARM_v7a_ICache(size = options.l1i_size,
-                                     assoc = options.l1i_assoc,
-                                     block_size=options.cacheline_size)
+                                           assoc = options.l1i_assoc,
+                                           block_size=options.cacheline_size)
                 dcache = O3_ARM_v7a_DCache(size = options.l1d_size,
-                                     assoc = options.l1d_assoc,
-                                     block_size=options.cacheline_size)
+                                           assoc = options.l1d_assoc,
+                                           block_size=options.cacheline_size)
             else:
                 icache = L1Cache(size = options.l1i_size,
                                  assoc = options.l1i_assoc,
@@ -64,6 +72,8 @@ def config_cache(options, system):
                                  assoc = options.l1d_assoc,
                                  block_size=options.cacheline_size)
 
+            # When connecting the caches, the clock is also inherited
+            # from the CPU in question
             if buildEnv['TARGET_ISA'] == 'x86':
                 system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
                                                       PageTableWalkerCache(),

src/cpu/BaseCPU.py

@@ -236,7 +236,10 @@ class BaseCPU(MemObject):
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
-        self.toL2Bus = CoherentBus()
+        # Override the default bus clock of 1 GHz and uses the CPU
+        # clock for the L1-to-L2 bus, and also set a width of 32 bytes
+        # (256-bits), which is four times that of the default bus.
+        self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
         self.connectCachedPorts(self.toL2Bus)
         self.l2cache = l2c
         self.toL2Bus.master = self.l2cache.cpu_side