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ARM: Make sure some undefined thumb32 instructions fault.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:10 -05:00
parent 3caa75d53a
commit 1ada9d4880
4 changed files with 13 additions and 2 deletions
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3
src/arch/arm/isa/formats/branch.isa
View file

@ -240,6 +240,9 @@ def format Thumb32BranchesAndMiscCtrl() {{
} }
case 0x4: case 0x4:
{ {
if (bits(machInst, 0) == 1) {
return new Unknown(machInst);
}
const uint32_t s = bits(machInst, 26); const uint32_t s = bits(machInst, 26);
const uint32_t i1 = !(bits(machInst, 13) ^ s); const uint32_t i1 = !(bits(machInst, 13) ^ s);
const uint32_t i2 = !(bits(machInst, 11) ^ s); const uint32_t i2 = !(bits(machInst, 11) ^ s);

8
src/arch/arm/isa/formats/data.isa
View file

@ -579,6 +579,9 @@ def format Thumb32DataProcReg() {{
const uint32_t op1 = bits(machInst, 23, 20); const uint32_t op1 = bits(machInst, 23, 20);
const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
const uint32_t op2 = bits(machInst, 7, 4); const uint32_t op2 = bits(machInst, 7, 4);
if (bits(machInst, 15, 12) != 0xf) {
return new Unknown(machInst);
}
if (bits(op1, 3) != 1) { if (bits(op1, 3) != 1) {
if (op2 == 0) { if (op2 == 0) {
IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
@ -609,8 +612,9 @@ def format Thumb32DataProcReg() {{
return new MovRegRegCc(machInst, rd, return new MovRegRegCc(machInst, rd,
INTREG_ZERO, rn, rm, ROR); INTREG_ZERO, rn, rm, ROR);
} }
} } else if (bits(op2, 3) == 0) {
{ return new Unknown(machInst);
} else {
const IntRegIndex rd = const IntRegIndex rd =
(IntRegIndex)(uint32_t)bits(machInst, 11, 8); (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
const IntRegIndex rm = const IntRegIndex rm =

3
src/arch/arm/isa/formats/mem.isa
View file

@ -469,6 +469,9 @@ def format Thumb32StoreSingle() {{
uint32_t op2 = bits(machInst, 11, 6); uint32_t op2 = bits(machInst, 11, 6);
bool op2Puw = ((op2 & 0x24) == 0x24 || bool op2Puw = ((op2 & 0x24) == 0x24 ||
(op2 & 0x3c) == 0x30); (op2 & 0x3c) == 0x30);
if (RN == 0xf) {
return new Unknown(machInst);
}
if (op1 == 4) { if (op1 == 4) {
return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0); return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0);
} else if (op1 == 0 && op2Puw) { } else if (op1 == 0 && op2Puw) {

1
src/arch/arm/isa/formats/mult.isa
View file

@ -336,6 +336,7 @@ def format Thumb32LongMulMulAccAndDiv() {{
return new Smlsld(machInst, rdlo, rdhi, rn, rm); return new Smlsld(machInst, rdlo, rdhi, rn, rm);
} }
} }
break;
case 0x6: case 0x6:
if (op2 == 0) { if (op2 == 0) {
return new Umlal(machInst, rdlo, rdhi, rn, rm); return new Umlal(machInst, rdlo, rdhi, rn, rm);