alpha: get rid of all turbolaser remnants
This commit is contained in:
parent
374ba9bae3
commit
18a30524d6
|
@ -698,7 +698,7 @@ nonsticky_vars.AddVariables(
|
||||||
)
|
)
|
||||||
|
|
||||||
# These variables get exported to #defines in config/*.hh (see src/SConscript).
|
# These variables get exported to #defines in config/*.hh (see src/SConscript).
|
||||||
env.ExportVariables = ['FULL_SYSTEM', 'ALPHA_TLASER', 'USE_FENV', \
|
env.ExportVariables = ['FULL_SYSTEM', 'USE_FENV', \
|
||||||
'USE_MYSQL', 'NO_FAST_ALLOC', 'FAST_ALLOC_DEBUG', \
|
'USE_MYSQL', 'NO_FAST_ALLOC', 'FAST_ALLOC_DEBUG', \
|
||||||
'FAST_ALLOC_STATS', 'SS_COMPATIBLE_FP', \
|
'FAST_ALLOC_STATS', 'SS_COMPATIBLE_FP', \
|
||||||
'USE_CHECKER', 'TARGET_ISA', 'CP_ANNOTATE']
|
'USE_CHECKER', 'TARGET_ISA', 'CP_ANNOTATE']
|
||||||
|
|
|
@ -1,2 +1 @@
|
||||||
FULL_SYSTEM = 1
|
FULL_SYSTEM = 1
|
||||||
ALPHA_TLASER = 0
|
|
||||||
|
|
|
@ -1,2 +0,0 @@
|
||||||
FULL_SYSTEM = 1
|
|
||||||
ALPHA_TLASER = 1
|
|
|
@ -31,7 +31,3 @@
|
||||||
Import('*')
|
Import('*')
|
||||||
|
|
||||||
all_isa_list.append('alpha')
|
all_isa_list.append('alpha')
|
||||||
|
|
||||||
# Alpha can be compiled with Turbolaser support instead of Tsunami
|
|
||||||
sticky_vars.Add(BoolVariable('ALPHA_TLASER',
|
|
||||||
'Model Alpha TurboLaser platform (vs. Tsunami)', False))
|
|
||||||
|
|
|
@ -33,17 +33,11 @@
|
||||||
#ifndef __ARCH_ALPHA_EV5_HH__
|
#ifndef __ARCH_ALPHA_EV5_HH__
|
||||||
#define __ARCH_ALPHA_EV5_HH__
|
#define __ARCH_ALPHA_EV5_HH__
|
||||||
|
|
||||||
#include "config/alpha_tlaser.hh"
|
|
||||||
#include "arch/alpha/isa_traits.hh"
|
#include "arch/alpha/isa_traits.hh"
|
||||||
|
|
||||||
namespace AlphaISA {
|
namespace AlphaISA {
|
||||||
|
|
||||||
#if ALPHA_TLASER
|
|
||||||
const uint64_t AsnMask = ULL(0x7f);
|
|
||||||
#else
|
|
||||||
const uint64_t AsnMask = ULL(0xff);
|
const uint64_t AsnMask = ULL(0xff);
|
||||||
#endif
|
|
||||||
|
|
||||||
const int VAddrImplBits = 43;
|
const int VAddrImplBits = 43;
|
||||||
const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
|
const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
|
||||||
const Addr VAddrUnImplMask = ~VAddrImplMask;
|
const Addr VAddrUnImplMask = ~VAddrImplMask;
|
||||||
|
@ -53,13 +47,8 @@ inline Addr VAddrOffset(Addr a) { return a & PageOffset; }
|
||||||
inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
|
inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
|
||||||
inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
|
inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
|
||||||
|
|
||||||
#if ALPHA_TLASER
|
|
||||||
inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
|
|
||||||
const int PAddrImplBits = 40;
|
|
||||||
#else
|
|
||||||
inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
|
inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
|
||||||
const int PAddrImplBits = 44; // for Tsunami
|
const int PAddrImplBits = 44; // for Tsunami
|
||||||
#endif
|
|
||||||
const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
|
const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
|
||||||
const Addr PAddrUncachedBit39 = ULL(0x8000000000);
|
const Addr PAddrUncachedBit39 = ULL(0x8000000000);
|
||||||
const Addr PAddrUncachedBit40 = ULL(0x10000000000);
|
const Addr PAddrUncachedBit40 = ULL(0x10000000000);
|
||||||
|
@ -69,12 +58,10 @@ const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
|
||||||
inline Addr
|
inline Addr
|
||||||
Phys2K0Seg(Addr addr)
|
Phys2K0Seg(Addr addr)
|
||||||
{
|
{
|
||||||
#if !ALPHA_TLASER
|
|
||||||
if (addr & PAddrUncachedBit43) {
|
if (addr & PAddrUncachedBit43) {
|
||||||
addr &= PAddrUncachedMask;
|
addr &= PAddrUncachedMask;
|
||||||
addr |= PAddrUncachedBit40;
|
addr |= PAddrUncachedBit40;
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
return addr | K0SegBase;
|
return addr | K0SegBase;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -39,7 +39,6 @@
|
||||||
#include "base/inifile.hh"
|
#include "base/inifile.hh"
|
||||||
#include "base/str.hh"
|
#include "base/str.hh"
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
#include "config/alpha_tlaser.hh"
|
|
||||||
#include "cpu/thread_context.hh"
|
#include "cpu/thread_context.hh"
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
|
@ -215,12 +214,7 @@ TLB::checkCacheability(RequestPtr &req, bool itb)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#if ALPHA_TLASER
|
if (req->getPaddr() & PAddrUncachedBit43) {
|
||||||
if (req->getPaddr() & PAddrUncachedBit39)
|
|
||||||
#else
|
|
||||||
if (req->getPaddr() & PAddrUncachedBit43)
|
|
||||||
#endif
|
|
||||||
{
|
|
||||||
// IPR memory space not implemented
|
// IPR memory space not implemented
|
||||||
if (PAddrIprSpace(req->getPaddr())) {
|
if (PAddrIprSpace(req->getPaddr())) {
|
||||||
return new UnimpFault("IPR memory space not implemented!");
|
return new UnimpFault("IPR memory space not implemented!");
|
||||||
|
@ -228,11 +222,9 @@ TLB::checkCacheability(RequestPtr &req, bool itb)
|
||||||
// mark request as uncacheable
|
// mark request as uncacheable
|
||||||
req->setFlags(Request::UNCACHEABLE);
|
req->setFlags(Request::UNCACHEABLE);
|
||||||
|
|
||||||
#if !ALPHA_TLASER
|
|
||||||
// Clear bits 42:35 of the physical address (10-2 in
|
// Clear bits 42:35 of the physical address (10-2 in
|
||||||
// Tsunami manual)
|
// Tsunami manual)
|
||||||
req->setPaddr(req->getPaddr() & PAddrUncachedMask);
|
req->setPaddr(req->getPaddr() & PAddrUncachedMask);
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
// We shouldn't be able to read from an uncachable address in Alpha as
|
// We shouldn't be able to read from an uncachable address in Alpha as
|
||||||
// we don't have a ROM and we don't want to try to fetch from a device
|
// we don't have a ROM and we don't want to try to fetch from a device
|
||||||
|
@ -398,13 +390,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
|
||||||
|
|
||||||
// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
|
// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
|
||||||
// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
|
// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
|
||||||
#if ALPHA_TLASER
|
if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
|
||||||
if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
|
|
||||||
VAddrSpaceEV5(req->getVaddr()) == 2)
|
|
||||||
#else
|
|
||||||
if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
|
|
||||||
#endif
|
|
||||||
{
|
|
||||||
// only valid in kernel mode
|
// only valid in kernel mode
|
||||||
if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
|
if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
|
||||||
mode_kernel) {
|
mode_kernel) {
|
||||||
|
@ -414,14 +400,11 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
|
||||||
|
|
||||||
req->setPaddr(req->getVaddr() & PAddrImplMask);
|
req->setPaddr(req->getVaddr() & PAddrImplMask);
|
||||||
|
|
||||||
#if !ALPHA_TLASER
|
|
||||||
// sign extend the physical address properly
|
// sign extend the physical address properly
|
||||||
if (req->getPaddr() & PAddrUncachedBit40)
|
if (req->getPaddr() & PAddrUncachedBit40)
|
||||||
req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
|
req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
|
||||||
else
|
else
|
||||||
req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
|
req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
|
||||||
#endif
|
|
||||||
|
|
||||||
} else {
|
} else {
|
||||||
// not a physical address: need to look up pte
|
// not a physical address: need to look up pte
|
||||||
int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
|
int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
|
||||||
|
@ -495,13 +478,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
|
||||||
}
|
}
|
||||||
|
|
||||||
// Check for "superpage" mapping
|
// Check for "superpage" mapping
|
||||||
#if ALPHA_TLASER
|
if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
|
||||||
if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
|
|
||||||
VAddrSpaceEV5(req->getVaddr()) == 2)
|
|
||||||
#else
|
|
||||||
if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
|
|
||||||
#endif
|
|
||||||
{
|
|
||||||
// only valid in kernel mode
|
// only valid in kernel mode
|
||||||
if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
|
if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
|
||||||
mode_kernel) {
|
mode_kernel) {
|
||||||
|
@ -515,14 +492,11 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
|
||||||
|
|
||||||
req->setPaddr(req->getVaddr() & PAddrImplMask);
|
req->setPaddr(req->getVaddr() & PAddrImplMask);
|
||||||
|
|
||||||
#if !ALPHA_TLASER
|
|
||||||
// sign extend the physical address properly
|
// sign extend the physical address properly
|
||||||
if (req->getPaddr() & PAddrUncachedBit40)
|
if (req->getPaddr() & PAddrUncachedBit40)
|
||||||
req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
|
req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
|
||||||
else
|
else
|
||||||
req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
|
req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
|
||||||
#endif
|
|
||||||
|
|
||||||
} else {
|
} else {
|
||||||
if (write)
|
if (write)
|
||||||
write_accesses++;
|
write_accesses++;
|
||||||
|
|
|
@ -38,8 +38,3 @@ class Uart(BasicPioDevice):
|
||||||
|
|
||||||
class Uart8250(Uart):
|
class Uart8250(Uart):
|
||||||
type = 'Uart8250'
|
type = 'Uart8250'
|
||||||
|
|
||||||
if build_env['ALPHA_TLASER']:
|
|
||||||
class Uart8530(Uart):
|
|
||||||
type = 'Uart8530'
|
|
||||||
|
|
||||||
|
|
|
@ -251,13 +251,12 @@ def test_builder(env, ref_dir):
|
||||||
configs = []
|
configs = []
|
||||||
if env['FULL_SYSTEM']:
|
if env['FULL_SYSTEM']:
|
||||||
if env['TARGET_ISA'] == 'alpha':
|
if env['TARGET_ISA'] == 'alpha':
|
||||||
if not env['ALPHA_TLASER']:
|
configs += ['tsunami-simple-atomic',
|
||||||
configs += ['tsunami-simple-atomic',
|
'tsunami-simple-timing',
|
||||||
'tsunami-simple-timing',
|
'tsunami-simple-atomic-dual',
|
||||||
'tsunami-simple-atomic-dual',
|
'tsunami-simple-timing-dual',
|
||||||
'tsunami-simple-timing-dual',
|
'twosys-tsunami-simple-atomic',
|
||||||
'twosys-tsunami-simple-atomic',
|
'tsunami-o3', 'tsunami-o3-dual']
|
||||||
'tsunami-o3', 'tsunami-o3-dual']
|
|
||||||
if env['TARGET_ISA'] == 'sparc':
|
if env['TARGET_ISA'] == 'sparc':
|
||||||
configs += ['t1000-simple-atomic',
|
configs += ['t1000-simple-atomic',
|
||||||
't1000-simple-timing']
|
't1000-simple-timing']
|
||||||
|
|
Loading…
Reference in a new issue