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use string name to figure out if we have a "AndLink" instruction

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arch/mips/isa/operands.isa:
    uq -> uw

--HG--
extra : convert_revision : eeac6dba813de8174d080a5fa9b5a396b345113a
This commit is contained in:
Korey Sewell 2006-02-18 04:17:11 -05:00
parent 6bf71f96f3
commit 159e334531
2 changed files with 9 additions and 7 deletions
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12
arch/mips/isa/formats/branch.isa
View file

@ -213,10 +213,11 @@ def template JumpOrBranchDecode {{
}}; }};
def format Branch(code,*flags) {{ def format Branch(code,*flags) {{
code = 'bool cond;\n' + code + '\n' code = 'bool cond;\n\t' + code + '\n'
if flags == 'IsLink': strlen = len(name)
code += 'R31 = NPC + 8\n' if name[strlen-2:] == 'al':
code += 'R31 = NPC + 8;\n'
code += '\nif (cond) NPC = NPC + disp;\n'; code += '\nif (cond) NPC = NPC + disp;\n';
@ -231,8 +232,9 @@ def format Branch(code,*flags) {{
def format BranchLikely(code,*flags) {{ def format BranchLikely(code,*flags) {{
code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n'; code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
if flags == 'IsLink': strlen = len(name)
code += 'R31 = NPC + 8\n' if name[strlen-3:] == 'all':
code += 'R31 = NPC + 8;\n'
iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
('IsDirectControl', 'IsCondControl','IsCondDelaySlot')) ('IsDirectControl', 'IsCondControl','IsCondDelaySlot'))

4
arch/mips/isa/operands.isa
View file

@ -26,10 +26,10 @@ def operands {{
'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4) 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), #'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
# The next two are hacks for non-full-system call-pal emulation # The next two are hacks for non-full-system call-pal emulation
#'R0': ('IntReg', 'uq', '0', None, 1), #'R0': ('IntReg', 'uq', '0', None, 1),
#'R16': ('IntReg', 'uq', '16', None, 1) #'R31': ('IntReg', 'uw', '31', None, 1)
}}; }};